Path: blob/master/drivers/hid/amd-sfh-hid/amd_sfh_pcie.h
26282 views
/* SPDX-License-Identifier: GPL-2.0-or-later */1/*2* AMD MP2 PCIe communication driver3* Copyright 2020-2021 Advanced Micro Devices, Inc.4* Authors: Shyam Sundar S K <[email protected]>5* Sandeep Singh <[email protected]>6* Basavaraj Natikar <[email protected]>7*/89#ifndef PCIE_MP2_AMD_H10#define PCIE_MP2_AMD_H1112#include "amd_sfh_common.h"1314/* MP2 C2P Message Registers */15#define AMD_C2P_MSG0 0x1050016#define AMD_C2P_MSG1 0x1050417#define AMD_C2P_MSG2 0x105081819/* MP2 P2C Message Registers */20#define AMD_P2C_MSG3 0x1068C /* Supported Sensors info */2122#define V2_STATUS 0x22324#define HPD_IDX 1625#define ACS_IDX 222627#define SENSOR_DISCOVERY_STATUS_MASK GENMASK(5, 3)28#define SENSOR_DISCOVERY_STATUS_SHIFT 32930/* SFH Command register */31union sfh_cmd_base {32u32 ul;33struct {34u32 cmd_id : 8;35u32 sensor_id : 8;36u32 period : 16;37} s;38struct {39u32 cmd_id : 4;40u32 intr_disable : 1;41u32 rsvd1 : 3;42u32 length : 7;43u32 mem_type : 1;44u32 sensor_id : 8;45u32 period : 8;46} cmd_v2;47};4849union cmd_response {50u32 resp;51struct {52u32 status : 2;53u32 out_in_c2p : 1;54u32 rsvd1 : 1;55u32 response : 4;56u32 sub_cmd : 8;57u32 sensor_id : 6;58u32 rsvd2 : 10;59} response_v2;60};6162union sfh_cmd_param {63u32 ul;64struct {65u32 buf_layout : 2;66u32 buf_length : 6;67u32 rsvd : 24;68} s;69};7071struct sfh_cmd_reg {72union sfh_cmd_base cmd_base;73union sfh_cmd_param cmd_param;74phys_addr_t phys_addr;75};7677enum sensor_idx {78accel_idx = 0,79gyro_idx = 1,80mag_idx = 2,81op_idx = 15,82als_idx = 1983};8485enum mem_use_type {86USE_DRAM,87USE_C2P_REG,88};8990struct hpd_status {91union {92struct {93u32 object_distance : 16;94u32 probablity : 8;95u32 human_presence_actual : 4;96u32 human_presence_report : 4;97} shpd;98u32 val;99};100};101102int amd_mp2_get_sensor_num(struct amd_mp2_dev *privdata, u8 *sensor_id);103int amd_sfh_hid_client_init(struct amd_mp2_dev *privdata);104int amd_sfh_hid_client_deinit(struct amd_mp2_dev *privdata);105void amd_sfh_set_desc_ops(struct amd_mp2_ops *mp2_ops);106107#endif108109110