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torvalds
GitHub Repository: torvalds/linux
Path: blob/master/drivers/net/wireless/realtek/rtw88/main.c
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1
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2
/* Copyright(c) 2018-2019 Realtek Corporation
3
*/
4
5
#include <linux/devcoredump.h>
6
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#include "main.h"
8
#include "regd.h"
9
#include "fw.h"
10
#include "ps.h"
11
#include "sec.h"
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#include "mac.h"
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#include "coex.h"
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#include "phy.h"
15
#include "reg.h"
16
#include "efuse.h"
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#include "tx.h"
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#include "debug.h"
19
#include "bf.h"
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#include "sar.h"
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#include "sdio.h"
22
#include "led.h"
23
24
bool rtw_disable_lps_deep_mode;
25
EXPORT_SYMBOL(rtw_disable_lps_deep_mode);
26
bool rtw_bf_support = true;
27
unsigned int rtw_debug_mask;
28
EXPORT_SYMBOL(rtw_debug_mask);
29
/* EDCCA is enabled during normal behavior. For debugging purpose in
30
* a noisy environment, it can be disabled via edcca debugfs. Because
31
* all rtw88 devices will probably be affected if environment is noisy,
32
* rtw_edcca_enabled is just declared by driver instead of by device.
33
* So, turning it off will take effect for all rtw88 devices before
34
* there is a tough reason to maintain rtw_edcca_enabled by device.
35
*/
36
bool rtw_edcca_enabled = true;
37
38
module_param_named(disable_lps_deep, rtw_disable_lps_deep_mode, bool, 0644);
39
module_param_named(support_bf, rtw_bf_support, bool, 0644);
40
module_param_named(debug_mask, rtw_debug_mask, uint, 0644);
41
42
MODULE_PARM_DESC(disable_lps_deep, "Set Y to disable Deep PS");
43
MODULE_PARM_DESC(support_bf, "Set Y to enable beamformee support");
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MODULE_PARM_DESC(debug_mask, "Debugging mask");
45
46
static struct ieee80211_channel rtw_channeltable_2g[] = {
47
{.center_freq = 2412, .hw_value = 1,},
48
{.center_freq = 2417, .hw_value = 2,},
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{.center_freq = 2422, .hw_value = 3,},
50
{.center_freq = 2427, .hw_value = 4,},
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{.center_freq = 2432, .hw_value = 5,},
52
{.center_freq = 2437, .hw_value = 6,},
53
{.center_freq = 2442, .hw_value = 7,},
54
{.center_freq = 2447, .hw_value = 8,},
55
{.center_freq = 2452, .hw_value = 9,},
56
{.center_freq = 2457, .hw_value = 10,},
57
{.center_freq = 2462, .hw_value = 11,},
58
{.center_freq = 2467, .hw_value = 12,},
59
{.center_freq = 2472, .hw_value = 13,},
60
{.center_freq = 2484, .hw_value = 14,},
61
};
62
63
static struct ieee80211_channel rtw_channeltable_5g[] = {
64
{.center_freq = 5180, .hw_value = 36,},
65
{.center_freq = 5200, .hw_value = 40,},
66
{.center_freq = 5220, .hw_value = 44,},
67
{.center_freq = 5240, .hw_value = 48,},
68
{.center_freq = 5260, .hw_value = 52,},
69
{.center_freq = 5280, .hw_value = 56,},
70
{.center_freq = 5300, .hw_value = 60,},
71
{.center_freq = 5320, .hw_value = 64,},
72
{.center_freq = 5500, .hw_value = 100,},
73
{.center_freq = 5520, .hw_value = 104,},
74
{.center_freq = 5540, .hw_value = 108,},
75
{.center_freq = 5560, .hw_value = 112,},
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{.center_freq = 5580, .hw_value = 116,},
77
{.center_freq = 5600, .hw_value = 120,},
78
{.center_freq = 5620, .hw_value = 124,},
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{.center_freq = 5640, .hw_value = 128,},
80
{.center_freq = 5660, .hw_value = 132,},
81
{.center_freq = 5680, .hw_value = 136,},
82
{.center_freq = 5700, .hw_value = 140,},
83
{.center_freq = 5720, .hw_value = 144,},
84
{.center_freq = 5745, .hw_value = 149,},
85
{.center_freq = 5765, .hw_value = 153,},
86
{.center_freq = 5785, .hw_value = 157,},
87
{.center_freq = 5805, .hw_value = 161,},
88
{.center_freq = 5825, .hw_value = 165,
89
.flags = IEEE80211_CHAN_NO_HT40MINUS},
90
};
91
92
static struct ieee80211_rate rtw_ratetable[] = {
93
{.bitrate = 10, .hw_value = 0x00,},
94
{.bitrate = 20, .hw_value = 0x01,},
95
{.bitrate = 55, .hw_value = 0x02,},
96
{.bitrate = 110, .hw_value = 0x03,},
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{.bitrate = 60, .hw_value = 0x04,},
98
{.bitrate = 90, .hw_value = 0x05,},
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{.bitrate = 120, .hw_value = 0x06,},
100
{.bitrate = 180, .hw_value = 0x07,},
101
{.bitrate = 240, .hw_value = 0x08,},
102
{.bitrate = 360, .hw_value = 0x09,},
103
{.bitrate = 480, .hw_value = 0x0a,},
104
{.bitrate = 540, .hw_value = 0x0b,},
105
};
106
107
static const struct ieee80211_iface_limit rtw_iface_limits[] = {
108
{
109
.max = 1,
110
.types = BIT(NL80211_IFTYPE_STATION),
111
},
112
{
113
.max = 1,
114
.types = BIT(NL80211_IFTYPE_AP),
115
}
116
};
117
118
static const struct ieee80211_iface_combination rtw_iface_combs[] = {
119
{
120
.limits = rtw_iface_limits,
121
.n_limits = ARRAY_SIZE(rtw_iface_limits),
122
.max_interfaces = 2,
123
.num_different_channels = 1,
124
}
125
};
126
127
u16 rtw_desc_to_bitrate(u8 desc_rate)
128
{
129
struct ieee80211_rate rate;
130
131
if (WARN(desc_rate >= ARRAY_SIZE(rtw_ratetable), "invalid desc rate\n"))
132
return 0;
133
134
rate = rtw_ratetable[desc_rate];
135
136
return rate.bitrate;
137
}
138
139
static const struct ieee80211_supported_band rtw_band_2ghz = {
140
.band = NL80211_BAND_2GHZ,
141
142
.channels = rtw_channeltable_2g,
143
.n_channels = ARRAY_SIZE(rtw_channeltable_2g),
144
145
.bitrates = rtw_ratetable,
146
.n_bitrates = ARRAY_SIZE(rtw_ratetable),
147
148
.ht_cap = {0},
149
.vht_cap = {0},
150
};
151
152
static const struct ieee80211_supported_band rtw_band_5ghz = {
153
.band = NL80211_BAND_5GHZ,
154
155
.channels = rtw_channeltable_5g,
156
.n_channels = ARRAY_SIZE(rtw_channeltable_5g),
157
158
/* 5G has no CCK rates */
159
.bitrates = rtw_ratetable + 4,
160
.n_bitrates = ARRAY_SIZE(rtw_ratetable) - 4,
161
162
.ht_cap = {0},
163
.vht_cap = {0},
164
};
165
166
struct rtw_watch_dog_iter_data {
167
struct rtw_dev *rtwdev;
168
struct rtw_vif *rtwvif;
169
};
170
171
static void rtw_dynamic_csi_rate(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif)
172
{
173
struct rtw_bf_info *bf_info = &rtwdev->bf_info;
174
u8 fix_rate_enable = 0;
175
u8 new_csi_rate_idx;
176
177
if (rtwvif->bfee.role != RTW_BFEE_SU &&
178
rtwvif->bfee.role != RTW_BFEE_MU)
179
return;
180
181
rtw_chip_cfg_csi_rate(rtwdev, rtwdev->dm_info.min_rssi,
182
bf_info->cur_csi_rpt_rate,
183
fix_rate_enable, &new_csi_rate_idx);
184
185
if (new_csi_rate_idx != bf_info->cur_csi_rpt_rate)
186
bf_info->cur_csi_rpt_rate = new_csi_rate_idx;
187
}
188
189
static void rtw_vif_watch_dog_iter(void *data, struct ieee80211_vif *vif)
190
{
191
struct rtw_watch_dog_iter_data *iter_data = data;
192
struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
193
194
if (vif->type == NL80211_IFTYPE_STATION)
195
if (vif->cfg.assoc)
196
iter_data->rtwvif = rtwvif;
197
198
rtw_dynamic_csi_rate(iter_data->rtwdev, rtwvif);
199
200
rtwvif->stats.tx_unicast = 0;
201
rtwvif->stats.rx_unicast = 0;
202
rtwvif->stats.tx_cnt = 0;
203
rtwvif->stats.rx_cnt = 0;
204
}
205
206
static void rtw_sw_beacon_loss_check(struct rtw_dev *rtwdev,
207
struct rtw_vif *rtwvif, int received_beacons)
208
{
209
int watchdog_delay = 2000000 / 1024; /* TU */
210
int beacon_int, expected_beacons;
211
212
if (rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_BCN_FILTER) || !rtwvif)
213
return;
214
215
beacon_int = rtwvif_to_vif(rtwvif)->bss_conf.beacon_int;
216
expected_beacons = DIV_ROUND_UP(watchdog_delay, beacon_int);
217
218
rtwdev->beacon_loss = received_beacons < expected_beacons / 2;
219
}
220
221
/* process TX/RX statistics periodically for hardware,
222
* the information helps hardware to enhance performance
223
*/
224
static void rtw_watch_dog_work(struct work_struct *work)
225
{
226
struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
227
watch_dog_work.work);
228
struct rtw_traffic_stats *stats = &rtwdev->stats;
229
struct rtw_watch_dog_iter_data data = {};
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bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
231
int received_beacons = rtwdev->dm_info.cur_pkt_count.num_bcn_pkt;
232
u32 tx_unicast_mbps, rx_unicast_mbps;
233
bool ps_active;
234
235
mutex_lock(&rtwdev->mutex);
236
237
if (!test_bit(RTW_FLAG_RUNNING, rtwdev->flags))
238
goto unlock;
239
240
ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
241
RTW_WATCH_DOG_DELAY_TIME);
242
243
if (rtwdev->stats.tx_cnt > 100 || rtwdev->stats.rx_cnt > 100)
244
set_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
245
else
246
clear_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags);
247
248
if (busy_traffic != test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags))
249
rtw_coex_wl_status_change_notify(rtwdev, 0);
250
251
if (stats->tx_cnt > RTW_LPS_THRESHOLD ||
252
stats->rx_cnt > RTW_LPS_THRESHOLD)
253
ps_active = true;
254
else
255
ps_active = false;
256
257
tx_unicast_mbps = stats->tx_unicast >> RTW_TP_SHIFT;
258
rx_unicast_mbps = stats->rx_unicast >> RTW_TP_SHIFT;
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ewma_tp_add(&stats->tx_ewma_tp, tx_unicast_mbps);
261
ewma_tp_add(&stats->rx_ewma_tp, rx_unicast_mbps);
262
stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
263
stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
264
265
/* reset tx/rx statictics */
266
stats->tx_unicast = 0;
267
stats->rx_unicast = 0;
268
stats->tx_cnt = 0;
269
stats->rx_cnt = 0;
270
271
if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
272
goto unlock;
273
274
/* make sure BB/RF is working for dynamic mech */
275
rtw_leave_lps(rtwdev);
276
rtw_coex_wl_status_check(rtwdev);
277
rtw_coex_query_bt_hid_list(rtwdev);
278
rtw_coex_active_query_bt_info(rtwdev);
279
280
rtw_phy_dynamic_mechanism(rtwdev);
281
282
rtw_hci_dynamic_rx_agg(rtwdev,
283
tx_unicast_mbps >= 1 || rx_unicast_mbps >= 1);
284
285
data.rtwdev = rtwdev;
286
/* rtw_iterate_vifs internally uses an atomic iterator which is needed
287
* to avoid taking local->iflist_mtx mutex
288
*/
289
rtw_iterate_vifs(rtwdev, rtw_vif_watch_dog_iter, &data);
290
291
rtw_sw_beacon_loss_check(rtwdev, data.rtwvif, received_beacons);
292
293
/* fw supports only one station associated to enter lps, if there are
294
* more than two stations associated to the AP, then we can not enter
295
* lps, because fw does not handle the overlapped beacon interval
296
*
297
* rtw_recalc_lps() iterate vifs and determine if driver can enter
298
* ps by vif->type and vif->cfg.ps, all we need to do here is to
299
* get that vif and check if device is having traffic more than the
300
* threshold.
301
*/
302
if (rtwdev->ps_enabled && data.rtwvif && !ps_active &&
303
!rtwdev->beacon_loss && !rtwdev->ap_active)
304
rtw_enter_lps(rtwdev, data.rtwvif->port);
305
306
rtwdev->watch_dog_cnt++;
307
308
unlock:
309
mutex_unlock(&rtwdev->mutex);
310
}
311
312
static void rtw_c2h_work(struct work_struct *work)
313
{
314
struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, c2h_work);
315
struct sk_buff *skb, *tmp;
316
317
skb_queue_walk_safe(&rtwdev->c2h_queue, skb, tmp) {
318
skb_unlink(skb, &rtwdev->c2h_queue);
319
rtw_fw_c2h_cmd_handle(rtwdev, skb);
320
dev_kfree_skb_any(skb);
321
}
322
}
323
324
static void rtw_ips_work(struct work_struct *work)
325
{
326
struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ips_work);
327
328
mutex_lock(&rtwdev->mutex);
329
if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)
330
rtw_enter_ips(rtwdev);
331
mutex_unlock(&rtwdev->mutex);
332
}
333
334
static void rtw_sta_rc_work(struct work_struct *work)
335
{
336
struct rtw_sta_info *si = container_of(work, struct rtw_sta_info,
337
rc_work);
338
struct rtw_dev *rtwdev = si->rtwdev;
339
340
mutex_lock(&rtwdev->mutex);
341
rtw_update_sta_info(rtwdev, si, true);
342
mutex_unlock(&rtwdev->mutex);
343
}
344
345
int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
346
struct ieee80211_vif *vif)
347
{
348
struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
349
struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
350
int i;
351
352
if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
353
si->mac_id = rtwvif->mac_id;
354
} else {
355
si->mac_id = rtw_acquire_macid(rtwdev);
356
if (si->mac_id >= RTW_MAX_MAC_ID_NUM)
357
return -ENOSPC;
358
}
359
360
si->rtwdev = rtwdev;
361
si->sta = sta;
362
si->vif = vif;
363
si->init_ra_lv = 1;
364
ewma_rssi_init(&si->avg_rssi);
365
for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
366
rtw_txq_init(rtwdev, sta->txq[i]);
367
INIT_WORK(&si->rc_work, rtw_sta_rc_work);
368
369
rtw_update_sta_info(rtwdev, si, true);
370
rtw_fw_media_status_report(rtwdev, si->mac_id, true);
371
372
rtwdev->sta_cnt++;
373
rtwdev->beacon_loss = false;
374
rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM joined with macid %d\n",
375
sta->addr, si->mac_id);
376
377
return 0;
378
}
379
380
void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta,
381
bool fw_exist)
382
{
383
struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
384
struct ieee80211_vif *vif = si->vif;
385
int i;
386
387
cancel_work_sync(&si->rc_work);
388
389
if (vif->type != NL80211_IFTYPE_STATION || sta->tdls)
390
rtw_release_macid(rtwdev, si->mac_id);
391
if (fw_exist)
392
rtw_fw_media_status_report(rtwdev, si->mac_id, false);
393
394
for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
395
rtw_txq_cleanup(rtwdev, sta->txq[i]);
396
397
kfree(si->mask);
398
399
rtwdev->sta_cnt--;
400
rtw_dbg(rtwdev, RTW_DBG_STATE, "sta %pM with macid %d left\n",
401
sta->addr, si->mac_id);
402
}
403
404
struct rtw_fwcd_hdr {
405
u32 item;
406
u32 size;
407
u32 padding1;
408
u32 padding2;
409
} __packed;
410
411
static int rtw_fwcd_prep(struct rtw_dev *rtwdev)
412
{
413
const struct rtw_chip_info *chip = rtwdev->chip;
414
struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
415
const struct rtw_fwcd_segs *segs = chip->fwcd_segs;
416
u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr);
417
u8 i;
418
419
if (segs) {
420
prep_size += segs->num * sizeof(struct rtw_fwcd_hdr);
421
422
for (i = 0; i < segs->num; i++)
423
prep_size += segs->segs[i];
424
}
425
426
desc->data = vmalloc(prep_size);
427
if (!desc->data)
428
return -ENOMEM;
429
430
desc->size = prep_size;
431
desc->next = desc->data;
432
433
return 0;
434
}
435
436
static u8 *rtw_fwcd_next(struct rtw_dev *rtwdev, u32 item, u32 size)
437
{
438
struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
439
struct rtw_fwcd_hdr *hdr;
440
u8 *next;
441
442
if (!desc->data) {
443
rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared successfully\n");
444
return NULL;
445
}
446
447
next = desc->next + sizeof(struct rtw_fwcd_hdr);
448
if (next - desc->data + size > desc->size) {
449
rtw_dbg(rtwdev, RTW_DBG_FW, "fwcd isn't prepared enough\n");
450
return NULL;
451
}
452
453
hdr = (struct rtw_fwcd_hdr *)(desc->next);
454
hdr->item = item;
455
hdr->size = size;
456
hdr->padding1 = 0x01234567;
457
hdr->padding2 = 0x89abcdef;
458
desc->next = next + size;
459
460
return next;
461
}
462
463
static void rtw_fwcd_dump(struct rtw_dev *rtwdev)
464
{
465
struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
466
467
rtw_dbg(rtwdev, RTW_DBG_FW, "dump fwcd\n");
468
469
/* Data will be freed after lifetime of device coredump. After calling
470
* dev_coredump, data is supposed to be handled by the device coredump
471
* framework. Note that a new dump will be discarded if a previous one
472
* hasn't been released yet.
473
*/
474
dev_coredumpv(rtwdev->dev, desc->data, desc->size, GFP_KERNEL);
475
}
476
477
static void rtw_fwcd_free(struct rtw_dev *rtwdev, bool free_self)
478
{
479
struct rtw_fwcd_desc *desc = &rtwdev->fw.fwcd_desc;
480
481
if (free_self) {
482
rtw_dbg(rtwdev, RTW_DBG_FW, "free fwcd by self\n");
483
vfree(desc->data);
484
}
485
486
desc->data = NULL;
487
desc->next = NULL;
488
}
489
490
static int rtw_fw_dump_crash_log(struct rtw_dev *rtwdev)
491
{
492
u32 size = rtwdev->chip->fw_rxff_size;
493
u32 *buf;
494
u8 seq;
495
496
buf = (u32 *)rtw_fwcd_next(rtwdev, RTW_FWCD_TLV, size);
497
if (!buf)
498
return -ENOMEM;
499
500
if (rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0, size, buf)) {
501
rtw_dbg(rtwdev, RTW_DBG_FW, "dump fw fifo fail\n");
502
return -EINVAL;
503
}
504
505
if (GET_FW_DUMP_LEN(buf) == 0) {
506
rtw_dbg(rtwdev, RTW_DBG_FW, "fw crash dump's length is 0\n");
507
return -EINVAL;
508
}
509
510
seq = GET_FW_DUMP_SEQ(buf);
511
if (seq > 0) {
512
rtw_dbg(rtwdev, RTW_DBG_FW,
513
"fw crash dump's seq is wrong: %d\n", seq);
514
return -EINVAL;
515
}
516
517
return 0;
518
}
519
520
int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size,
521
u32 fwcd_item)
522
{
523
u32 rxff = rtwdev->chip->fw_rxff_size;
524
u32 dump_size, done_size = 0;
525
u8 *buf;
526
int ret;
527
528
buf = rtw_fwcd_next(rtwdev, fwcd_item, size);
529
if (!buf)
530
return -ENOMEM;
531
532
while (size) {
533
dump_size = size > rxff ? rxff : size;
534
535
ret = rtw_ddma_to_fw_fifo(rtwdev, ocp_src + done_size,
536
dump_size);
537
if (ret) {
538
rtw_err(rtwdev,
539
"ddma fw 0x%x [+0x%x] to fw fifo fail\n",
540
ocp_src, done_size);
541
return ret;
542
}
543
544
ret = rtw_fw_dump_fifo(rtwdev, RTW_FW_FIFO_SEL_RXBUF_FW, 0,
545
dump_size, (u32 *)(buf + done_size));
546
if (ret) {
547
rtw_err(rtwdev,
548
"dump fw 0x%x [+0x%x] from fw fifo fail\n",
549
ocp_src, done_size);
550
return ret;
551
}
552
553
size -= dump_size;
554
done_size += dump_size;
555
}
556
557
return 0;
558
}
559
EXPORT_SYMBOL(rtw_dump_fw);
560
561
int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size)
562
{
563
u8 *buf;
564
u32 i;
565
566
if (addr & 0x3) {
567
WARN(1, "should be 4-byte aligned, addr = 0x%08x\n", addr);
568
return -EINVAL;
569
}
570
571
buf = rtw_fwcd_next(rtwdev, RTW_FWCD_REG, size);
572
if (!buf)
573
return -ENOMEM;
574
575
for (i = 0; i < size; i += 4)
576
*(u32 *)(buf + i) = rtw_read32(rtwdev, addr + i);
577
578
return 0;
579
}
580
EXPORT_SYMBOL(rtw_dump_reg);
581
582
void rtw_vif_assoc_changed(struct rtw_vif *rtwvif,
583
struct ieee80211_bss_conf *conf)
584
{
585
struct ieee80211_vif *vif = NULL;
586
587
if (conf)
588
vif = container_of(conf, struct ieee80211_vif, bss_conf);
589
590
if (conf && vif->cfg.assoc) {
591
rtwvif->aid = vif->cfg.aid;
592
rtwvif->net_type = RTW_NET_MGD_LINKED;
593
} else {
594
rtwvif->aid = 0;
595
rtwvif->net_type = RTW_NET_NO_LINK;
596
}
597
}
598
599
static void rtw_reset_key_iter(struct ieee80211_hw *hw,
600
struct ieee80211_vif *vif,
601
struct ieee80211_sta *sta,
602
struct ieee80211_key_conf *key,
603
void *data)
604
{
605
struct rtw_dev *rtwdev = (struct rtw_dev *)data;
606
struct rtw_sec_desc *sec = &rtwdev->sec;
607
608
rtw_sec_clear_cam(rtwdev, sec, key->hw_key_idx);
609
}
610
611
static void rtw_reset_sta_iter(void *data, struct ieee80211_sta *sta)
612
{
613
struct rtw_dev *rtwdev = (struct rtw_dev *)data;
614
615
if (rtwdev->sta_cnt == 0) {
616
rtw_warn(rtwdev, "sta count before reset should not be 0\n");
617
return;
618
}
619
rtw_sta_remove(rtwdev, sta, false);
620
}
621
622
static void rtw_reset_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
623
{
624
struct rtw_dev *rtwdev = (struct rtw_dev *)data;
625
struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
626
627
rtw_bf_disassoc(rtwdev, vif, NULL);
628
rtw_vif_assoc_changed(rtwvif, NULL);
629
rtw_txq_cleanup(rtwdev, vif->txq);
630
631
rtw_release_macid(rtwdev, rtwvif->mac_id);
632
}
633
634
void rtw_fw_recovery(struct rtw_dev *rtwdev)
635
{
636
if (!test_bit(RTW_FLAG_RESTARTING, rtwdev->flags))
637
ieee80211_queue_work(rtwdev->hw, &rtwdev->fw_recovery_work);
638
}
639
EXPORT_SYMBOL(rtw_fw_recovery);
640
641
static void __fw_recovery_work(struct rtw_dev *rtwdev)
642
{
643
int ret = 0;
644
645
set_bit(RTW_FLAG_RESTARTING, rtwdev->flags);
646
clear_bit(RTW_FLAG_RESTART_TRIGGERING, rtwdev->flags);
647
648
ret = rtw_fwcd_prep(rtwdev);
649
if (ret)
650
goto free;
651
ret = rtw_fw_dump_crash_log(rtwdev);
652
if (ret)
653
goto free;
654
ret = rtw_chip_dump_fw_crash(rtwdev);
655
if (ret)
656
goto free;
657
658
rtw_fwcd_dump(rtwdev);
659
free:
660
rtw_fwcd_free(rtwdev, !!ret);
661
rtw_write8(rtwdev, REG_MCU_TST_CFG, 0);
662
663
WARN(1, "firmware crash, start reset and recover\n");
664
665
rcu_read_lock();
666
rtw_iterate_keys_rcu(rtwdev, NULL, rtw_reset_key_iter, rtwdev);
667
rcu_read_unlock();
668
rtw_iterate_stas_atomic(rtwdev, rtw_reset_sta_iter, rtwdev);
669
rtw_iterate_vifs_atomic(rtwdev, rtw_reset_vif_iter, rtwdev);
670
bitmap_zero(rtwdev->hw_port, RTW_PORT_NUM);
671
rtw_enter_ips(rtwdev);
672
}
673
674
static void rtw_fw_recovery_work(struct work_struct *work)
675
{
676
struct rtw_dev *rtwdev = container_of(work, struct rtw_dev,
677
fw_recovery_work);
678
679
mutex_lock(&rtwdev->mutex);
680
__fw_recovery_work(rtwdev);
681
mutex_unlock(&rtwdev->mutex);
682
683
ieee80211_restart_hw(rtwdev->hw);
684
}
685
686
struct rtw_txq_ba_iter_data {
687
};
688
689
static void rtw_txq_ba_iter(void *data, struct ieee80211_sta *sta)
690
{
691
struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
692
int ret;
693
u8 tid;
694
695
tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
696
while (tid != IEEE80211_NUM_TIDS) {
697
clear_bit(tid, si->tid_ba);
698
ret = ieee80211_start_tx_ba_session(sta, tid, 0);
699
if (ret == -EINVAL) {
700
struct ieee80211_txq *txq;
701
struct rtw_txq *rtwtxq;
702
703
txq = sta->txq[tid];
704
rtwtxq = (struct rtw_txq *)txq->drv_priv;
705
set_bit(RTW_TXQ_BLOCK_BA, &rtwtxq->flags);
706
}
707
708
tid = find_first_bit(si->tid_ba, IEEE80211_NUM_TIDS);
709
}
710
}
711
712
static void rtw_txq_ba_work(struct work_struct *work)
713
{
714
struct rtw_dev *rtwdev = container_of(work, struct rtw_dev, ba_work);
715
struct rtw_txq_ba_iter_data data;
716
717
rtw_iterate_stas_atomic(rtwdev, rtw_txq_ba_iter, &data);
718
}
719
720
void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel)
721
{
722
if (IS_CH_2G_BAND(channel))
723
pkt_stat->band = NL80211_BAND_2GHZ;
724
else if (IS_CH_5G_BAND(channel))
725
pkt_stat->band = NL80211_BAND_5GHZ;
726
else
727
return;
728
729
pkt_stat->freq = ieee80211_channel_to_frequency(channel, pkt_stat->band);
730
}
731
EXPORT_SYMBOL(rtw_set_rx_freq_band);
732
733
void rtw_set_dtim_period(struct rtw_dev *rtwdev, u8 dtim_period)
734
{
735
rtw_write32_set(rtwdev, REG_TCR, BIT_TCR_UPDATE_TIMIE);
736
rtw_write8(rtwdev, REG_DTIM_COUNTER_ROOT, dtim_period ? dtim_period - 1 : 0);
737
}
738
739
void rtw_update_channel(struct rtw_dev *rtwdev, u8 center_channel,
740
u8 primary_channel, enum rtw_supported_band band,
741
enum rtw_bandwidth bandwidth)
742
{
743
enum nl80211_band nl_band = rtw_hw_to_nl80211_band(band);
744
struct rtw_hal *hal = &rtwdev->hal;
745
u8 *cch_by_bw = hal->cch_by_bw;
746
u32 center_freq, primary_freq;
747
enum rtw_sar_bands sar_band;
748
u8 primary_channel_idx;
749
750
center_freq = ieee80211_channel_to_frequency(center_channel, nl_band);
751
primary_freq = ieee80211_channel_to_frequency(primary_channel, nl_band);
752
753
/* assign the center channel used while 20M bw is selected */
754
cch_by_bw[RTW_CHANNEL_WIDTH_20] = primary_channel;
755
756
/* assign the center channel used while current bw is selected */
757
cch_by_bw[bandwidth] = center_channel;
758
759
switch (bandwidth) {
760
case RTW_CHANNEL_WIDTH_20:
761
default:
762
primary_channel_idx = RTW_SC_DONT_CARE;
763
break;
764
case RTW_CHANNEL_WIDTH_40:
765
if (primary_freq > center_freq)
766
primary_channel_idx = RTW_SC_20_UPPER;
767
else
768
primary_channel_idx = RTW_SC_20_LOWER;
769
break;
770
case RTW_CHANNEL_WIDTH_80:
771
if (primary_freq > center_freq) {
772
if (primary_freq - center_freq == 10)
773
primary_channel_idx = RTW_SC_20_UPPER;
774
else
775
primary_channel_idx = RTW_SC_20_UPMOST;
776
777
/* assign the center channel used
778
* while 40M bw is selected
779
*/
780
cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel + 4;
781
} else {
782
if (center_freq - primary_freq == 10)
783
primary_channel_idx = RTW_SC_20_LOWER;
784
else
785
primary_channel_idx = RTW_SC_20_LOWEST;
786
787
/* assign the center channel used
788
* while 40M bw is selected
789
*/
790
cch_by_bw[RTW_CHANNEL_WIDTH_40] = center_channel - 4;
791
}
792
break;
793
}
794
795
switch (center_channel) {
796
case 1 ... 14:
797
sar_band = RTW_SAR_BAND_0;
798
break;
799
case 36 ... 64:
800
sar_band = RTW_SAR_BAND_1;
801
break;
802
case 100 ... 144:
803
sar_band = RTW_SAR_BAND_3;
804
break;
805
case 149 ... 177:
806
sar_band = RTW_SAR_BAND_4;
807
break;
808
default:
809
WARN(1, "unknown ch(%u) to SAR band\n", center_channel);
810
sar_band = RTW_SAR_BAND_0;
811
break;
812
}
813
814
hal->current_primary_channel_index = primary_channel_idx;
815
hal->current_band_width = bandwidth;
816
hal->primary_channel = primary_channel;
817
hal->current_channel = center_channel;
818
hal->current_band_type = band;
819
hal->sar_band = sar_band;
820
}
821
822
void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
823
struct rtw_channel_params *chan_params)
824
{
825
struct ieee80211_channel *channel = chandef->chan;
826
enum nl80211_chan_width width = chandef->width;
827
u32 primary_freq, center_freq;
828
u8 center_chan;
829
u8 bandwidth = RTW_CHANNEL_WIDTH_20;
830
831
center_chan = channel->hw_value;
832
primary_freq = channel->center_freq;
833
center_freq = chandef->center_freq1;
834
835
switch (width) {
836
case NL80211_CHAN_WIDTH_20_NOHT:
837
case NL80211_CHAN_WIDTH_20:
838
bandwidth = RTW_CHANNEL_WIDTH_20;
839
break;
840
case NL80211_CHAN_WIDTH_40:
841
bandwidth = RTW_CHANNEL_WIDTH_40;
842
if (primary_freq > center_freq)
843
center_chan -= 2;
844
else
845
center_chan += 2;
846
break;
847
case NL80211_CHAN_WIDTH_80:
848
bandwidth = RTW_CHANNEL_WIDTH_80;
849
if (primary_freq > center_freq) {
850
if (primary_freq - center_freq == 10)
851
center_chan -= 2;
852
else
853
center_chan -= 6;
854
} else {
855
if (center_freq - primary_freq == 10)
856
center_chan += 2;
857
else
858
center_chan += 6;
859
}
860
break;
861
default:
862
center_chan = 0;
863
break;
864
}
865
866
chan_params->center_chan = center_chan;
867
chan_params->bandwidth = bandwidth;
868
chan_params->primary_chan = channel->hw_value;
869
}
870
871
void rtw_set_channel(struct rtw_dev *rtwdev)
872
{
873
const struct rtw_chip_info *chip = rtwdev->chip;
874
struct ieee80211_hw *hw = rtwdev->hw;
875
struct rtw_hal *hal = &rtwdev->hal;
876
struct rtw_channel_params ch_param;
877
u8 center_chan, primary_chan, bandwidth, band;
878
879
rtw_get_channel_params(&hw->conf.chandef, &ch_param);
880
if (WARN(ch_param.center_chan == 0, "Invalid channel\n"))
881
return;
882
883
center_chan = ch_param.center_chan;
884
primary_chan = ch_param.primary_chan;
885
bandwidth = ch_param.bandwidth;
886
band = ch_param.center_chan > 14 ? RTW_BAND_5G : RTW_BAND_2G;
887
888
rtw_update_channel(rtwdev, center_chan, primary_chan, band, bandwidth);
889
890
if (rtwdev->scan_info.op_chan)
891
rtw_store_op_chan(rtwdev, true);
892
893
chip->ops->set_channel(rtwdev, center_chan, bandwidth,
894
hal->current_primary_channel_index);
895
896
if (hal->current_band_type == RTW_BAND_5G) {
897
rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_5G);
898
} else {
899
if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
900
rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G);
901
else
902
rtw_coex_switchband_notify(rtwdev, COEX_SWITCH_TO_24G_NOFORSCAN);
903
}
904
905
rtw_phy_set_tx_power_level(rtwdev, center_chan);
906
907
/* if the channel isn't set for scanning, we will do RF calibration
908
* in ieee80211_ops::mgd_prepare_tx(). Performing the calibration
909
* during scanning on each channel takes too long.
910
*/
911
if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
912
rtwdev->need_rfk = true;
913
}
914
915
void rtw_chip_prepare_tx(struct rtw_dev *rtwdev)
916
{
917
const struct rtw_chip_info *chip = rtwdev->chip;
918
919
if (rtwdev->need_rfk) {
920
rtwdev->need_rfk = false;
921
chip->ops->phy_calibration(rtwdev);
922
}
923
}
924
925
static void rtw_vif_write_addr(struct rtw_dev *rtwdev, u32 start, u8 *addr)
926
{
927
int i;
928
929
for (i = 0; i < ETH_ALEN; i++)
930
rtw_write8(rtwdev, start + i, addr[i]);
931
}
932
933
void rtw_vif_port_config(struct rtw_dev *rtwdev,
934
struct rtw_vif *rtwvif,
935
u32 config)
936
{
937
u32 addr, mask;
938
939
if (config & PORT_SET_MAC_ADDR) {
940
addr = rtwvif->conf->mac_addr.addr;
941
rtw_vif_write_addr(rtwdev, addr, rtwvif->mac_addr);
942
}
943
if (config & PORT_SET_BSSID) {
944
addr = rtwvif->conf->bssid.addr;
945
rtw_vif_write_addr(rtwdev, addr, rtwvif->bssid);
946
}
947
if (config & PORT_SET_NET_TYPE) {
948
addr = rtwvif->conf->net_type.addr;
949
mask = rtwvif->conf->net_type.mask;
950
rtw_write32_mask(rtwdev, addr, mask, rtwvif->net_type);
951
}
952
if (config & PORT_SET_AID) {
953
addr = rtwvif->conf->aid.addr;
954
mask = rtwvif->conf->aid.mask;
955
rtw_write32_mask(rtwdev, addr, mask, rtwvif->aid);
956
}
957
if (config & PORT_SET_BCN_CTRL) {
958
addr = rtwvif->conf->bcn_ctrl.addr;
959
mask = rtwvif->conf->bcn_ctrl.mask;
960
rtw_write8_mask(rtwdev, addr, mask, rtwvif->bcn_ctrl);
961
}
962
}
963
964
static u8 hw_bw_cap_to_bitamp(u8 bw_cap)
965
{
966
u8 bw = 0;
967
968
switch (bw_cap) {
969
case EFUSE_HW_CAP_IGNORE:
970
case EFUSE_HW_CAP_SUPP_BW80:
971
bw |= BIT(RTW_CHANNEL_WIDTH_80);
972
fallthrough;
973
case EFUSE_HW_CAP_SUPP_BW40:
974
bw |= BIT(RTW_CHANNEL_WIDTH_40);
975
fallthrough;
976
default:
977
bw |= BIT(RTW_CHANNEL_WIDTH_20);
978
break;
979
}
980
981
return bw;
982
}
983
984
static void rtw_hw_config_rf_ant_num(struct rtw_dev *rtwdev, u8 hw_ant_num)
985
{
986
const struct rtw_chip_info *chip = rtwdev->chip;
987
struct rtw_hal *hal = &rtwdev->hal;
988
989
if (hw_ant_num == EFUSE_HW_CAP_IGNORE ||
990
hw_ant_num >= hal->rf_path_num)
991
return;
992
993
switch (hw_ant_num) {
994
case 1:
995
hal->rf_type = RF_1T1R;
996
hal->rf_path_num = 1;
997
if (!chip->fix_rf_phy_num)
998
hal->rf_phy_num = hal->rf_path_num;
999
hal->antenna_tx = BB_PATH_A;
1000
hal->antenna_rx = BB_PATH_A;
1001
break;
1002
default:
1003
WARN(1, "invalid hw configuration from efuse\n");
1004
break;
1005
}
1006
}
1007
1008
static u64 get_vht_ra_mask(struct ieee80211_sta *sta)
1009
{
1010
u64 ra_mask = 0;
1011
u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map);
1012
u8 vht_mcs_cap;
1013
int i, nss;
1014
1015
/* 4SS, every two bits for MCS7/8/9 */
1016
for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 10) {
1017
vht_mcs_cap = mcs_map & 0x3;
1018
switch (vht_mcs_cap) {
1019
case 2: /* MCS9 */
1020
ra_mask |= 0x3ffULL << nss;
1021
break;
1022
case 1: /* MCS8 */
1023
ra_mask |= 0x1ffULL << nss;
1024
break;
1025
case 0: /* MCS7 */
1026
ra_mask |= 0x0ffULL << nss;
1027
break;
1028
default:
1029
break;
1030
}
1031
}
1032
1033
return ra_mask;
1034
}
1035
1036
static u8 get_rate_id(u8 wireless_set, enum rtw_bandwidth bw_mode, u8 tx_num)
1037
{
1038
u8 rate_id = 0;
1039
1040
switch (wireless_set) {
1041
case WIRELESS_CCK:
1042
rate_id = RTW_RATEID_B_20M;
1043
break;
1044
case WIRELESS_OFDM:
1045
rate_id = RTW_RATEID_G;
1046
break;
1047
case WIRELESS_CCK | WIRELESS_OFDM:
1048
rate_id = RTW_RATEID_BG;
1049
break;
1050
case WIRELESS_OFDM | WIRELESS_HT:
1051
if (tx_num == 1)
1052
rate_id = RTW_RATEID_GN_N1SS;
1053
else if (tx_num == 2)
1054
rate_id = RTW_RATEID_GN_N2SS;
1055
else if (tx_num == 3)
1056
rate_id = RTW_RATEID_ARFR5_N_3SS;
1057
break;
1058
case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_HT:
1059
if (bw_mode == RTW_CHANNEL_WIDTH_40) {
1060
if (tx_num == 1)
1061
rate_id = RTW_RATEID_BGN_40M_1SS;
1062
else if (tx_num == 2)
1063
rate_id = RTW_RATEID_BGN_40M_2SS;
1064
else if (tx_num == 3)
1065
rate_id = RTW_RATEID_ARFR5_N_3SS;
1066
else if (tx_num == 4)
1067
rate_id = RTW_RATEID_ARFR7_N_4SS;
1068
} else {
1069
if (tx_num == 1)
1070
rate_id = RTW_RATEID_BGN_20M_1SS;
1071
else if (tx_num == 2)
1072
rate_id = RTW_RATEID_BGN_20M_2SS;
1073
else if (tx_num == 3)
1074
rate_id = RTW_RATEID_ARFR5_N_3SS;
1075
else if (tx_num == 4)
1076
rate_id = RTW_RATEID_ARFR7_N_4SS;
1077
}
1078
break;
1079
case WIRELESS_OFDM | WIRELESS_VHT:
1080
if (tx_num == 1)
1081
rate_id = RTW_RATEID_ARFR1_AC_1SS;
1082
else if (tx_num == 2)
1083
rate_id = RTW_RATEID_ARFR0_AC_2SS;
1084
else if (tx_num == 3)
1085
rate_id = RTW_RATEID_ARFR4_AC_3SS;
1086
else if (tx_num == 4)
1087
rate_id = RTW_RATEID_ARFR6_AC_4SS;
1088
break;
1089
case WIRELESS_CCK | WIRELESS_OFDM | WIRELESS_VHT:
1090
if (bw_mode >= RTW_CHANNEL_WIDTH_80) {
1091
if (tx_num == 1)
1092
rate_id = RTW_RATEID_ARFR1_AC_1SS;
1093
else if (tx_num == 2)
1094
rate_id = RTW_RATEID_ARFR0_AC_2SS;
1095
else if (tx_num == 3)
1096
rate_id = RTW_RATEID_ARFR4_AC_3SS;
1097
else if (tx_num == 4)
1098
rate_id = RTW_RATEID_ARFR6_AC_4SS;
1099
} else {
1100
if (tx_num == 1)
1101
rate_id = RTW_RATEID_ARFR2_AC_2G_1SS;
1102
else if (tx_num == 2)
1103
rate_id = RTW_RATEID_ARFR3_AC_2G_2SS;
1104
else if (tx_num == 3)
1105
rate_id = RTW_RATEID_ARFR4_AC_3SS;
1106
else if (tx_num == 4)
1107
rate_id = RTW_RATEID_ARFR6_AC_4SS;
1108
}
1109
break;
1110
default:
1111
break;
1112
}
1113
1114
return rate_id;
1115
}
1116
1117
#define RA_MASK_CCK_RATES 0x0000f
1118
#define RA_MASK_OFDM_RATES 0x00ff0
1119
#define RA_MASK_HT_RATES_1SS (0xff000ULL << 0)
1120
#define RA_MASK_HT_RATES_2SS (0xff000ULL << 8)
1121
#define RA_MASK_HT_RATES_3SS (0xff000ULL << 16)
1122
#define RA_MASK_HT_RATES (RA_MASK_HT_RATES_1SS | \
1123
RA_MASK_HT_RATES_2SS | \
1124
RA_MASK_HT_RATES_3SS)
1125
#define RA_MASK_VHT_RATES_1SS (0x3ff000ULL << 0)
1126
#define RA_MASK_VHT_RATES_2SS (0x3ff000ULL << 10)
1127
#define RA_MASK_VHT_RATES_3SS (0x3ff000ULL << 20)
1128
#define RA_MASK_VHT_RATES (RA_MASK_VHT_RATES_1SS | \
1129
RA_MASK_VHT_RATES_2SS | \
1130
RA_MASK_VHT_RATES_3SS)
1131
#define RA_MASK_CCK_IN_BG 0x00005
1132
#define RA_MASK_CCK_IN_HT 0x00005
1133
#define RA_MASK_CCK_IN_VHT 0x00005
1134
#define RA_MASK_OFDM_IN_VHT 0x00010
1135
#define RA_MASK_OFDM_IN_HT_2G 0x00010
1136
#define RA_MASK_OFDM_IN_HT_5G 0x00030
1137
1138
static u64 rtw_rate_mask_rssi(struct rtw_sta_info *si, u8 wireless_set)
1139
{
1140
u8 rssi_level = si->rssi_level;
1141
1142
if (wireless_set == WIRELESS_CCK)
1143
return 0xffffffffffffffffULL;
1144
1145
if (rssi_level == 0)
1146
return 0xffffffffffffffffULL;
1147
else if (rssi_level == 1)
1148
return 0xfffffffffffffff0ULL;
1149
else if (rssi_level == 2)
1150
return 0xffffffffffffefe0ULL;
1151
else if (rssi_level == 3)
1152
return 0xffffffffffffcfc0ULL;
1153
else if (rssi_level == 4)
1154
return 0xffffffffffff8f80ULL;
1155
else
1156
return 0xffffffffffff0f00ULL;
1157
}
1158
1159
static u64 rtw_rate_mask_recover(u64 ra_mask, u64 ra_mask_bak)
1160
{
1161
if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0)
1162
ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
1163
1164
if (ra_mask == 0)
1165
ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
1166
1167
return ra_mask;
1168
}
1169
1170
static u64 rtw_rate_mask_cfg(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
1171
u64 ra_mask, bool is_vht_enable)
1172
{
1173
struct rtw_hal *hal = &rtwdev->hal;
1174
const struct cfg80211_bitrate_mask *mask = si->mask;
1175
u64 cfg_mask = GENMASK_ULL(63, 0);
1176
u8 band;
1177
1178
if (!si->use_cfg_mask)
1179
return ra_mask;
1180
1181
band = hal->current_band_type;
1182
if (band == RTW_BAND_2G) {
1183
band = NL80211_BAND_2GHZ;
1184
cfg_mask = mask->control[band].legacy;
1185
} else if (band == RTW_BAND_5G) {
1186
band = NL80211_BAND_5GHZ;
1187
cfg_mask = u64_encode_bits(mask->control[band].legacy,
1188
RA_MASK_OFDM_RATES);
1189
}
1190
1191
if (!is_vht_enable) {
1192
if (ra_mask & RA_MASK_HT_RATES_1SS)
1193
cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
1194
RA_MASK_HT_RATES_1SS);
1195
if (ra_mask & RA_MASK_HT_RATES_2SS)
1196
cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
1197
RA_MASK_HT_RATES_2SS);
1198
} else {
1199
if (ra_mask & RA_MASK_VHT_RATES_1SS)
1200
cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
1201
RA_MASK_VHT_RATES_1SS);
1202
if (ra_mask & RA_MASK_VHT_RATES_2SS)
1203
cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
1204
RA_MASK_VHT_RATES_2SS);
1205
}
1206
1207
ra_mask &= cfg_mask;
1208
1209
return ra_mask;
1210
}
1211
1212
void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
1213
bool reset_ra_mask)
1214
{
1215
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1216
struct ieee80211_sta *sta = si->sta;
1217
struct rtw_efuse *efuse = &rtwdev->efuse;
1218
struct rtw_hal *hal = &rtwdev->hal;
1219
u8 wireless_set;
1220
u8 bw_mode;
1221
u8 rate_id;
1222
u8 stbc_en = 0;
1223
u8 ldpc_en = 0;
1224
u8 tx_num = 1;
1225
u64 ra_mask = 0;
1226
u64 ra_mask_bak = 0;
1227
bool is_vht_enable = false;
1228
bool is_support_sgi = false;
1229
1230
if (sta->deflink.vht_cap.vht_supported) {
1231
is_vht_enable = true;
1232
ra_mask |= get_vht_ra_mask(sta);
1233
if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
1234
stbc_en = VHT_STBC_EN;
1235
if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
1236
ldpc_en = VHT_LDPC_EN;
1237
} else if (sta->deflink.ht_cap.ht_supported) {
1238
ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 36) |
1239
((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 28) |
1240
(sta->deflink.ht_cap.mcs.rx_mask[1] << 20) |
1241
(sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1242
if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
1243
stbc_en = HT_STBC_EN;
1244
if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
1245
ldpc_en = HT_LDPC_EN;
1246
}
1247
1248
if (efuse->hw_cap.nss == 1 || rtwdev->hal.txrx_1ss)
1249
ra_mask &= RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS;
1250
else if (efuse->hw_cap.nss == 2)
1251
ra_mask &= RA_MASK_VHT_RATES_2SS | RA_MASK_HT_RATES_2SS |
1252
RA_MASK_VHT_RATES_1SS | RA_MASK_HT_RATES_1SS;
1253
1254
if (hal->current_band_type == RTW_BAND_5G) {
1255
ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4;
1256
ra_mask_bak = ra_mask;
1257
if (sta->deflink.vht_cap.vht_supported) {
1258
ra_mask &= RA_MASK_VHT_RATES | RA_MASK_OFDM_IN_VHT;
1259
wireless_set = WIRELESS_OFDM | WIRELESS_VHT;
1260
} else if (sta->deflink.ht_cap.ht_supported) {
1261
ra_mask &= RA_MASK_HT_RATES | RA_MASK_OFDM_IN_HT_5G;
1262
wireless_set = WIRELESS_OFDM | WIRELESS_HT;
1263
} else {
1264
wireless_set = WIRELESS_OFDM;
1265
}
1266
dm_info->rrsr_val_init = RRSR_INIT_5G;
1267
} else if (hal->current_band_type == RTW_BAND_2G) {
1268
ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ];
1269
ra_mask_bak = ra_mask;
1270
if (sta->deflink.vht_cap.vht_supported) {
1271
ra_mask &= RA_MASK_VHT_RATES | RA_MASK_CCK_IN_VHT |
1272
RA_MASK_OFDM_IN_VHT;
1273
wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
1274
WIRELESS_HT | WIRELESS_VHT;
1275
} else if (sta->deflink.ht_cap.ht_supported) {
1276
ra_mask &= RA_MASK_HT_RATES | RA_MASK_CCK_IN_HT |
1277
RA_MASK_OFDM_IN_HT_2G;
1278
wireless_set = WIRELESS_CCK | WIRELESS_OFDM |
1279
WIRELESS_HT;
1280
} else if (sta->deflink.supp_rates[0] <= 0xf) {
1281
wireless_set = WIRELESS_CCK;
1282
} else {
1283
ra_mask &= RA_MASK_OFDM_RATES | RA_MASK_CCK_IN_BG;
1284
wireless_set = WIRELESS_CCK | WIRELESS_OFDM;
1285
}
1286
dm_info->rrsr_val_init = RRSR_INIT_2G;
1287
} else {
1288
rtw_err(rtwdev, "Unknown band type\n");
1289
ra_mask_bak = ra_mask;
1290
wireless_set = 0;
1291
}
1292
1293
switch (sta->deflink.bandwidth) {
1294
case IEEE80211_STA_RX_BW_80:
1295
bw_mode = RTW_CHANNEL_WIDTH_80;
1296
is_support_sgi = sta->deflink.vht_cap.vht_supported &&
1297
(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
1298
break;
1299
case IEEE80211_STA_RX_BW_40:
1300
bw_mode = RTW_CHANNEL_WIDTH_40;
1301
is_support_sgi = sta->deflink.ht_cap.ht_supported &&
1302
(sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
1303
break;
1304
default:
1305
bw_mode = RTW_CHANNEL_WIDTH_20;
1306
is_support_sgi = sta->deflink.ht_cap.ht_supported &&
1307
(sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
1308
break;
1309
}
1310
1311
if (sta->deflink.vht_cap.vht_supported ||
1312
sta->deflink.ht_cap.ht_supported)
1313
tx_num = efuse->hw_cap.nss;
1314
1315
rate_id = get_rate_id(wireless_set, bw_mode, tx_num);
1316
1317
ra_mask &= rtw_rate_mask_rssi(si, wireless_set);
1318
ra_mask = rtw_rate_mask_recover(ra_mask, ra_mask_bak);
1319
ra_mask = rtw_rate_mask_cfg(rtwdev, si, ra_mask, is_vht_enable);
1320
1321
si->bw_mode = bw_mode;
1322
si->stbc_en = stbc_en;
1323
si->ldpc_en = ldpc_en;
1324
si->sgi_enable = is_support_sgi;
1325
si->vht_enable = is_vht_enable;
1326
si->ra_mask = ra_mask;
1327
si->rate_id = rate_id;
1328
1329
rtw_fw_send_ra_info(rtwdev, si, reset_ra_mask);
1330
}
1331
1332
int rtw_wait_firmware_completion(struct rtw_dev *rtwdev)
1333
{
1334
const struct rtw_chip_info *chip = rtwdev->chip;
1335
struct rtw_fw_state *fw;
1336
int ret = 0;
1337
1338
fw = &rtwdev->fw;
1339
wait_for_completion(&fw->completion);
1340
if (!fw->firmware)
1341
ret = -EINVAL;
1342
1343
if (chip->wow_fw_name) {
1344
fw = &rtwdev->wow_fw;
1345
wait_for_completion(&fw->completion);
1346
if (!fw->firmware)
1347
ret = -EINVAL;
1348
}
1349
1350
return ret;
1351
}
1352
EXPORT_SYMBOL(rtw_wait_firmware_completion);
1353
1354
static enum rtw_lps_deep_mode rtw_update_lps_deep_mode(struct rtw_dev *rtwdev,
1355
struct rtw_fw_state *fw)
1356
{
1357
const struct rtw_chip_info *chip = rtwdev->chip;
1358
1359
if (rtw_disable_lps_deep_mode || !chip->lps_deep_mode_supported ||
1360
!fw->feature)
1361
return LPS_DEEP_MODE_NONE;
1362
1363
if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_PG)) &&
1364
rtw_fw_feature_check(fw, FW_FEATURE_PG))
1365
return LPS_DEEP_MODE_PG;
1366
1367
if ((chip->lps_deep_mode_supported & BIT(LPS_DEEP_MODE_LCLK)) &&
1368
rtw_fw_feature_check(fw, FW_FEATURE_LCLK))
1369
return LPS_DEEP_MODE_LCLK;
1370
1371
return LPS_DEEP_MODE_NONE;
1372
}
1373
1374
int rtw_power_on(struct rtw_dev *rtwdev)
1375
{
1376
const struct rtw_chip_info *chip = rtwdev->chip;
1377
struct rtw_fw_state *fw = &rtwdev->fw;
1378
bool wifi_only;
1379
int ret;
1380
1381
ret = rtw_hci_setup(rtwdev);
1382
if (ret) {
1383
rtw_err(rtwdev, "failed to setup hci\n");
1384
goto err;
1385
}
1386
1387
/* power on MAC before firmware downloaded */
1388
ret = rtw_mac_power_on(rtwdev);
1389
if (ret) {
1390
rtw_err(rtwdev, "failed to power on mac\n");
1391
goto err;
1392
}
1393
1394
ret = rtw_wait_firmware_completion(rtwdev);
1395
if (ret) {
1396
rtw_err(rtwdev, "failed to wait firmware completion\n");
1397
goto err_off;
1398
}
1399
1400
ret = rtw_download_firmware(rtwdev, fw);
1401
if (ret) {
1402
rtw_err(rtwdev, "failed to download firmware\n");
1403
goto err_off;
1404
}
1405
1406
/* config mac after firmware downloaded */
1407
ret = rtw_mac_init(rtwdev);
1408
if (ret) {
1409
rtw_err(rtwdev, "failed to configure mac\n");
1410
goto err_off;
1411
}
1412
1413
chip->ops->phy_set_param(rtwdev);
1414
1415
ret = rtw_mac_postinit(rtwdev);
1416
if (ret) {
1417
rtw_err(rtwdev, "failed to configure mac in postinit\n");
1418
goto err_off;
1419
}
1420
1421
ret = rtw_hci_start(rtwdev);
1422
if (ret) {
1423
rtw_err(rtwdev, "failed to start hci\n");
1424
goto err_off;
1425
}
1426
1427
/* send H2C after HCI has started */
1428
rtw_fw_send_general_info(rtwdev);
1429
rtw_fw_send_phydm_info(rtwdev);
1430
1431
wifi_only = !rtwdev->efuse.btcoex;
1432
rtw_coex_power_on_setting(rtwdev);
1433
rtw_coex_init_hw_config(rtwdev, wifi_only);
1434
1435
return 0;
1436
1437
err_off:
1438
rtw_mac_power_off(rtwdev);
1439
1440
err:
1441
return ret;
1442
}
1443
EXPORT_SYMBOL(rtw_power_on);
1444
1445
void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start)
1446
{
1447
if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_NOTIFY_SCAN))
1448
return;
1449
1450
if (start) {
1451
rtw_fw_scan_notify(rtwdev, true);
1452
} else {
1453
reinit_completion(&rtwdev->fw_scan_density);
1454
rtw_fw_scan_notify(rtwdev, false);
1455
if (!wait_for_completion_timeout(&rtwdev->fw_scan_density,
1456
SCAN_NOTIFY_TIMEOUT))
1457
rtw_warn(rtwdev, "firmware failed to report density after scan\n");
1458
}
1459
}
1460
1461
void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
1462
const u8 *mac_addr, bool hw_scan)
1463
{
1464
u32 config = 0;
1465
int ret = 0;
1466
1467
rtw_leave_lps(rtwdev);
1468
1469
if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) {
1470
ret = rtw_leave_ips(rtwdev);
1471
if (ret) {
1472
rtw_err(rtwdev, "failed to leave idle state\n");
1473
return;
1474
}
1475
}
1476
1477
ether_addr_copy(rtwvif->mac_addr, mac_addr);
1478
config |= PORT_SET_MAC_ADDR;
1479
rtw_vif_port_config(rtwdev, rtwvif, config);
1480
1481
rtw_coex_scan_notify(rtwdev, COEX_SCAN_START);
1482
rtw_core_fw_scan_notify(rtwdev, true);
1483
1484
set_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags);
1485
set_bit(RTW_FLAG_SCANNING, rtwdev->flags);
1486
1487
rtw_phy_dig_set_max_coverage(rtwdev);
1488
}
1489
1490
void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
1491
bool hw_scan)
1492
{
1493
struct rtw_vif *rtwvif = vif ? (struct rtw_vif *)vif->drv_priv : NULL;
1494
u32 config = 0;
1495
1496
if (!rtwvif)
1497
return;
1498
1499
rtw_phy_dig_reset(rtwdev);
1500
clear_bit(RTW_FLAG_SCANNING, rtwdev->flags);
1501
clear_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags);
1502
1503
rtw_core_fw_scan_notify(rtwdev, false);
1504
1505
ether_addr_copy(rtwvif->mac_addr, vif->addr);
1506
config |= PORT_SET_MAC_ADDR;
1507
rtw_vif_port_config(rtwdev, rtwvif, config);
1508
1509
rtw_coex_scan_notify(rtwdev, COEX_SCAN_FINISH);
1510
1511
if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE))
1512
ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work);
1513
}
1514
1515
int rtw_core_start(struct rtw_dev *rtwdev)
1516
{
1517
int ret;
1518
1519
ret = rtwdev->chip->ops->power_on(rtwdev);
1520
if (ret)
1521
return ret;
1522
1523
rtw_sec_enable_sec_engine(rtwdev);
1524
1525
rtwdev->lps_conf.deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->fw);
1526
rtwdev->lps_conf.wow_deep_mode = rtw_update_lps_deep_mode(rtwdev, &rtwdev->wow_fw);
1527
1528
/* rcr reset after powered on */
1529
rtw_write32(rtwdev, REG_RCR, rtwdev->hal.rcr);
1530
1531
ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->watch_dog_work,
1532
RTW_WATCH_DOG_DELAY_TIME);
1533
1534
set_bit(RTW_FLAG_RUNNING, rtwdev->flags);
1535
1536
return 0;
1537
}
1538
1539
void rtw_power_off(struct rtw_dev *rtwdev)
1540
{
1541
rtw_hci_stop(rtwdev);
1542
rtw_coex_power_off_setting(rtwdev);
1543
rtw_mac_power_off(rtwdev);
1544
}
1545
EXPORT_SYMBOL(rtw_power_off);
1546
1547
void rtw_core_stop(struct rtw_dev *rtwdev)
1548
{
1549
struct rtw_coex *coex = &rtwdev->coex;
1550
1551
clear_bit(RTW_FLAG_RUNNING, rtwdev->flags);
1552
clear_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
1553
1554
mutex_unlock(&rtwdev->mutex);
1555
1556
cancel_work_sync(&rtwdev->c2h_work);
1557
cancel_work_sync(&rtwdev->update_beacon_work);
1558
cancel_delayed_work_sync(&rtwdev->watch_dog_work);
1559
cancel_delayed_work_sync(&coex->bt_relink_work);
1560
cancel_delayed_work_sync(&coex->bt_reenable_work);
1561
cancel_delayed_work_sync(&coex->defreeze_work);
1562
cancel_delayed_work_sync(&coex->wl_remain_work);
1563
cancel_delayed_work_sync(&coex->bt_remain_work);
1564
cancel_delayed_work_sync(&coex->wl_connecting_work);
1565
cancel_delayed_work_sync(&coex->bt_multi_link_remain_work);
1566
cancel_delayed_work_sync(&coex->wl_ccklock_work);
1567
1568
mutex_lock(&rtwdev->mutex);
1569
1570
rtwdev->chip->ops->power_off(rtwdev);
1571
}
1572
1573
static void rtw_init_ht_cap(struct rtw_dev *rtwdev,
1574
struct ieee80211_sta_ht_cap *ht_cap)
1575
{
1576
const struct rtw_chip_info *chip = rtwdev->chip;
1577
struct rtw_efuse *efuse = &rtwdev->efuse;
1578
int i;
1579
1580
ht_cap->ht_supported = true;
1581
ht_cap->cap = 0;
1582
ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
1583
IEEE80211_HT_CAP_MAX_AMSDU |
1584
(1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
1585
1586
if (rtw_chip_has_rx_ldpc(rtwdev))
1587
ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
1588
if (rtw_chip_has_tx_stbc(rtwdev))
1589
ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC;
1590
1591
if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40))
1592
ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1593
IEEE80211_HT_CAP_DSSSCCK40 |
1594
IEEE80211_HT_CAP_SGI_40;
1595
ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
1596
ht_cap->ampdu_density = chip->ampdu_density;
1597
ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
1598
1599
for (i = 0; i < efuse->hw_cap.nss; i++)
1600
ht_cap->mcs.rx_mask[i] = 0xFF;
1601
ht_cap->mcs.rx_mask[4] = 0x01;
1602
ht_cap->mcs.rx_highest = cpu_to_le16(150 * efuse->hw_cap.nss);
1603
}
1604
1605
static void rtw_init_vht_cap(struct rtw_dev *rtwdev,
1606
struct ieee80211_sta_vht_cap *vht_cap)
1607
{
1608
struct rtw_efuse *efuse = &rtwdev->efuse;
1609
u16 mcs_map = 0;
1610
__le16 highest;
1611
int i;
1612
1613
if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE &&
1614
efuse->hw_cap.ptcl != EFUSE_HW_CAP_PTCL_VHT)
1615
return;
1616
1617
vht_cap->vht_supported = true;
1618
vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
1619
IEEE80211_VHT_CAP_SHORT_GI_80 |
1620
IEEE80211_VHT_CAP_RXSTBC_1 |
1621
IEEE80211_VHT_CAP_HTC_VHT |
1622
IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
1623
0;
1624
if (rtwdev->hal.rf_path_num > 1)
1625
vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
1626
vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
1627
IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
1628
vht_cap->cap |= (rtwdev->hal.bfee_sts_cap <<
1629
IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT);
1630
1631
if (rtw_chip_has_rx_ldpc(rtwdev))
1632
vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
1633
1634
for (i = 0; i < 8; i++) {
1635
if (i < efuse->hw_cap.nss)
1636
mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
1637
else
1638
mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
1639
}
1640
1641
highest = cpu_to_le16(390 * efuse->hw_cap.nss);
1642
1643
vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(mcs_map);
1644
vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map);
1645
vht_cap->vht_mcs.rx_highest = highest;
1646
vht_cap->vht_mcs.tx_highest = highest;
1647
}
1648
1649
static u16 rtw_get_max_scan_ie_len(struct rtw_dev *rtwdev)
1650
{
1651
u16 len;
1652
1653
len = rtwdev->chip->max_scan_ie_len;
1654
1655
if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_SCAN_OFFLOAD) &&
1656
rtwdev->chip->id == RTW_CHIP_TYPE_8822C)
1657
len = IEEE80211_MAX_DATA_LEN;
1658
else if (rtw_fw_feature_ext_check(&rtwdev->fw, FW_FEATURE_EXT_OLD_PAGE_NUM))
1659
len -= RTW_OLD_PROBE_PG_CNT * TX_PAGE_SIZE;
1660
1661
return len;
1662
}
1663
1664
static struct ieee80211_supported_band *
1665
rtw_sband_dup(struct rtw_dev *rtwdev,
1666
const struct ieee80211_supported_band *sband)
1667
{
1668
struct ieee80211_supported_band *dup;
1669
1670
dup = devm_kmemdup(rtwdev->dev, sband, sizeof(*sband), GFP_KERNEL);
1671
if (!dup)
1672
return NULL;
1673
1674
dup->channels = devm_kmemdup_array(rtwdev->dev, sband->channels,
1675
sband->n_channels,
1676
sizeof(*sband->channels),
1677
GFP_KERNEL);
1678
if (!dup->channels)
1679
return NULL;
1680
1681
dup->bitrates = devm_kmemdup_array(rtwdev->dev, sband->bitrates,
1682
sband->n_bitrates,
1683
sizeof(*sband->bitrates),
1684
GFP_KERNEL);
1685
if (!dup->bitrates)
1686
return NULL;
1687
1688
return dup;
1689
}
1690
1691
static void rtw_set_supported_band(struct ieee80211_hw *hw,
1692
const struct rtw_chip_info *chip)
1693
{
1694
struct ieee80211_supported_band *sband;
1695
struct rtw_dev *rtwdev = hw->priv;
1696
1697
if (chip->band & RTW_BAND_2G) {
1698
sband = rtw_sband_dup(rtwdev, &rtw_band_2ghz);
1699
if (!sband)
1700
goto err_out;
1701
if (chip->ht_supported)
1702
rtw_init_ht_cap(rtwdev, &sband->ht_cap);
1703
hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
1704
}
1705
1706
if (chip->band & RTW_BAND_5G) {
1707
sband = rtw_sband_dup(rtwdev, &rtw_band_5ghz);
1708
if (!sband)
1709
goto err_out;
1710
if (chip->ht_supported)
1711
rtw_init_ht_cap(rtwdev, &sband->ht_cap);
1712
if (chip->vht_supported)
1713
rtw_init_vht_cap(rtwdev, &sband->vht_cap);
1714
hw->wiphy->bands[NL80211_BAND_5GHZ] = sband;
1715
}
1716
1717
return;
1718
1719
err_out:
1720
rtw_err(rtwdev, "failed to set supported band\n");
1721
}
1722
1723
static void rtw_vif_smps_iter(void *data, u8 *mac,
1724
struct ieee80211_vif *vif)
1725
{
1726
struct rtw_dev *rtwdev = (struct rtw_dev *)data;
1727
1728
if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc)
1729
return;
1730
1731
if (rtwdev->hal.txrx_1ss)
1732
ieee80211_request_smps(vif, 0, IEEE80211_SMPS_STATIC);
1733
else
1734
ieee80211_request_smps(vif, 0, IEEE80211_SMPS_OFF);
1735
}
1736
1737
void rtw_set_txrx_1ss(struct rtw_dev *rtwdev, bool txrx_1ss)
1738
{
1739
const struct rtw_chip_info *chip = rtwdev->chip;
1740
struct rtw_hal *hal = &rtwdev->hal;
1741
1742
if (!chip->ops->config_txrx_mode || rtwdev->hal.txrx_1ss == txrx_1ss)
1743
return;
1744
1745
rtwdev->hal.txrx_1ss = txrx_1ss;
1746
if (txrx_1ss)
1747
chip->ops->config_txrx_mode(rtwdev, BB_PATH_A, BB_PATH_A, false);
1748
else
1749
chip->ops->config_txrx_mode(rtwdev, hal->antenna_tx,
1750
hal->antenna_rx, false);
1751
rtw_iterate_vifs_atomic(rtwdev, rtw_vif_smps_iter, rtwdev);
1752
}
1753
1754
static void __update_firmware_feature(struct rtw_dev *rtwdev,
1755
struct rtw_fw_state *fw)
1756
{
1757
u32 feature;
1758
const struct rtw_fw_hdr *fw_hdr =
1759
(const struct rtw_fw_hdr *)fw->firmware->data;
1760
1761
feature = le32_to_cpu(fw_hdr->feature);
1762
fw->feature = feature & FW_FEATURE_SIG ? feature : 0;
1763
1764
if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C &&
1765
RTW_FW_SUIT_VER_CODE(rtwdev->fw) < RTW_FW_VER_CODE(9, 9, 13))
1766
fw->feature_ext |= FW_FEATURE_EXT_OLD_PAGE_NUM;
1767
}
1768
1769
static void __update_firmware_info(struct rtw_dev *rtwdev,
1770
struct rtw_fw_state *fw)
1771
{
1772
const struct rtw_fw_hdr *fw_hdr =
1773
(const struct rtw_fw_hdr *)fw->firmware->data;
1774
1775
fw->h2c_version = le16_to_cpu(fw_hdr->h2c_fmt_ver);
1776
fw->version = le16_to_cpu(fw_hdr->version);
1777
fw->sub_version = fw_hdr->subversion;
1778
fw->sub_index = fw_hdr->subindex;
1779
1780
__update_firmware_feature(rtwdev, fw);
1781
}
1782
1783
static void __update_firmware_info_legacy(struct rtw_dev *rtwdev,
1784
struct rtw_fw_state *fw)
1785
{
1786
struct rtw_fw_hdr_legacy *legacy =
1787
(struct rtw_fw_hdr_legacy *)fw->firmware->data;
1788
1789
fw->h2c_version = 0;
1790
fw->version = le16_to_cpu(legacy->version);
1791
fw->sub_version = legacy->subversion1;
1792
fw->sub_index = legacy->subversion2;
1793
}
1794
1795
static void update_firmware_info(struct rtw_dev *rtwdev,
1796
struct rtw_fw_state *fw)
1797
{
1798
if (rtw_chip_wcpu_8051(rtwdev))
1799
__update_firmware_info_legacy(rtwdev, fw);
1800
else
1801
__update_firmware_info(rtwdev, fw);
1802
}
1803
1804
static void rtw_load_firmware_cb(const struct firmware *firmware, void *context)
1805
{
1806
struct rtw_fw_state *fw = context;
1807
struct rtw_dev *rtwdev = fw->rtwdev;
1808
1809
if (!firmware || !firmware->data) {
1810
rtw_err(rtwdev, "failed to request firmware\n");
1811
complete_all(&fw->completion);
1812
return;
1813
}
1814
1815
fw->firmware = firmware;
1816
update_firmware_info(rtwdev, fw);
1817
complete_all(&fw->completion);
1818
1819
rtw_info(rtwdev, "%sFirmware version %u.%u.%u, H2C version %u\n",
1820
fw->type == RTW_WOWLAN_FW ? "WOW " : "",
1821
fw->version, fw->sub_version, fw->sub_index, fw->h2c_version);
1822
}
1823
1824
static int rtw_load_firmware(struct rtw_dev *rtwdev, enum rtw_fw_type type)
1825
{
1826
const char *fw_name;
1827
struct rtw_fw_state *fw;
1828
int ret;
1829
1830
switch (type) {
1831
case RTW_WOWLAN_FW:
1832
fw = &rtwdev->wow_fw;
1833
fw_name = rtwdev->chip->wow_fw_name;
1834
break;
1835
1836
case RTW_NORMAL_FW:
1837
fw = &rtwdev->fw;
1838
fw_name = rtwdev->chip->fw_name;
1839
break;
1840
1841
default:
1842
rtw_warn(rtwdev, "unsupported firmware type\n");
1843
return -ENOENT;
1844
}
1845
1846
fw->type = type;
1847
fw->rtwdev = rtwdev;
1848
init_completion(&fw->completion);
1849
1850
ret = request_firmware_nowait(THIS_MODULE, true, fw_name, rtwdev->dev,
1851
GFP_KERNEL, fw, rtw_load_firmware_cb);
1852
if (ret) {
1853
rtw_err(rtwdev, "failed to async firmware request\n");
1854
return ret;
1855
}
1856
1857
return 0;
1858
}
1859
1860
static int rtw_chip_parameter_setup(struct rtw_dev *rtwdev)
1861
{
1862
const struct rtw_chip_info *chip = rtwdev->chip;
1863
struct rtw_hal *hal = &rtwdev->hal;
1864
struct rtw_efuse *efuse = &rtwdev->efuse;
1865
1866
switch (rtw_hci_type(rtwdev)) {
1867
case RTW_HCI_TYPE_PCIE:
1868
rtwdev->hci.rpwm_addr = 0x03d9;
1869
rtwdev->hci.cpwm_addr = 0x03da;
1870
break;
1871
case RTW_HCI_TYPE_SDIO:
1872
rtwdev->hci.rpwm_addr = REG_SDIO_HRPWM1;
1873
rtwdev->hci.cpwm_addr = REG_SDIO_HCPWM1_V2;
1874
break;
1875
case RTW_HCI_TYPE_USB:
1876
rtwdev->hci.rpwm_addr = 0xfe58;
1877
rtwdev->hci.cpwm_addr = 0xfe57;
1878
break;
1879
default:
1880
rtw_err(rtwdev, "unsupported hci type\n");
1881
return -EINVAL;
1882
}
1883
1884
hal->chip_version = rtw_read32(rtwdev, REG_SYS_CFG1);
1885
hal->cut_version = BIT_GET_CHIP_VER(hal->chip_version);
1886
hal->mp_chip = (hal->chip_version & BIT_RTL_ID) ? 0 : 1;
1887
if (hal->chip_version & BIT_RF_TYPE_ID) {
1888
hal->rf_type = RF_2T2R;
1889
hal->rf_path_num = 2;
1890
hal->antenna_tx = BB_PATH_AB;
1891
hal->antenna_rx = BB_PATH_AB;
1892
} else {
1893
hal->rf_type = RF_1T1R;
1894
hal->rf_path_num = 1;
1895
hal->antenna_tx = BB_PATH_A;
1896
hal->antenna_rx = BB_PATH_A;
1897
}
1898
hal->rf_phy_num = chip->fix_rf_phy_num ? chip->fix_rf_phy_num :
1899
hal->rf_path_num;
1900
1901
efuse->physical_size = chip->phy_efuse_size;
1902
efuse->logical_size = chip->log_efuse_size;
1903
efuse->protect_size = chip->ptct_efuse_size;
1904
1905
/* default use ack */
1906
rtwdev->hal.rcr |= BIT_VHT_DACK;
1907
1908
hal->bfee_sts_cap = 3;
1909
1910
return 0;
1911
}
1912
1913
static int rtw_chip_efuse_enable(struct rtw_dev *rtwdev)
1914
{
1915
struct rtw_fw_state *fw = &rtwdev->fw;
1916
int ret;
1917
1918
ret = rtw_hci_setup(rtwdev);
1919
if (ret) {
1920
rtw_err(rtwdev, "failed to setup hci\n");
1921
goto err;
1922
}
1923
1924
ret = rtw_mac_power_on(rtwdev);
1925
if (ret) {
1926
rtw_err(rtwdev, "failed to power on mac\n");
1927
goto err;
1928
}
1929
1930
rtw_write8(rtwdev, REG_C2HEVT, C2H_HW_FEATURE_DUMP);
1931
1932
wait_for_completion(&fw->completion);
1933
if (!fw->firmware) {
1934
ret = -EINVAL;
1935
rtw_err(rtwdev, "failed to load firmware\n");
1936
goto err;
1937
}
1938
1939
ret = rtw_download_firmware(rtwdev, fw);
1940
if (ret) {
1941
rtw_err(rtwdev, "failed to download firmware\n");
1942
goto err_off;
1943
}
1944
1945
return 0;
1946
1947
err_off:
1948
rtw_mac_power_off(rtwdev);
1949
1950
err:
1951
return ret;
1952
}
1953
1954
static int rtw_dump_hw_feature(struct rtw_dev *rtwdev)
1955
{
1956
struct rtw_efuse *efuse = &rtwdev->efuse;
1957
u8 hw_feature[HW_FEATURE_LEN];
1958
u8 id;
1959
u8 bw;
1960
int i;
1961
1962
if (!rtwdev->chip->hw_feature_report)
1963
return 0;
1964
1965
id = rtw_read8(rtwdev, REG_C2HEVT);
1966
if (id != C2H_HW_FEATURE_REPORT) {
1967
rtw_err(rtwdev, "failed to read hw feature report\n");
1968
return -EBUSY;
1969
}
1970
1971
for (i = 0; i < HW_FEATURE_LEN; i++)
1972
hw_feature[i] = rtw_read8(rtwdev, REG_C2HEVT + 2 + i);
1973
1974
rtw_write8(rtwdev, REG_C2HEVT, 0);
1975
1976
bw = GET_EFUSE_HW_CAP_BW(hw_feature);
1977
efuse->hw_cap.bw = hw_bw_cap_to_bitamp(bw);
1978
efuse->hw_cap.hci = GET_EFUSE_HW_CAP_HCI(hw_feature);
1979
efuse->hw_cap.nss = GET_EFUSE_HW_CAP_NSS(hw_feature);
1980
efuse->hw_cap.ptcl = GET_EFUSE_HW_CAP_PTCL(hw_feature);
1981
efuse->hw_cap.ant_num = GET_EFUSE_HW_CAP_ANT_NUM(hw_feature);
1982
1983
rtw_hw_config_rf_ant_num(rtwdev, efuse->hw_cap.ant_num);
1984
1985
if (efuse->hw_cap.nss == EFUSE_HW_CAP_IGNORE ||
1986
efuse->hw_cap.nss > rtwdev->hal.rf_path_num)
1987
efuse->hw_cap.nss = rtwdev->hal.rf_path_num;
1988
1989
rtw_dbg(rtwdev, RTW_DBG_EFUSE,
1990
"hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n",
1991
efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl,
1992
efuse->hw_cap.ant_num, efuse->hw_cap.nss);
1993
1994
return 0;
1995
}
1996
1997
static void rtw_chip_efuse_disable(struct rtw_dev *rtwdev)
1998
{
1999
rtw_hci_stop(rtwdev);
2000
rtw_mac_power_off(rtwdev);
2001
}
2002
2003
static int rtw_chip_efuse_info_setup(struct rtw_dev *rtwdev)
2004
{
2005
struct rtw_efuse *efuse = &rtwdev->efuse;
2006
int ret;
2007
2008
mutex_lock(&rtwdev->mutex);
2009
2010
/* power on mac to read efuse */
2011
ret = rtw_chip_efuse_enable(rtwdev);
2012
if (ret)
2013
goto out_unlock;
2014
2015
ret = rtw_parse_efuse_map(rtwdev);
2016
if (ret)
2017
goto out_disable;
2018
2019
ret = rtw_dump_hw_feature(rtwdev);
2020
if (ret)
2021
goto out_disable;
2022
2023
ret = rtw_check_supported_rfe(rtwdev);
2024
if (ret)
2025
goto out_disable;
2026
2027
if (efuse->crystal_cap == 0xff)
2028
efuse->crystal_cap = 0;
2029
if (efuse->pa_type_2g == 0xff)
2030
efuse->pa_type_2g = 0;
2031
if (efuse->pa_type_5g == 0xff)
2032
efuse->pa_type_5g = 0;
2033
if (efuse->lna_type_2g == 0xff)
2034
efuse->lna_type_2g = 0;
2035
if (efuse->lna_type_5g == 0xff)
2036
efuse->lna_type_5g = 0;
2037
if (efuse->channel_plan == 0xff)
2038
efuse->channel_plan = 0x7f;
2039
if (efuse->rf_board_option == 0xff)
2040
efuse->rf_board_option = 0;
2041
if (efuse->bt_setting & BIT(0))
2042
efuse->share_ant = true;
2043
if (efuse->regd == 0xff)
2044
efuse->regd = 0;
2045
if (efuse->tx_bb_swing_setting_2g == 0xff)
2046
efuse->tx_bb_swing_setting_2g = 0;
2047
if (efuse->tx_bb_swing_setting_5g == 0xff)
2048
efuse->tx_bb_swing_setting_5g = 0;
2049
2050
efuse->btcoex = (efuse->rf_board_option & 0xe0) == 0x20;
2051
efuse->ext_pa_2g = efuse->pa_type_2g & BIT(4) ? 1 : 0;
2052
efuse->ext_lna_2g = efuse->lna_type_2g & BIT(3) ? 1 : 0;
2053
efuse->ext_pa_5g = efuse->pa_type_5g & BIT(0) ? 1 : 0;
2054
efuse->ext_lna_5g = efuse->lna_type_5g & BIT(3) ? 1 : 0;
2055
2056
if (!is_valid_ether_addr(efuse->addr)) {
2057
eth_random_addr(efuse->addr);
2058
dev_warn(rtwdev->dev, "efuse MAC invalid, using random\n");
2059
}
2060
2061
out_disable:
2062
rtw_chip_efuse_disable(rtwdev);
2063
2064
out_unlock:
2065
mutex_unlock(&rtwdev->mutex);
2066
return ret;
2067
}
2068
2069
static int rtw_chip_board_info_setup(struct rtw_dev *rtwdev)
2070
{
2071
struct rtw_hal *hal = &rtwdev->hal;
2072
const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
2073
2074
if (!rfe_def)
2075
return -ENODEV;
2076
2077
rtw_phy_setup_phy_cond(rtwdev, hal->pkg_type);
2078
2079
rtw_phy_init_tx_power(rtwdev);
2080
rtw_load_table(rtwdev, rfe_def->phy_pg_tbl);
2081
rtw_load_table(rtwdev, rfe_def->txpwr_lmt_tbl);
2082
rtw_phy_tx_power_by_rate_config(hal);
2083
rtw_phy_tx_power_limit_config(hal);
2084
2085
return 0;
2086
}
2087
2088
int rtw_chip_info_setup(struct rtw_dev *rtwdev)
2089
{
2090
int ret;
2091
2092
ret = rtw_chip_parameter_setup(rtwdev);
2093
if (ret) {
2094
rtw_err(rtwdev, "failed to setup chip parameters\n");
2095
goto err_out;
2096
}
2097
2098
ret = rtw_chip_efuse_info_setup(rtwdev);
2099
if (ret) {
2100
rtw_err(rtwdev, "failed to setup chip efuse info\n");
2101
goto err_out;
2102
}
2103
2104
ret = rtw_chip_board_info_setup(rtwdev);
2105
if (ret) {
2106
rtw_err(rtwdev, "failed to setup chip board info\n");
2107
goto err_out;
2108
}
2109
2110
return 0;
2111
2112
err_out:
2113
return ret;
2114
}
2115
EXPORT_SYMBOL(rtw_chip_info_setup);
2116
2117
static void rtw_stats_init(struct rtw_dev *rtwdev)
2118
{
2119
struct rtw_traffic_stats *stats = &rtwdev->stats;
2120
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2121
int i;
2122
2123
ewma_tp_init(&stats->tx_ewma_tp);
2124
ewma_tp_init(&stats->rx_ewma_tp);
2125
2126
for (i = 0; i < RTW_EVM_NUM; i++)
2127
ewma_evm_init(&dm_info->ewma_evm[i]);
2128
for (i = 0; i < RTW_SNR_NUM; i++)
2129
ewma_snr_init(&dm_info->ewma_snr[i]);
2130
}
2131
2132
int rtw_core_init(struct rtw_dev *rtwdev)
2133
{
2134
const struct rtw_chip_info *chip = rtwdev->chip;
2135
struct rtw_coex *coex = &rtwdev->coex;
2136
int ret;
2137
2138
INIT_LIST_HEAD(&rtwdev->rsvd_page_list);
2139
INIT_LIST_HEAD(&rtwdev->txqs);
2140
2141
timer_setup(&rtwdev->tx_report.purge_timer,
2142
rtw_tx_report_purge_timer, 0);
2143
rtwdev->tx_wq = alloc_workqueue("rtw_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);
2144
if (!rtwdev->tx_wq) {
2145
rtw_warn(rtwdev, "alloc_workqueue rtw_tx_wq failed\n");
2146
return -ENOMEM;
2147
}
2148
2149
INIT_DELAYED_WORK(&rtwdev->watch_dog_work, rtw_watch_dog_work);
2150
INIT_DELAYED_WORK(&coex->bt_relink_work, rtw_coex_bt_relink_work);
2151
INIT_DELAYED_WORK(&coex->bt_reenable_work, rtw_coex_bt_reenable_work);
2152
INIT_DELAYED_WORK(&coex->defreeze_work, rtw_coex_defreeze_work);
2153
INIT_DELAYED_WORK(&coex->wl_remain_work, rtw_coex_wl_remain_work);
2154
INIT_DELAYED_WORK(&coex->bt_remain_work, rtw_coex_bt_remain_work);
2155
INIT_DELAYED_WORK(&coex->wl_connecting_work, rtw_coex_wl_connecting_work);
2156
INIT_DELAYED_WORK(&coex->bt_multi_link_remain_work,
2157
rtw_coex_bt_multi_link_remain_work);
2158
INIT_DELAYED_WORK(&coex->wl_ccklock_work, rtw_coex_wl_ccklock_work);
2159
INIT_WORK(&rtwdev->tx_work, rtw_tx_work);
2160
INIT_WORK(&rtwdev->c2h_work, rtw_c2h_work);
2161
INIT_WORK(&rtwdev->ips_work, rtw_ips_work);
2162
INIT_WORK(&rtwdev->fw_recovery_work, rtw_fw_recovery_work);
2163
INIT_WORK(&rtwdev->update_beacon_work, rtw_fw_update_beacon_work);
2164
INIT_WORK(&rtwdev->ba_work, rtw_txq_ba_work);
2165
skb_queue_head_init(&rtwdev->c2h_queue);
2166
skb_queue_head_init(&rtwdev->coex.queue);
2167
skb_queue_head_init(&rtwdev->tx_report.queue);
2168
2169
spin_lock_init(&rtwdev->txq_lock);
2170
spin_lock_init(&rtwdev->tx_report.q_lock);
2171
2172
mutex_init(&rtwdev->mutex);
2173
mutex_init(&rtwdev->hal.tx_power_mutex);
2174
2175
init_waitqueue_head(&rtwdev->coex.wait);
2176
init_completion(&rtwdev->lps_leave_check);
2177
init_completion(&rtwdev->fw_scan_density);
2178
2179
rtwdev->sec.total_cam_num = 32;
2180
rtwdev->hal.current_channel = 1;
2181
rtwdev->dm_info.fix_rate = U8_MAX;
2182
2183
rtw_stats_init(rtwdev);
2184
2185
/* default rx filter setting */
2186
rtwdev->hal.rcr = BIT_APP_FCS | BIT_APP_MIC | BIT_APP_ICV |
2187
BIT_PKTCTL_DLEN | BIT_HTC_LOC_CTRL | BIT_APP_PHYSTS |
2188
BIT_AB | BIT_AM | BIT_APM;
2189
2190
ret = rtw_load_firmware(rtwdev, RTW_NORMAL_FW);
2191
if (ret) {
2192
rtw_warn(rtwdev, "no firmware loaded\n");
2193
goto out;
2194
}
2195
2196
if (chip->wow_fw_name) {
2197
ret = rtw_load_firmware(rtwdev, RTW_WOWLAN_FW);
2198
if (ret) {
2199
rtw_warn(rtwdev, "no wow firmware loaded\n");
2200
wait_for_completion(&rtwdev->fw.completion);
2201
if (rtwdev->fw.firmware)
2202
release_firmware(rtwdev->fw.firmware);
2203
goto out;
2204
}
2205
}
2206
2207
return 0;
2208
2209
out:
2210
destroy_workqueue(rtwdev->tx_wq);
2211
return ret;
2212
}
2213
EXPORT_SYMBOL(rtw_core_init);
2214
2215
void rtw_core_deinit(struct rtw_dev *rtwdev)
2216
{
2217
struct rtw_fw_state *fw = &rtwdev->fw;
2218
struct rtw_fw_state *wow_fw = &rtwdev->wow_fw;
2219
struct rtw_rsvd_page *rsvd_pkt, *tmp;
2220
unsigned long flags;
2221
2222
rtw_wait_firmware_completion(rtwdev);
2223
2224
if (fw->firmware)
2225
release_firmware(fw->firmware);
2226
2227
if (wow_fw->firmware)
2228
release_firmware(wow_fw->firmware);
2229
2230
destroy_workqueue(rtwdev->tx_wq);
2231
timer_delete_sync(&rtwdev->tx_report.purge_timer);
2232
spin_lock_irqsave(&rtwdev->tx_report.q_lock, flags);
2233
skb_queue_purge(&rtwdev->tx_report.queue);
2234
spin_unlock_irqrestore(&rtwdev->tx_report.q_lock, flags);
2235
skb_queue_purge(&rtwdev->coex.queue);
2236
skb_queue_purge(&rtwdev->c2h_queue);
2237
2238
list_for_each_entry_safe(rsvd_pkt, tmp, &rtwdev->rsvd_page_list,
2239
build_list) {
2240
list_del(&rsvd_pkt->build_list);
2241
kfree(rsvd_pkt);
2242
}
2243
2244
mutex_destroy(&rtwdev->mutex);
2245
mutex_destroy(&rtwdev->hal.tx_power_mutex);
2246
}
2247
EXPORT_SYMBOL(rtw_core_deinit);
2248
2249
int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
2250
{
2251
struct rtw_hal *hal = &rtwdev->hal;
2252
int max_tx_headroom = 0;
2253
int ret;
2254
2255
max_tx_headroom = rtwdev->chip->tx_pkt_desc_sz;
2256
2257
if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO)
2258
max_tx_headroom += RTW_SDIO_DATA_PTR_ALIGN;
2259
2260
hw->extra_tx_headroom = max_tx_headroom;
2261
hw->queues = IEEE80211_NUM_ACS;
2262
hw->txq_data_size = sizeof(struct rtw_txq);
2263
hw->sta_data_size = sizeof(struct rtw_sta_info);
2264
hw->vif_data_size = sizeof(struct rtw_vif);
2265
2266
ieee80211_hw_set(hw, SIGNAL_DBM);
2267
ieee80211_hw_set(hw, RX_INCLUDES_FCS);
2268
ieee80211_hw_set(hw, AMPDU_AGGREGATION);
2269
ieee80211_hw_set(hw, MFP_CAPABLE);
2270
ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
2271
ieee80211_hw_set(hw, SUPPORTS_PS);
2272
ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
2273
ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
2274
if (rtwdev->chip->amsdu_in_ampdu)
2275
ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
2276
ieee80211_hw_set(hw, HAS_RATE_CONTROL);
2277
ieee80211_hw_set(hw, TX_AMSDU);
2278
ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
2279
2280
hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
2281
BIT(NL80211_IFTYPE_AP) |
2282
BIT(NL80211_IFTYPE_ADHOC);
2283
hw->wiphy->available_antennas_tx = hal->antenna_tx;
2284
hw->wiphy->available_antennas_rx = hal->antenna_rx;
2285
2286
hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
2287
WIPHY_FLAG_TDLS_EXTERNAL_SETUP;
2288
2289
hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
2290
hw->wiphy->max_scan_ssids = RTW_SCAN_MAX_SSIDS;
2291
hw->wiphy->max_scan_ie_len = rtw_get_max_scan_ie_len(rtwdev);
2292
2293
if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C) {
2294
hw->wiphy->iface_combinations = rtw_iface_combs;
2295
hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw_iface_combs);
2296
}
2297
2298
wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
2299
wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN);
2300
wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL);
2301
2302
#ifdef CONFIG_PM
2303
hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
2304
hw->wiphy->max_sched_scan_ssids = rtwdev->chip->max_sched_scan_ssids;
2305
#endif
2306
rtw_set_supported_band(hw, rtwdev->chip);
2307
SET_IEEE80211_PERM_ADDR(hw, rtwdev->efuse.addr);
2308
2309
hw->wiphy->sar_capa = &rtw_sar_capa;
2310
2311
ret = rtw_regd_init(rtwdev);
2312
if (ret) {
2313
rtw_err(rtwdev, "failed to init regd\n");
2314
return ret;
2315
}
2316
2317
rtw_led_init(rtwdev);
2318
2319
ret = ieee80211_register_hw(hw);
2320
if (ret) {
2321
rtw_err(rtwdev, "failed to register hw\n");
2322
goto led_deinit;
2323
}
2324
2325
ret = rtw_regd_hint(rtwdev);
2326
if (ret) {
2327
rtw_err(rtwdev, "failed to hint regd\n");
2328
goto led_deinit;
2329
}
2330
2331
rtw_debugfs_init(rtwdev);
2332
2333
rtwdev->bf_info.bfer_mu_cnt = 0;
2334
rtwdev->bf_info.bfer_su_cnt = 0;
2335
2336
return 0;
2337
2338
led_deinit:
2339
rtw_led_deinit(rtwdev);
2340
return ret;
2341
}
2342
EXPORT_SYMBOL(rtw_register_hw);
2343
2344
void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw)
2345
{
2346
ieee80211_unregister_hw(hw);
2347
rtw_debugfs_deinit(rtwdev);
2348
rtw_led_deinit(rtwdev);
2349
}
2350
EXPORT_SYMBOL(rtw_unregister_hw);
2351
2352
static
2353
void rtw_swap_reg_nbytes(struct rtw_dev *rtwdev, const struct rtw_hw_reg *reg1,
2354
const struct rtw_hw_reg *reg2, u8 nbytes)
2355
{
2356
u8 i;
2357
2358
for (i = 0; i < nbytes; i++) {
2359
u8 v1 = rtw_read8(rtwdev, reg1->addr + i);
2360
u8 v2 = rtw_read8(rtwdev, reg2->addr + i);
2361
2362
rtw_write8(rtwdev, reg1->addr + i, v2);
2363
rtw_write8(rtwdev, reg2->addr + i, v1);
2364
}
2365
}
2366
2367
static
2368
void rtw_swap_reg_mask(struct rtw_dev *rtwdev, const struct rtw_hw_reg *reg1,
2369
const struct rtw_hw_reg *reg2)
2370
{
2371
u32 v1, v2;
2372
2373
v1 = rtw_read32_mask(rtwdev, reg1->addr, reg1->mask);
2374
v2 = rtw_read32_mask(rtwdev, reg2->addr, reg2->mask);
2375
rtw_write32_mask(rtwdev, reg2->addr, reg2->mask, v1);
2376
rtw_write32_mask(rtwdev, reg1->addr, reg1->mask, v2);
2377
}
2378
2379
struct rtw_iter_port_switch_data {
2380
struct rtw_dev *rtwdev;
2381
struct rtw_vif *rtwvif_ap;
2382
};
2383
2384
static void rtw_port_switch_iter(void *data, struct ieee80211_vif *vif)
2385
{
2386
struct rtw_iter_port_switch_data *iter_data = data;
2387
struct rtw_dev *rtwdev = iter_data->rtwdev;
2388
struct rtw_vif *rtwvif_target = (struct rtw_vif *)vif->drv_priv;
2389
struct rtw_vif *rtwvif_ap = iter_data->rtwvif_ap;
2390
const struct rtw_hw_reg *reg1, *reg2;
2391
2392
if (rtwvif_target->port != RTW_PORT_0)
2393
return;
2394
2395
rtw_dbg(rtwdev, RTW_DBG_STATE, "AP port switch from %d -> %d\n",
2396
rtwvif_ap->port, rtwvif_target->port);
2397
2398
/* Leave LPS so the value swapped are not in PS mode */
2399
rtw_leave_lps(rtwdev);
2400
2401
reg1 = &rtwvif_ap->conf->net_type;
2402
reg2 = &rtwvif_target->conf->net_type;
2403
rtw_swap_reg_mask(rtwdev, reg1, reg2);
2404
2405
reg1 = &rtwvif_ap->conf->mac_addr;
2406
reg2 = &rtwvif_target->conf->mac_addr;
2407
rtw_swap_reg_nbytes(rtwdev, reg1, reg2, ETH_ALEN);
2408
2409
reg1 = &rtwvif_ap->conf->bssid;
2410
reg2 = &rtwvif_target->conf->bssid;
2411
rtw_swap_reg_nbytes(rtwdev, reg1, reg2, ETH_ALEN);
2412
2413
reg1 = &rtwvif_ap->conf->bcn_ctrl;
2414
reg2 = &rtwvif_target->conf->bcn_ctrl;
2415
rtw_swap_reg_nbytes(rtwdev, reg1, reg2, 1);
2416
2417
swap(rtwvif_target->port, rtwvif_ap->port);
2418
swap(rtwvif_target->conf, rtwvif_ap->conf);
2419
2420
rtw_fw_default_port(rtwdev, rtwvif_target);
2421
}
2422
2423
void rtw_core_port_switch(struct rtw_dev *rtwdev, struct ieee80211_vif *vif)
2424
{
2425
struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
2426
struct rtw_iter_port_switch_data iter_data;
2427
2428
if (vif->type != NL80211_IFTYPE_AP || rtwvif->port == RTW_PORT_0)
2429
return;
2430
2431
iter_data.rtwdev = rtwdev;
2432
iter_data.rtwvif_ap = rtwvif;
2433
rtw_iterate_vifs(rtwdev, rtw_port_switch_iter, &iter_data);
2434
}
2435
2436
static void rtw_check_sta_active_iter(void *data, struct ieee80211_vif *vif)
2437
{
2438
struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
2439
bool *active = data;
2440
2441
if (*active)
2442
return;
2443
2444
if (vif->type != NL80211_IFTYPE_STATION)
2445
return;
2446
2447
if (vif->cfg.assoc || !is_zero_ether_addr(rtwvif->bssid))
2448
*active = true;
2449
}
2450
2451
bool rtw_core_check_sta_active(struct rtw_dev *rtwdev)
2452
{
2453
bool sta_active = false;
2454
2455
rtw_iterate_vifs(rtwdev, rtw_check_sta_active_iter, &sta_active);
2456
2457
return rtwdev->ap_active || sta_active;
2458
}
2459
2460
void rtw_core_enable_beacon(struct rtw_dev *rtwdev, bool enable)
2461
{
2462
if (!rtwdev->ap_active)
2463
return;
2464
2465
if (enable) {
2466
rtw_write32_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
2467
rtw_write8_clr(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE);
2468
} else {
2469
rtw_write32_clr(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
2470
rtw_write8_set(rtwdev, REG_TXPAUSE, BIT_HIGH_QUEUE);
2471
}
2472
}
2473
2474
void rtw_set_ampdu_factor(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
2475
struct ieee80211_bss_conf *bss_conf)
2476
{
2477
const struct rtw_chip_ops *ops = rtwdev->chip->ops;
2478
struct ieee80211_sta *sta;
2479
u8 factor = 0xff;
2480
2481
if (!ops->set_ampdu_factor)
2482
return;
2483
2484
rcu_read_lock();
2485
2486
sta = ieee80211_find_sta(vif, bss_conf->bssid);
2487
if (!sta) {
2488
rcu_read_unlock();
2489
rtw_warn(rtwdev, "%s: failed to find station %pM\n",
2490
__func__, bss_conf->bssid);
2491
return;
2492
}
2493
2494
if (sta->deflink.vht_cap.vht_supported)
2495
factor = u32_get_bits(sta->deflink.vht_cap.cap,
2496
IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK);
2497
else if (sta->deflink.ht_cap.ht_supported)
2498
factor = sta->deflink.ht_cap.ampdu_factor;
2499
2500
rcu_read_unlock();
2501
2502
if (factor != 0xff)
2503
ops->set_ampdu_factor(rtwdev, factor);
2504
}
2505
2506
MODULE_AUTHOR("Realtek Corporation");
2507
MODULE_DESCRIPTION("Realtek 802.11ac wireless core module");
2508
MODULE_LICENSE("Dual BSD/GPL");
2509
2510