Path: blob/master/include/dt-bindings/clock/amlogic,a1-pll-clkc.h
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */1/*2* Copyright (c) 2019 Amlogic, Inc. All rights reserved.3* Author: Jian Hu <[email protected]>4*5* Copyright (c) 2023, SberDevices. All Rights Reserved.6* Author: Dmitry Rokosov <[email protected]>7*/89#ifndef __A1_PLL_CLKC_H10#define __A1_PLL_CLKC_H1112#define CLKID_FIXED_PLL_DCO 013#define CLKID_FIXED_PLL 114#define CLKID_FCLK_DIV2_DIV 215#define CLKID_FCLK_DIV3_DIV 316#define CLKID_FCLK_DIV5_DIV 417#define CLKID_FCLK_DIV7_DIV 518#define CLKID_FCLK_DIV2 619#define CLKID_FCLK_DIV3 720#define CLKID_FCLK_DIV5 821#define CLKID_FCLK_DIV7 922#define CLKID_HIFI_PLL 1023#define CLKID_SYS_PLL 112425#endif /* __A1_PLL_CLKC_H */262728