Path: blob/master/include/dt-bindings/clock/amlogic,c3-pll-clkc.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */1/*2* Copyright (c) 2023 Amlogic, Inc. All rights reserved.3* Author: Chuan Liu <[email protected]>4*/56#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H7#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H89#define CLKID_FCLK_50M_EN 010#define CLKID_FCLK_50M 111#define CLKID_FCLK_DIV2_DIV 212#define CLKID_FCLK_DIV2 313#define CLKID_FCLK_DIV2P5_DIV 414#define CLKID_FCLK_DIV2P5 515#define CLKID_FCLK_DIV3_DIV 616#define CLKID_FCLK_DIV3 717#define CLKID_FCLK_DIV4_DIV 818#define CLKID_FCLK_DIV4 919#define CLKID_FCLK_DIV5_DIV 1020#define CLKID_FCLK_DIV5 1121#define CLKID_FCLK_DIV7_DIV 1222#define CLKID_FCLK_DIV7 1323#define CLKID_GP0_PLL_DCO 1424#define CLKID_GP0_PLL 1525#define CLKID_HIFI_PLL_DCO 1626#define CLKID_HIFI_PLL 1727#define CLKID_MCLK_PLL_DCO 1828#define CLKID_MCLK_PLL_OD 1929#define CLKID_MCLK_PLL 2030#define CLKID_MCLK0_SEL 2131#define CLKID_MCLK0_SEL_EN 2232#define CLKID_MCLK0_DIV 2333#define CLKID_MCLK0 2434#define CLKID_MCLK1_SEL 2535#define CLKID_MCLK1_SEL_EN 2636#define CLKID_MCLK1_DIV 2737#define CLKID_MCLK1 283839#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H */404142