CoCalc -- axis,artpec9-clk.h

GitHub Repository: torvalds/linux
Path: blob/master/include/dt-bindings/clock/axis,artpec9-clk.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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 * Copyright (c) 2025 Samsung Electronics Co., Ltd.
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 *             https://www.samsung.com
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 * Copyright (c) 2025  Axis Communications AB.
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 *             https://www.axis.com
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 *
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 * Device Tree binding constants for ARTPEC-9 clock controller.
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 */
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#ifndef _DT_BINDINGS_CLOCK_ARTPEC9_H
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#define _DT_BINDINGS_CLOCK_ARTPEC9_H
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/* CMU_CMU */
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#define CLK_FOUT_SHARED0_PLL						1
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#define CLK_DOUT_SHARED0_DIV2						2
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#define CLK_DOUT_SHARED0_DIV3						3
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#define CLK_DOUT_SHARED0_DIV4						4
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#define CLK_FOUT_SHARED1_PLL						5
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#define CLK_DOUT_SHARED1_DIV2						6
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#define CLK_DOUT_SHARED1_DIV3						7
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#define CLK_DOUT_SHARED1_DIV4						8
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#define CLK_FOUT_AUDIO_PLL						9
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#define CLK_DOUT_CMU_ADD						10
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#define CLK_DOUT_CMU_BUS						11
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#define CLK_DOUT_CMU_CDC_CORE						12
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#define CLK_DOUT_CMU_CORE_MAIN						13
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#define CLK_DOUT_CMU_CPUCL_SWITCH					14
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#define CLK_DOUT_CMU_DLP_CORE						15
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#define CLK_DOUT_CMU_FSYS0_BUS						16
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#define CLK_DOUT_CMU_FSYS0_IP						17
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#define CLK_DOUT_CMU_FSYS1_BUS						18
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#define CLK_DOUT_CMU_FSYS1_SCAN0					19
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#define CLK_DOUT_CMU_FSYS1_SCAN1					20
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#define CLK_DOUT_CMU_GPU_3D						21
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#define CLK_DOUT_CMU_GPU_2D						22
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#define CLK_DOUT_CMU_IMEM_ACLK						23
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#define CLK_DOUT_CMU_IMEM_CA5						24
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#define CLK_DOUT_CMU_IMEM_JPEG						25
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#define CLK_DOUT_CMU_IMEM_SSS						26
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#define CLK_DOUT_CMU_IPA_CORE						27
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#define CLK_DOUT_CMU_LCPU						28
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#define CLK_DOUT_CMU_MIF_SWITCH						29
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#define CLK_DOUT_CMU_MIF_BUSP						30
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#define CLK_DOUT_CMU_PERI_DISP						31
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#define CLK_DOUT_CMU_PERI_IP						32
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#define CLK_DOUT_CMU_RSP_CORE						33
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#define CLK_DOUT_CMU_TRFM						34
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#define CLK_DOUT_CMU_VIO_CORE_L						35
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#define CLK_DOUT_CMU_VIO_CORE						36
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#define CLK_DOUT_CMU_VIP0						37
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#define CLK_DOUT_CMU_VIP1						38
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#define CLK_DOUT_CMU_VPP_CORE						39
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#define CLK_DOUT_CMU_VIO_AUDIO						40
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/* CMU_BUS */
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#define CLK_MOUT_BUS_ACLK_USER						1
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/* CMU_CORE */
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#define CLK_MOUT_CORE_ACLK_USER						1
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/* CMU_CPUCL */
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#define CLK_FOUT_CPUCL_PLL0						1
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#define CLK_MOUT_CPUCL_PLL0						2
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#define CLK_FOUT_CPUCL_PLL1						3
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#define CLK_MOUT_CPUCL_PLL_SCU						4
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#define CLK_MOUT_CPUCL_SWITCH_SCU_USER					5
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#define CLK_MOUT_CPUCL_SWITCH_USER					6
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#define CLK_DOUT_CPUCL_CPU						7
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#define CLK_DOUT_CPUCL_CLUSTER_PERIPHCLK				8
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#define CLK_DOUT_CPUCL_CLUSTER_GICCLK					9
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#define CLK_DOUT_CPUCL_CLUSTER_PCLK					10
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#define CLK_DOUT_CPUCL_CMUREF						11
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#define CLK_DOUT_CPUCL_CLUSTER_ATCLK					12
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#define CLK_DOUT_CPUCL_CLUSTER_SCU					13
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#define CLK_DOUT_CPUCL_DBG						14
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#define CLK_GOUT_CPUCL_SHORTSTOP					15
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#define CLK_GOUT_CPUCL_CLUSTER_CPU					16
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#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK				17
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#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG				18
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/* CMU_FSYS0 */
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#define CLK_MOUT_FSYS0_BUS_USER						1
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#define CLK_MOUT_FSYS0_IP_USER						2
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#define CLK_MOUT_FSYS0_MAIN_USER					3
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#define CLK_DOUT_FSYS0_125						4
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#define CLK_DOUT_FSYS0_ADC						5
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#define CLK_DOUT_FSYS0_BUS_300						6
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#define CLK_DOUT_FSYS0_EQOS0						7
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#define CLK_DOUT_FSYS0_EQOS1						8
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#define CLK_DOUT_FSYS0_MMC_CARD0					9
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#define CLK_DOUT_FSYS0_MMC_CARD1					10
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#define CLK_DOUT_FSYS0_MMC_CARD2					11
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#define CLK_DOUT_FSYS0_QSPI						12
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#define CLK_DOUT_FSYS0_SFMC_NAND					13
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#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I			14
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#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_CSR_I			15
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#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_PHASE_CLK_250	16
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#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_TXCLK		17
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#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_I_RGMII_PHASE_CLK_250	18
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#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_I_RGMII_TXCLK		19
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#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_ACLK_I			20
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#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_CLK_CSR_I			21
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#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_APB_S_PCLK			22
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#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_CORE_CLK			23
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#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_DMA_CLK				24
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#define CLK_GOUT_FSYS0_I3C0_IPCLKPORT_I_HDR_TX_CLK			25
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#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_APB_S_PCLK			26
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#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_CORE_CLK			27
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#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_DMA_CLK				28
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#define CLK_GOUT_FSYS0_I3C1_IPCLKPORT_I_HDR_TX_CLK			29
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#define CLK_GOUT_FSYS0_MMC0_IPCLKPORT_SDCLKIN				30
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#define CLK_GOUT_FSYS0_MMC1_IPCLKPORT_SDCLKIN				31
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#define CLK_GOUT_FSYS0_MMC2_IPCLKPORT_SDCLKIN				32
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#define CLK_GOUT_FSYS0_QSPI_IPCLKPORT_HCLK				33
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#define CLK_GOUT_FSYS0_QSPI_IPCLKPORT_SSI_CLK				34
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#define CLK_GOUT_FSYS0_SFMC_IPCLKPORT_I_ACLK_NAND			35
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#define CLK_GOUT_FSYS0_I2C0_IPCLKPORT_I_PCLK				36
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#define CLK_GOUT_FSYS0_I2C1_IPCLKPORT_I_PCLK				37
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#define CLK_GOUT_FSYS0_MMC0_IPCLKPORT_I_ACLK				38
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#define CLK_GOUT_FSYS0_MMC1_IPCLKPORT_I_ACLK				39
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#define CLK_GOUT_FSYS0_MMC2_IPCLKPORT_I_ACLK				40
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#define CLK_GOUT_FSYS0_PWM_IPCLKPORT_I_PCLK_S0				41
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/* CMU_FSYS1 */
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#define CLK_FOUT_FSYS1_PLL						1
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#define CLK_MOUT_FSYS1_SCAN0_USER					2
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#define CLK_MOUT_FSYS1_SCAN1_USER					3
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#define CLK_MOUT_FSYS1_BUS_USER						4
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#define CLK_DOUT_FSYS1_200						5
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#define CLK_DOUT_FSYS1_BUS_300						6
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#define CLK_DOUT_FSYS1_OTP_MEM						7
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#define CLK_DOUT_FSYS1_PCIE_PHY_REFCLK_SYSPLL				8
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#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_100		9
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#define CLK_GOUT_FSYS1_UART0_PCLK					10
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#define CLK_GOUT_FSYS1_UART0_SCLK_UART					11
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#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_PHY_APB2CR_PCLK_300		12
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#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_DBI_ACLK_SOC		13
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#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_MSTR_ACLK_SOC		14
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#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X1_SLV_ACLK_SOC		15
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#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_DBI_ACLK_SOC		16
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#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_MSTR_ACLK_SOC		17
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#define CLK_GOUT_FSYS1_IPCLKPORT_PCIE_SUB_CON_X2_SLV_ACLK_SOC		18
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#define CLK_GOUT_FSYS1_USB20DRD_IPCLKPORT_ACLK_PHYCTRL_20		19
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#define CLK_GOUT_FSYS1_USB20DRD_IPCLKPORT_BUS_CLK_EARLY			20
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#define CLK_GOUT_FSYS1_XHB_AHBBR_FSYS1_IPCLKPORT_CLK			21
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#define CLK_GOUT_FSYS1_XHB_USB_IPCLKPORT_CLK				22
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/* CMU_IMEM */
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#define CLK_MOUT_IMEM_ACLK_USER						1
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#define CLK_MOUT_IMEM_CA5_USER						2
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#define CLK_MOUT_IMEM_SSS_USER						3
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#define CLK_MOUT_IMEM_JPEG_USER						4
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#define CLK_DOUT_IMEM_PCLK						5
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#define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_ATCLK				6
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#define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_CLKIN				7
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#define CLK_GOUT_IMEM_CA5_0_IPCLKPORT_PCLK_DBG				8
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#define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_ATCLK				9
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#define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_CLKIN				10
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#define CLK_GOUT_IMEM_CA5_1_IPCLKPORT_PCLK_DBG				11
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#define CLK_GOUT_IMEM_MCT0_PCLK						12
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#define CLK_GOUT_IMEM_MCT1_PCLK						13
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#define CLK_GOUT_IMEM_MCT2_PCLK						14
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#define CLK_GOUT_IMEM_MCT3_PCLK						15
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#define CLK_GOUT_IMEM_PCLK_TMU0_APBIF					16
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/* CMU_PERI */
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#define CLK_MOUT_PERI_IP_USER						1
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#define CLK_MOUT_PERI_DISP_USER						2
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#define CLK_DOUT_PERI_125						3
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#define CLK_DOUT_PERI_PCLK						4
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#define CLK_DOUT_PERI_SPI						5
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#define CLK_DOUT_PERI_UART1						6
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#define CLK_DOUT_PERI_UART2						7
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#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_APB_CLK			8
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#define CLK_GOUT_PERI_DMA4DSIM_IPCLKPORT_CLK_AXI_CLK			9
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#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_APB_S_PCLK			10
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#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_CORE_CLK				11
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#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_DMA_CLK				12
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#define CLK_GOUT_PERI_I3C2_IPCLKPORT_I_HDR_TX_CLK			13
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#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_APB_S_PCLK			14
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#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_CORE_CLK				15
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#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_DMA_CLK				16
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#define CLK_GOUT_PERI_I3C3_IPCLKPORT_I_HDR_TX_CLK			17
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#define CLK_GOUT_PERI_APB_ASYNC_DSIM_IPCLKPORT_PCLKS			18
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#define CLK_GOUT_PERI_I2C2_IPCLKPORT_I_PCLK				19
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#define CLK_GOUT_PERI_I2C3_IPCLKPORT_I_PCLK				20
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#define CLK_GOUT_PERI_SPI0_PCLK						21
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#define CLK_GOUT_PERI_SPI0_SCLK_SPI					22
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#define CLK_GOUT_PERI_UART1_PCLK					23
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#define CLK_GOUT_PERI_UART1_SCLK_UART					24
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#define CLK_GOUT_PERI_UART2_PCLK					25
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#define CLK_GOUT_PERI_UART2_SCLK_UART					26
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#endif /* _DT_BINDINGS_CLOCK_ARTPEC9_H */
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