/*1* BSD LICENSE2*3* Copyright(c) 2017 Broadcom. All rights reserved.4*5* Redistribution and use in source and binary forms, with or without6* modification, are permitted provided that the following conditions7* are met:8*9* * Redistributions of source code must retain the above copyright10* notice, this list of conditions and the following disclaimer.11* * Redistributions in binary form must reproduce the above copyright12* notice, this list of conditions and the following disclaimer in13* the documentation and/or other materials provided with the14* distribution.15* * Neither the name of Broadcom Corporation nor the names of its16* contributors may be used to endorse or promote products derived17* from this software without specific prior written permission.18*19* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS20* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT21* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR22* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT23* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,24* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT25* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,26* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY27* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT28* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE29* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.30*/3132#ifndef _CLOCK_BCM_SR_H33#define _CLOCK_BCM_SR_H3435/* GENPLL 0 clock channel ID SCR HSLS FS PCIE */36#define BCM_SR_GENPLL0 037#define BCM_SR_GENPLL0_125M_CLK 138#define BCM_SR_GENPLL0_SCR_CLK 239#define BCM_SR_GENPLL0_250M_CLK 340#define BCM_SR_GENPLL0_PCIE_AXI_CLK 441#define BCM_SR_GENPLL0_PAXC_AXI_X2_CLK 542#define BCM_SR_GENPLL0_PAXC_AXI_CLK 64344/* GENPLL 1 clock channel ID MHB PCIE NITRO */45#define BCM_SR_GENPLL1 046#define BCM_SR_GENPLL1_PCIE_TL_CLK 147#define BCM_SR_GENPLL1_MHB_APB_CLK 24849/* GENPLL 2 clock channel ID NITRO MHB*/50#define BCM_SR_GENPLL2 051#define BCM_SR_GENPLL2_NIC_CLK 152#define BCM_SR_GENPLL2_TS_500_CLK 253#define BCM_SR_GENPLL2_125_NITRO_CLK 354#define BCM_SR_GENPLL2_CHIMP_CLK 455#define BCM_SR_GENPLL2_NIC_FLASH_CLK 556#define BCM_SR_GENPLL2_FS4_CLK 65758/* GENPLL 3 HSLS clock channel ID */59#define BCM_SR_GENPLL3 060#define BCM_SR_GENPLL3_HSLS_CLK 161#define BCM_SR_GENPLL3_SDIO_CLK 26263/* GENPLL 4 SCR clock channel ID */64#define BCM_SR_GENPLL4 065#define BCM_SR_GENPLL4_CCN_CLK 166#define BCM_SR_GENPLL4_TPIU_PLL_CLK 267#define BCM_SR_GENPLL4_NOC_CLK 368#define BCM_SR_GENPLL4_CHCLK_FS4_CLK 469#define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK 57071/* GENPLL 5 FS4 clock channel ID */72#define BCM_SR_GENPLL5 073#define BCM_SR_GENPLL5_FS4_HF_CLK 174#define BCM_SR_GENPLL5_CRYPTO_AE_CLK 275#define BCM_SR_GENPLL5_RAID_AE_CLK 37677/* GENPLL 6 NITRO clock channel ID */78#define BCM_SR_GENPLL6 079#define BCM_SR_GENPLL6_48_USB_CLK 18081/* LCPLL0 clock channel ID */82#define BCM_SR_LCPLL0 083#define BCM_SR_LCPLL0_SATA_REFP_CLK 184#define BCM_SR_LCPLL0_SATA_REFN_CLK 285#define BCM_SR_LCPLL0_SATA_350_CLK 386#define BCM_SR_LCPLL0_SATA_500_CLK 48788/* LCPLL1 clock channel ID */89#define BCM_SR_LCPLL1 090#define BCM_SR_LCPLL1_WAN_CLK 191#define BCM_SR_LCPLL1_USB_REF_CLK 292#define BCM_SR_LCPLL1_CRMU_TS_CLK 39394/* LCPLL PCIE clock channel ID */95#define BCM_SR_LCPLL_PCIE 096#define BCM_SR_LCPLL_PCIE_PHY_REF_CLK 19798/* GENPLL EMEM0 clock channel ID */99#define BCM_SR_EMEMPLL0 0100#define BCM_SR_EMEMPLL0_EMEM_CLK 1101102/* GENPLL EMEM0 clock channel ID */103#define BCM_SR_EMEMPLL1 0104#define BCM_SR_EMEMPLL1_EMEM_CLK 1105106/* GENPLL EMEM0 clock channel ID */107#define BCM_SR_EMEMPLL2 0108#define BCM_SR_EMEMPLL2_EMEM_CLK 1109110#endif /* _CLOCK_BCM_SR_H */111112113