Path: blob/master/include/dt-bindings/gpio/tegra241-gpio.h
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/* SPDX-License-Identifier: GPL-2.0 */1/* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. */23/*4* This header provides constants for the nvidia,tegra241-gpio DT binding.5*6* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below7* provide names for this.8*9* The second cell contains standard flag values specified in gpio.h.10*/1112#ifndef _DT_BINDINGS_GPIO_TEGRA241_GPIO_H13#define _DT_BINDINGS_GPIO_TEGRA241_GPIO_H1415#include <dt-bindings/gpio/gpio.h>1617/* GPIOs implemented by main GPIO controller */18#define TEGRA241_MAIN_GPIO_PORT_A 019#define TEGRA241_MAIN_GPIO_PORT_B 120#define TEGRA241_MAIN_GPIO_PORT_C 221#define TEGRA241_MAIN_GPIO_PORT_D 322#define TEGRA241_MAIN_GPIO_PORT_E 423#define TEGRA241_MAIN_GPIO_PORT_F 524#define TEGRA241_MAIN_GPIO_PORT_G 625#define TEGRA241_MAIN_GPIO_PORT_H 726#define TEGRA241_MAIN_GPIO_PORT_I 827#define TEGRA241_MAIN_GPIO_PORT_J 928#define TEGRA241_MAIN_GPIO_PORT_K 1029#define TEGRA241_MAIN_GPIO_PORT_L 113031#define TEGRA241_MAIN_GPIO(port, offset) \32((TEGRA241_MAIN_GPIO_PORT_##port * 8) + (offset))3334/* GPIOs implemented by AON GPIO controller */35#define TEGRA241_AON_GPIO_PORT_AA 036#define TEGRA241_AON_GPIO_PORT_BB 13738#define TEGRA241_AON_GPIO(port, offset) \39((TEGRA241_AON_GPIO_PORT_##port * 8) + (offset))4041#endif424344