Path: blob/master/include/dt-bindings/iio/qcom,spmi-vadc.h
26285 views
/* SPDX-License-Identifier: GPL-2.0 */1/*2* Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved.3*/45#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H6#define _DT_BINDINGS_QCOM_SPMI_VADC_H78/* Voltage ADC channels */9#define VADC_USBIN 0x0010#define VADC_DCIN 0x0111#define VADC_VCHG_SNS 0x0212#define VADC_SPARE1_03 0x0313#define VADC_USB_ID_MV 0x0414#define VADC_VCOIN 0x0515#define VADC_VBAT_SNS 0x0616#define VADC_VSYS 0x0717#define VADC_DIE_TEMP 0x0818#define VADC_REF_625MV 0x0919#define VADC_REF_1250MV 0x0a20#define VADC_CHG_TEMP 0x0b21#define VADC_SPARE1 0x0c22#define VADC_SPARE2 0x0d23#define VADC_GND_REF 0x0e24#define VADC_VDD_VADC 0x0f2526#define VADC_P_MUX1_1_1 0x1027#define VADC_P_MUX2_1_1 0x1128#define VADC_P_MUX3_1_1 0x1229#define VADC_P_MUX4_1_1 0x1330#define VADC_P_MUX5_1_1 0x1431#define VADC_P_MUX6_1_1 0x1532#define VADC_P_MUX7_1_1 0x1633#define VADC_P_MUX8_1_1 0x1734#define VADC_P_MUX9_1_1 0x1835#define VADC_P_MUX10_1_1 0x1936#define VADC_P_MUX11_1_1 0x1a37#define VADC_P_MUX12_1_1 0x1b38#define VADC_P_MUX13_1_1 0x1c39#define VADC_P_MUX14_1_1 0x1d40#define VADC_P_MUX15_1_1 0x1e41#define VADC_P_MUX16_1_1 0x1f4243#define VADC_P_MUX1_1_3 0x2044#define VADC_P_MUX2_1_3 0x2145#define VADC_P_MUX3_1_3 0x2246#define VADC_P_MUX4_1_3 0x2347#define VADC_P_MUX5_1_3 0x2448#define VADC_P_MUX6_1_3 0x2549#define VADC_P_MUX7_1_3 0x2650#define VADC_P_MUX8_1_3 0x2751#define VADC_P_MUX9_1_3 0x2852#define VADC_P_MUX10_1_3 0x2953#define VADC_P_MUX11_1_3 0x2a54#define VADC_P_MUX12_1_3 0x2b55#define VADC_P_MUX13_1_3 0x2c56#define VADC_P_MUX14_1_3 0x2d57#define VADC_P_MUX15_1_3 0x2e58#define VADC_P_MUX16_1_3 0x2f5960#define VADC_LR_MUX1_BAT_THERM 0x3061#define VADC_LR_MUX2_BAT_ID 0x3162#define VADC_LR_MUX3_XO_THERM 0x3263#define VADC_LR_MUX4_AMUX_THM1 0x3364#define VADC_LR_MUX5_AMUX_THM2 0x3465#define VADC_LR_MUX6_AMUX_THM3 0x3566#define VADC_LR_MUX7_HW_ID 0x3667#define VADC_LR_MUX8_AMUX_THM4 0x3768#define VADC_LR_MUX9_AMUX_THM5 0x3869#define VADC_LR_MUX10_USB_ID 0x3970#define VADC_AMUX_PU1 0x3a71#define VADC_AMUX_PU2 0x3b72#define VADC_LR_MUX3_BUF_XO_THERM 0x3c7374#define VADC_LR_MUX1_PU1_BAT_THERM 0x7075#define VADC_LR_MUX2_PU1_BAT_ID 0x7176#define VADC_LR_MUX3_PU1_XO_THERM 0x7277#define VADC_LR_MUX4_PU1_AMUX_THM1 0x7378#define VADC_LR_MUX5_PU1_AMUX_THM2 0x7479#define VADC_LR_MUX6_PU1_AMUX_THM3 0x7580#define VADC_LR_MUX7_PU1_AMUX_HW_ID 0x7681#define VADC_LR_MUX8_PU1_AMUX_THM4 0x7782#define VADC_LR_MUX9_PU1_AMUX_THM5 0x7883#define VADC_LR_MUX10_PU1_AMUX_USB_ID 0x7984#define VADC_LR_MUX3_BUF_PU1_XO_THERM 0x7c8586#define VADC_LR_MUX1_PU2_BAT_THERM 0xb087#define VADC_LR_MUX2_PU2_BAT_ID 0xb188#define VADC_LR_MUX3_PU2_XO_THERM 0xb289#define VADC_LR_MUX4_PU2_AMUX_THM1 0xb390#define VADC_LR_MUX5_PU2_AMUX_THM2 0xb491#define VADC_LR_MUX6_PU2_AMUX_THM3 0xb592#define VADC_LR_MUX7_PU2_AMUX_HW_ID 0xb693#define VADC_LR_MUX8_PU2_AMUX_THM4 0xb794#define VADC_LR_MUX9_PU2_AMUX_THM5 0xb895#define VADC_LR_MUX10_PU2_AMUX_USB_ID 0xb996#define VADC_LR_MUX3_BUF_PU2_XO_THERM 0xbc9798#define VADC_LR_MUX1_PU1_PU2_BAT_THERM 0xf099#define VADC_LR_MUX2_PU1_PU2_BAT_ID 0xf1100#define VADC_LR_MUX3_PU1_PU2_XO_THERM 0xf2101#define VADC_LR_MUX4_PU1_PU2_AMUX_THM1 0xf3102#define VADC_LR_MUX5_PU1_PU2_AMUX_THM2 0xf4103#define VADC_LR_MUX6_PU1_PU2_AMUX_THM3 0xf5104#define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID 0xf6105#define VADC_LR_MUX8_PU1_PU2_AMUX_THM4 0xf7106#define VADC_LR_MUX9_PU1_PU2_AMUX_THM5 0xf8107#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9108#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc109110/* ADC channels for SPMI PMIC5 */111112#define ADC5_REF_GND 0x00113#define ADC5_1P25VREF 0x01114#define ADC5_VREF_VADC 0x02115#define ADC5_VREF_VADC5_DIV_3 0x82116#define ADC5_VPH_PWR 0x83117#define ADC5_VBAT_SNS 0x84118#define ADC5_VCOIN 0x85119#define ADC5_DIE_TEMP 0x06120#define ADC5_USB_IN_I 0x07121#define ADC5_USB_IN_V_16 0x08122#define ADC5_CHG_TEMP 0x09123#define ADC5_BAT_THERM 0x0a124#define ADC5_BAT_ID 0x0b125#define ADC5_XO_THERM 0x0c126#define ADC5_AMUX_THM1 0x0d127#define ADC5_AMUX_THM2 0x0e128#define ADC5_AMUX_THM3 0x0f129#define ADC5_AMUX_THM4 0x10130#define ADC5_AMUX_THM5 0x11131#define ADC5_GPIO1 0x12132#define ADC5_GPIO2 0x13133#define ADC5_GPIO3 0x14134#define ADC5_GPIO4 0x15135#define ADC5_GPIO5 0x16136#define ADC5_GPIO6 0x17137#define ADC5_GPIO7 0x18138#define ADC5_SBUx 0x99139#define ADC5_MID_CHG_DIV6 0x1e140#define ADC5_OFF 0xff141142/* 30k pull-up1 */143#define ADC5_BAT_THERM_30K_PU 0x2a144#define ADC5_BAT_ID_30K_PU 0x2b145#define ADC5_XO_THERM_30K_PU 0x2c146#define ADC5_AMUX_THM1_30K_PU 0x2d147#define ADC5_AMUX_THM2_30K_PU 0x2e148#define ADC5_AMUX_THM3_30K_PU 0x2f149#define ADC5_AMUX_THM4_30K_PU 0x30150#define ADC5_AMUX_THM5_30K_PU 0x31151#define ADC5_GPIO1_30K_PU 0x32152#define ADC5_GPIO2_30K_PU 0x33153#define ADC5_GPIO3_30K_PU 0x34154#define ADC5_GPIO4_30K_PU 0x35155#define ADC5_GPIO5_30K_PU 0x36156#define ADC5_GPIO6_30K_PU 0x37157#define ADC5_GPIO7_30K_PU 0x38158#define ADC5_SBUx_30K_PU 0x39159160/* 100k pull-up2 */161#define ADC5_BAT_THERM_100K_PU 0x4a162#define ADC5_BAT_ID_100K_PU 0x4b163#define ADC5_XO_THERM_100K_PU 0x4c164#define ADC5_AMUX_THM1_100K_PU 0x4d165#define ADC5_AMUX_THM2_100K_PU 0x4e166#define ADC5_AMUX_THM3_100K_PU 0x4f167#define ADC5_AMUX_THM4_100K_PU 0x50168#define ADC5_AMUX_THM5_100K_PU 0x51169#define ADC5_GPIO1_100K_PU 0x52170#define ADC5_GPIO2_100K_PU 0x53171#define ADC5_GPIO3_100K_PU 0x54172#define ADC5_GPIO4_100K_PU 0x55173#define ADC5_GPIO5_100K_PU 0x56174#define ADC5_GPIO6_100K_PU 0x57175#define ADC5_GPIO7_100K_PU 0x58176#define ADC5_SBUx_100K_PU 0x59177178/* 400k pull-up3 */179#define ADC5_BAT_THERM_400K_PU 0x6a180#define ADC5_BAT_ID_400K_PU 0x6b181#define ADC5_XO_THERM_400K_PU 0x6c182#define ADC5_AMUX_THM1_400K_PU 0x6d183#define ADC5_AMUX_THM2_400K_PU 0x6e184#define ADC5_AMUX_THM3_400K_PU 0x6f185#define ADC5_AMUX_THM4_400K_PU 0x70186#define ADC5_AMUX_THM5_400K_PU 0x71187#define ADC5_GPIO1_400K_PU 0x72188#define ADC5_GPIO2_400K_PU 0x73189#define ADC5_GPIO3_400K_PU 0x74190#define ADC5_GPIO4_400K_PU 0x75191#define ADC5_GPIO5_400K_PU 0x76192#define ADC5_GPIO6_400K_PU 0x77193#define ADC5_GPIO7_400K_PU 0x78194#define ADC5_SBUx_400K_PU 0x79195196/* 1/3 Divider */197#define ADC5_GPIO1_DIV3 0x92198#define ADC5_GPIO2_DIV3 0x93199#define ADC5_GPIO3_DIV3 0x94200#define ADC5_GPIO4_DIV3 0x95201#define ADC5_GPIO5_DIV3 0x96202#define ADC5_GPIO6_DIV3 0x97203#define ADC5_GPIO7_DIV3 0x98204#define ADC5_SBUx_DIV3 0x99205206/* Current and combined current/voltage channels */207#define ADC5_INT_EXT_ISENSE 0xa1208#define ADC5_PARALLEL_ISENSE 0xa5209#define ADC5_CUR_REPLICA_VDS 0xa7210#define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9211#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab212#define ADC5_EXT_SENS_OFFSET 0xad213214#define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0215#define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1216#define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2217#define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3218#define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4219#define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5220221#define ADC5_MAX_CHANNEL 0xc0222223/* ADC channels for ADC for PMIC7 */224225#define ADC7_REF_GND 0x00226#define ADC7_1P25VREF 0x01227#define ADC7_VREF_VADC 0x02228#define ADC7_DIE_TEMP 0x03229230#define ADC7_AMUX_THM1 0x04231#define ADC7_AMUX_THM2 0x05232#define ADC7_AMUX_THM3 0x06233#define ADC7_AMUX_THM4 0x07234#define ADC7_AMUX_THM5 0x08235#define ADC7_AMUX_THM6 0x09236#define ADC7_GPIO1 0x0a237#define ADC7_GPIO2 0x0b238#define ADC7_GPIO3 0x0c239#define ADC7_GPIO4 0x0d240241#define ADC7_SMB_TEMP 0x06242#define ADC7_CHG_TEMP 0x10243#define ADC7_USB_IN_V_16 0x11244#define ADC7_VDC_16 0x12245#define ADC7_CC1_ID 0x13246#define ADC7_VREF_BAT_THERM 0x15247#define ADC7_IIN_FB 0x17248#define ADC7_ICHG_SMB 0x18249#define ADC7_IIN_SMB 0x19250251/* 30k pull-up1 */252#define ADC7_AMUX_THM1_30K_PU 0x24253#define ADC7_AMUX_THM2_30K_PU 0x25254#define ADC7_AMUX_THM3_30K_PU 0x26255#define ADC7_AMUX_THM4_30K_PU 0x27256#define ADC7_AMUX_THM5_30K_PU 0x28257#define ADC7_AMUX_THM6_30K_PU 0x29258#define ADC7_GPIO1_30K_PU 0x2a259#define ADC7_GPIO2_30K_PU 0x2b260#define ADC7_GPIO3_30K_PU 0x2c261#define ADC7_GPIO4_30K_PU 0x2d262#define ADC7_CC1_ID_30K_PU 0x33263264/* 100k pull-up2 */265#define ADC7_AMUX_THM1_100K_PU 0x44266#define ADC7_AMUX_THM2_100K_PU 0x45267#define ADC7_AMUX_THM3_100K_PU 0x46268#define ADC7_AMUX_THM4_100K_PU 0x47269#define ADC7_AMUX_THM5_100K_PU 0x48270#define ADC7_AMUX_THM6_100K_PU 0x49271#define ADC7_GPIO1_100K_PU 0x4a272#define ADC7_GPIO2_100K_PU 0x4b273#define ADC7_GPIO3_100K_PU 0x4c274#define ADC7_GPIO4_100K_PU 0x4d275#define ADC7_CC1_ID_100K_PU 0x53276277/* 400k pull-up3 */278#define ADC7_AMUX_THM1_400K_PU 0x64279#define ADC7_AMUX_THM2_400K_PU 0x65280#define ADC7_AMUX_THM3_400K_PU 0x66281#define ADC7_AMUX_THM4_400K_PU 0x67282#define ADC7_AMUX_THM5_400K_PU 0x68283#define ADC7_AMUX_THM6_400K_PU 0x69284#define ADC7_GPIO1_400K_PU 0x6a285#define ADC7_GPIO2_400K_PU 0x6b286#define ADC7_GPIO3_400K_PU 0x6c287#define ADC7_GPIO4_400K_PU 0x6d288#define ADC7_CC1_ID_400K_PU 0x73289290/* 1/3 Divider */291#define ADC7_GPIO1_DIV3 0x8a292#define ADC7_GPIO2_DIV3 0x8b293#define ADC7_GPIO3_DIV3 0x8c294#define ADC7_GPIO4_DIV3 0x8d295296#define ADC7_VPH_PWR 0x8e297#define ADC7_VBAT_SNS 0x8f298299#define ADC7_SBUx 0x94300#define ADC7_VBAT_2S_MID 0x96301302#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */303304305