Book a Demo!
CoCalc Logo Icon
StoreFeaturesDocsShareSupportNewsAboutPoliciesSign UpSign In
torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/include/dt-bindings/memory/mediatek,mt8189-memory-port.h
38184 views
1
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

2
/*

3
 * Copyright (c) 2025 MediaTek Inc.

4
 * Author: Zhengnan chen <[email protected]>

5
 */

6
#ifndef _DT_BINDINGS_MEMORY_MEDIATEK_MT8189_MEMORY_PORT_H_

7
#define _DT_BINDINGS_MEMORY_MEDIATEK_MT8189_MEMORY_PORT_H_

8


9
#include <dt-bindings/memory/mtk-memory-port.h>

10


11
#define SMI_L0_ID		(0)

12
#define SMI_L1_ID		(1)

13
#define SMI_L2_ID		(2)

14
#define SMI_L4_ID		(3)

15
#define SMI_L7_ID		(4)

16
#define SMI_L9_ID		(5)

17
#define SMI_L11_ID		(6)

18
#define SMI_L13_ID		(7)

19
#define SMI_L14_ID		(8)

20
#define SMI_L16_ID		(9)

21
#define SMI_L17_ID		(10)

22
#define SMI_L19_ID		(11)

23
#define SMI_L20_ID		(12)

24


25
/*

26
 * MM IOMMU supports 16GB dma address. We separate it to four ranges:

27
 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters

28
 * locate in anyone region. BUT:

29
 * a) Make sure all the ports inside a larb are in one range.

30
 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.

31
 *

32
 * This is the suggested mapping in this SoC:

33
 *

34
 * modules		dma-address-region	larbs-ports

35
 * disp/mdp		0 ~ 4G			larb0/1/2

36
 * vcodec		4G ~ 8G                 larb4/7

37
 * imgsys/cam/ipesys	8G ~ 12G                the other larbs.

38
 * N/A			12G ~ 16G

39
 */

40


41
/* Larb0 -- disp */

42
#define M4U_L0_P0_DISP_OVL0_4L_HDR		MTK_M4U_ID(SMI_L0_ID, 0)

43
#define M4U_L0_P1_DISP_OVL0_4L_RDMA0		MTK_M4U_ID(SMI_L0_ID, 1)

44
#define M4U_L0_P2_DISP_OVL1_4L_RDMA1		MTK_M4U_ID(SMI_L0_ID, 2)

45
#define M4U_L0_P3_DISP_OVL0_4L_RDMA2		MTK_M4U_ID(SMI_L0_ID, 3)

46
#define M4U_L0_P4_DISP_OVL1_4L_RDMA3		MTK_M4U_ID(SMI_L0_ID, 4)

47
#define M4U_L0_P5_DISP_RDMA0			MTK_M4U_ID(SMI_L0_ID, 5)

48
#define M4U_L0_P6_DISP_WDMA0			MTK_M4U_ID(SMI_L0_ID, 6)

49
#define M4U_L0_P7_DISP_FAKE_ENG0		MTK_M4U_ID(SMI_L0_ID, 7)

50


51
/* Larb1 -- disp */

52
#define M4U_L1_P0_DISP_OVL1_4L_HDR		MTK_M4U_ID(SMI_L1_ID, 0)

53
#define M4U_L1_P1_DISP_OVL1_4L_RDMA0		MTK_M4U_ID(SMI_L1_ID, 1)

54
#define M4U_L1_P2_DISP_OVL0_4L_RDMA1		MTK_M4U_ID(SMI_L1_ID, 2)

55
#define M4U_L1_P3_DISP_OVL1_4L_RDMA2		MTK_M4U_ID(SMI_L1_ID, 3)

56
#define M4U_L1_P4_DISP_OVL0_4L_RDMA3		MTK_M4U_ID(SMI_L1_ID, 4)

57
#define M4U_L1_P5_DISP_RDMA1			MTK_M4U_ID(SMI_L1_ID, 5)

58
#define M4U_L1_P6_DISP_WDMA1			MTK_M4U_ID(SMI_L1_ID, 6)

59
#define M4U_L1_P7_DISP_FAKE_ENG1		MTK_M4U_ID(SMI_L1_ID, 7)

60


61
/* Larb2 -- mmlsys(mdp) */

62
#define M4U_L2_P0_MDP_RDMA0			MTK_M4U_ID(SMI_L2_ID, 0)

63
#define M4U_L2_P1_MDP_RDMA1			MTK_M4U_ID(SMI_L2_ID, 1)

64
#define M4U_L2_P2_MDP_WROT0			MTK_M4U_ID(SMI_L2_ID, 2)

65
#define M4U_L2_P3_MDP_WROT1			MTK_M4U_ID(SMI_L2_ID, 3)

66
#define M4U_L2_P4_MDP_DUMMY0			MTK_M4U_ID(SMI_L2_ID, 4)

67
#define M4U_L2_P5_MDP_DUMMY1			MTK_M4U_ID(SMI_L2_ID, 5)

68
#define M4U_L2_P6_MDP_RDMA2			MTK_M4U_ID(SMI_L2_ID, 6)

69
#define M4U_L2_P7_MDP_RDMA3			MTK_M4U_ID(SMI_L2_ID, 7)

70
#define M4U_L2_P8_MDP_WROT2			MTK_M4U_ID(SMI_L2_ID, 8)

71
#define M4U_L2_P9_MDP_WROT3			MTK_M4U_ID(SMI_L2_ID, 9)

72
#define M4U_L2_P10_DISP_FAKE0			MTK_M4U_ID(SMI_L2_ID, 10)

73


74
/* Larb3: null */

75


76
/* Larb4 -- vdec */

77
#define M4U_L4_P0_HW_VDEC_MC_EXT		MTK_M4U_ID(SMI_L4_ID, 0)

78
#define M4U_L4_P1_HW_VDEC_UFO_EXT		MTK_M4U_ID(SMI_L4_ID, 1)

79
#define M4U_L4_P2_HW_VDEC_PP_EXT		MTK_M4U_ID(SMI_L4_ID, 2)

80
#define M4U_L4_P3_HW_VDEC_PRED_RD_EXT		MTK_M4U_ID(SMI_L4_ID, 3)

81
#define M4U_L4_P4_HW_VDEC_PRED_WR_EXT		MTK_M4U_ID(SMI_L4_ID, 4)

82
#define M4U_L4_P5_HW_VDEC_PPWRAP_EXT		MTK_M4U_ID(SMI_L4_ID, 5)

83
#define M4U_L4_P6_HW_VDEC_TILE_EXT		MTK_M4U_ID(SMI_L4_ID, 6)

84
#define M4U_L4_P7_HW_VDEC_VLD_EXT		MTK_M4U_ID(SMI_L4_ID, 7)

85
#define M4U_L4_P8_HW_VDEC_VLD2_EXT		MTK_M4U_ID(SMI_L4_ID, 8)

86
#define M4U_L4_P9_HW_VDEC_AVC_MV_EXT		MTK_M4U_ID(SMI_L4_ID, 9)

87
#define M4U_L4_P10_HW_VDEC_RG_CTRL_DMA_EXT	MTK_M4U_ID(SMI_L4_ID, 10)

88
#define M4U_L4_P11_HW_VDEC_UFO_ENC_EXT		MTK_M4U_ID(SMI_L4_ID, 11)

89


90
/* Larb5: null */

91


92
/* Larb6: null */

93


94
/* Larb7 -- venc */

95
#define M4U_L7_P0_VENC_RCPU			MTK_M4U_ID(SMI_L7_ID, 0)

96
#define M4U_L7_P1_VENC_REC			MTK_M4U_ID(SMI_L7_ID, 1)

97
#define M4U_L7_P2_VENC_BSDMA			MTK_M4U_ID(SMI_L7_ID, 2)

98
#define M4U_L7_P3_VENC_SV_COMV			MTK_M4U_ID(SMI_L7_ID, 3)

99
#define M4U_L7_P4_VENC_RD_COMV			MTK_M4U_ID(SMI_L7_ID, 4)

100
#define M4U_L7_P5_JPGENC_Y_RDMA			MTK_M4U_ID(SMI_L7_ID, 5)

101
#define M4U_L7_P6_JPGENC_C_RDMA			MTK_M4U_ID(SMI_L7_ID, 6)

102
#define M4U_L7_P7_JPGENC_Q_RDMA			MTK_M4U_ID(SMI_L7_ID, 7)

103
#define M4U_L7_P8_VENC_SUB_W_LUMA		MTK_M4U_ID(SMI_L7_ID, 8)

104
#define M4U_L7_P9_JPGENC_BSDMA			MTK_M4U_ID(SMI_L7_ID, 9)

105
#define M4U_L7_P10_VENC_CUR_LUMA		MTK_M4U_ID(SMI_L7_ID, 10)

106
#define M4U_L7_P11_VENC_CUR_CHROMA		MTK_M4U_ID(SMI_L7_ID, 11)

107
#define M4U_L7_P12_VENC_REF_LUMA		MTK_M4U_ID(SMI_L7_ID, 12)

108
#define M4U_L7_P13_VENC_REF_CHROMA		MTK_M4U_ID(SMI_L7_ID, 13)

109
#define M4U_L7_P14_VENC_SUB_R_LUMA		MTK_M4U_ID(SMI_L7_ID, 14)

110
#define M4U_L7_P15_JPGDEC_WDMA			MTK_M4U_ID(SMI_L7_ID, 15)

111
#define M4U_L7_P16_JPGDEC_BSDMA			MTK_M4U_ID(SMI_L7_ID, 16)

112
#define M4U_L7_P17_JPGDEC_HUFF_OFFSET		MTK_M4U_ID(SMI_L7_ID, 17)

113


114
/* Larb8: null */

115


116
/* Larb9 --imgsys */

117
#define M4U_L9_P0_IMGI_D1			MTK_M4U_ID(SMI_L9_ID, 0)

118
#define M4U_L9_P1_IMGBI_D1			MTK_M4U_ID(SMI_L9_ID, 1)

119
#define M4U_L9_P2_DMGI_D1			MTK_M4U_ID(SMI_L9_ID, 2)

120
#define M4U_L9_P3_DEPI_D1			MTK_M4U_ID(SMI_L9_ID, 3)

121
#define M4U_L9_P4_LCE_D1			MTK_M4U_ID(SMI_L9_ID, 4)

122
#define M4U_L9_P5_SMTI_D1			MTK_M4U_ID(SMI_L9_ID, 5)

123
#define M4U_L9_P6_SMTO_D2			MTK_M4U_ID(SMI_L9_ID, 6)

124
#define M4U_L9_P7_SMTO_D1			MTK_M4U_ID(SMI_L9_ID, 7)

125
#define M4U_L9_P8_CRZO_D1			MTK_M4U_ID(SMI_L9_ID, 8)

126
#define M4U_L9_P9_IMG3O_D1			MTK_M4U_ID(SMI_L9_ID, 9)

127
#define M4U_L9_P10_VIPI_D1			MTK_M4U_ID(SMI_L9_ID, 10)

128
#define M4U_L9_P11_SMTI_D5			MTK_M4U_ID(SMI_L9_ID, 11)

129
#define M4U_L9_P12_TIMGO_D1			MTK_M4U_ID(SMI_L9_ID, 12)

130
#define M4U_L9_P13_UFBC_W0			MTK_M4U_ID(SMI_L9_ID, 13)

131
#define M4U_L9_P14_UFBC_R0			MTK_M4U_ID(SMI_L9_ID, 14)

132
#define M4U_L9_P15_WPE_RDMA1			MTK_M4U_ID(SMI_L9_ID, 15)

133
#define M4U_L9_P16_WPE_RDMA0			MTK_M4U_ID(SMI_L9_ID, 16)

134
#define M4U_L9_P17_WPE_WDMA			MTK_M4U_ID(SMI_L9_ID, 17)

135
#define M4U_L9_P18_MFB_RDMA0			MTK_M4U_ID(SMI_L9_ID, 18)

136
#define M4U_L9_P19_MFB_RDMA1			MTK_M4U_ID(SMI_L9_ID, 19)

137
#define M4U_L9_P20_MFB_RDMA2			MTK_M4U_ID(SMI_L9_ID, 20)

138
#define M4U_L9_P21_MFB_RDMA3			MTK_M4U_ID(SMI_L9_ID, 21)

139
#define M4U_L9_P22_MFB_RDMA4			MTK_M4U_ID(SMI_L9_ID, 22)

140
#define M4U_L9_P23_MFB_RDMA5			MTK_M4U_ID(SMI_L9_ID, 23)

141
#define M4U_L9_P24_MFB_WDMA0			MTK_M4U_ID(SMI_L9_ID, 24)

142
#define M4U_L9_P25_MFB_WDMA1			MTK_M4U_ID(SMI_L9_ID, 25)

143
#define M4U_L9_P26_RESERVE6			MTK_M4U_ID(SMI_L9_ID, 26)

144
#define M4U_L9_P27_RESERVE7			MTK_M4U_ID(SMI_L9_ID, 27)

145
#define M4U_L9_P28_RESERVE8			MTK_M4U_ID(SMI_L9_ID, 28)

146


147
/* Larb10: null */

148


149
/* Larb11 -- imgsys */

150
#define M4U_L11_P0_IMGI_D1			MTK_M4U_ID(SMI_L11_ID, 0)

151
#define M4U_L11_P1_IMGBI_D1			MTK_M4U_ID(SMI_L11_ID, 1)

152
#define M4U_L11_P2_DMGI_D1			MTK_M4U_ID(SMI_L11_ID, 2)

153
#define M4U_L11_P3_DEPI_D1			MTK_M4U_ID(SMI_L11_ID, 3)

154
#define M4U_L11_P4_LCE_D1			MTK_M4U_ID(SMI_L11_ID, 4)

155
#define M4U_L11_P5_SMTI_D1			MTK_M4U_ID(SMI_L11_ID, 5)

156
#define M4U_L11_P6_SMTO_D2			MTK_M4U_ID(SMI_L11_ID, 6)

157
#define M4U_L11_P7_SMTO_D1			MTK_M4U_ID(SMI_L11_ID, 7)

158
#define M4U_L11_P8_CRZO_D1			MTK_M4U_ID(SMI_L11_ID, 8)

159
#define M4U_L11_P9_IMG3O_D1			MTK_M4U_ID(SMI_L11_ID, 9)

160
#define M4U_L11_P10_VIPI_D1			MTK_M4U_ID(SMI_L11_ID, 10)

161
#define M4U_L11_P11_SMTI_D5			MTK_M4U_ID(SMI_L11_ID, 11)

162
#define M4U_L11_P12_TIMGO_D1			MTK_M4U_ID(SMI_L11_ID, 12)

163
#define M4U_L11_P13_UFBC_W0			MTK_M4U_ID(SMI_L11_ID, 13)

164
#define M4U_L11_P14_UFBC_R0			MTK_M4U_ID(SMI_L11_ID, 14)

165
#define M4U_L11_P15_WPE_RDMA1			MTK_M4U_ID(SMI_L11_ID, 15)

166
#define M4U_L11_P16_WPE_RDMA0			MTK_M4U_ID(SMI_L11_ID, 16)

167
#define M4U_L11_P17_WPE_WDMA			MTK_M4U_ID(SMI_L11_ID, 17)

168
#define M4U_L11_P18_MFB_RDMA0			MTK_M4U_ID(SMI_L11_ID, 18)

169
#define M4U_L11_P19_MFB_RDMA1			MTK_M4U_ID(SMI_L11_ID, 19)

170
#define M4U_L11_P20_MFB_RDMA2			MTK_M4U_ID(SMI_L11_ID, 20)

171
#define M4U_L11_P21_MFB_RDMA3			MTK_M4U_ID(SMI_L11_ID, 21)

172
#define M4U_L11_P22_MFB_RDMA4			MTK_M4U_ID(SMI_L11_ID, 22)

173
#define M4U_L11_P23_MFB_RDMA5			MTK_M4U_ID(SMI_L11_ID, 23)

174
#define M4U_L11_P24_MFB_WDMA0			MTK_M4U_ID(SMI_L11_ID, 24)

175
#define M4U_L11_P25_MFB_WDMA1			MTK_M4U_ID(SMI_L11_ID, 25)

176
#define M4U_L11_P26_RESERVE6			MTK_M4U_ID(SMI_L11_ID, 26)

177
#define M4U_L11_P27_RESERVE7			MTK_M4U_ID(SMI_L11_ID, 27)

178
#define M4U_L11_P28_RESERVE8			MTK_M4U_ID(SMI_L11_ID, 28)

179


180
/* Larb12: null */

181


182
/* Larb13 -- cam */

183
#define M4U_L13_P0_MRAWI			MTK_M4U_ID(SMI_L13_ID, 0)

184
#define M4U_L13_P1_MRAWO_0			MTK_M4U_ID(SMI_L13_ID, 1)

185
#define M4U_L13_P2_MRAWO_1			MTK_M4U_ID(SMI_L13_ID, 2)

186
#define M4U_L13_P3_CAMSV_1			MTK_M4U_ID(SMI_L13_ID, 3)

187
#define M4U_L13_P4_CAMSV_2			MTK_M4U_ID(SMI_L13_ID, 4)

188
#define M4U_L13_P5_CAMSV_3			MTK_M4U_ID(SMI_L13_ID, 5)

189
#define M4U_L13_P6_CAMSV_4			MTK_M4U_ID(SMI_L13_ID, 6)

190
#define M4U_L13_P7_CAMSV_5			MTK_M4U_ID(SMI_L13_ID, 7)

191
#define M4U_L13_P8_CAMSV_6			MTK_M4U_ID(SMI_L13_ID, 8)

192
#define M4U_L13_P9_CCUI				MTK_M4U_ID(SMI_L13_ID, 9)

193
#define M4U_L13_P10_CCUO			MTK_M4U_ID(SMI_L13_ID, 10)

194
#define M4U_L13_P11_FAKE			MTK_M4U_ID(SMI_L13_ID, 11)

195
#define M4U_L13_P12_PDAI_0			MTK_M4U_ID(SMI_L13_ID, 12)

196
#define M4U_L13_P13_PDAI_1			MTK_M4U_ID(SMI_L13_ID, 13)

197
#define M4U_L13_P14_PDAO			MTK_M4U_ID(SMI_L13_ID, 14)

198


199
/* Larb14 -- cam */

200
#define M4U_L14_P0_RESERVE			MTK_M4U_ID(SMI_L14_ID, 0)

201
#define M4U_L14_P1_RESERVE			MTK_M4U_ID(SMI_L14_ID, 1)

202
#define M4U_L14_P2_RESERVE			MTK_M4U_ID(SMI_L14_ID, 2)

203
#define M4U_L14_P3_CAMSV_0			MTK_M4U_ID(SMI_L14_ID, 3)

204
#define M4U_L14_P4_CCUI				MTK_M4U_ID(SMI_L14_ID, 4)

205
#define M4U_L14_P5_CCUO				MTK_M4U_ID(SMI_L14_ID, 5)

206
#define M4U_L14_P6_CAMSV_7			MTK_M4U_ID(SMI_L14_ID, 6)

207
#define M4U_L14_P7_CAMSV_8			MTK_M4U_ID(SMI_L14_ID, 7)

208
#define M4U_L14_P8_CAMSV_9			MTK_M4U_ID(SMI_L14_ID, 8)

209
#define M4U_L14_P9_CAMSV_10			MTK_M4U_ID(SMI_L14_ID, 9)

210


211
/* Larb15: null */

212


213
/* Larb16 -- cam */

214
#define M4U_L16_P0_IMGO_R1_A			MTK_M4U_ID(SMI_L16_ID, 0)

215
#define M4U_L16_P1_RRZO_R1_A			MTK_M4U_ID(SMI_L16_ID, 1)

216
#define M4U_L16_P2_CQI_R1_A			MTK_M4U_ID(SMI_L16_ID, 2)

217
#define M4U_L16_P3_BPCI_R1_A			MTK_M4U_ID(SMI_L16_ID, 3)

218
#define M4U_L16_P4_YUVO_R1_A			MTK_M4U_ID(SMI_L16_ID, 4)

219
#define M4U_L16_P5_UFDI_R2_A			MTK_M4U_ID(SMI_L16_ID, 5)

220
#define M4U_L16_P6_RAWI_R2_A			MTK_M4U_ID(SMI_L16_ID, 6)

221
#define M4U_L16_P7_RAWI_R3_A			MTK_M4U_ID(SMI_L16_ID, 7)

222
#define M4U_L16_P8_AAO_R1_A			MTK_M4U_ID(SMI_L16_ID, 8)

223
#define M4U_L16_P9_AFO_R1_A			MTK_M4U_ID(SMI_L16_ID, 9)

224
#define M4U_L16_P10_FLKO_R1_A			MTK_M4U_ID(SMI_L16_ID, 10)

225
#define M4U_L16_P11_LCESO_R1_A			MTK_M4U_ID(SMI_L16_ID, 11)

226
#define M4U_L16_P12_CRZO_R1_A			MTK_M4U_ID(SMI_L16_ID, 12)

227
#define M4U_L16_P13_LTMSO_R1_A			MTK_M4U_ID(SMI_L16_ID, 13)

228
#define M4U_L16_P14_RSSO_R1_A			MTK_M4U_ID(SMI_L16_ID, 14)

229
#define M4U_L16_P15_AAHO_R1_A			MTK_M4U_ID(SMI_L16_ID, 15)

230
#define M4U_L16_P16_LSCI_R1_A			MTK_M4U_ID(SMI_L16_ID, 16)

231


232
/* Larb17 -- cam */

233
#define M4U_L17_P0_IMGO_R1_B			MTK_M4U_ID(SMI_L17_ID, 0)

234
#define M4U_L17_P1_RRZO_R1_B			MTK_M4U_ID(SMI_L17_ID, 1)

235
#define M4U_L17_P2_CQI_R1_B			MTK_M4U_ID(SMI_L17_ID, 2)

236
#define M4U_L17_P3_BPCI_R1_B			MTK_M4U_ID(SMI_L17_ID, 3)

237
#define M4U_L17_P4_YUVO_R1_B			MTK_M4U_ID(SMI_L17_ID, 4)

238
#define M4U_L17_P5_UFDI_R2_B			MTK_M4U_ID(SMI_L17_ID, 5)

239
#define M4U_L17_P6_RAWI_R2_B			MTK_M4U_ID(SMI_L17_ID, 6)

240
#define M4U_L17_P7_RAWI_R3_B			MTK_M4U_ID(SMI_L17_ID, 7)

241
#define M4U_L17_P8_AAO_R1_B			MTK_M4U_ID(SMI_L17_ID, 8)

242
#define M4U_L17_P9_AFO_R1_B			MTK_M4U_ID(SMI_L17_ID, 9)

243
#define M4U_L17_P10_FLKO_R1_B			MTK_M4U_ID(SMI_L17_ID, 10)

244
#define M4U_L17_P11_LCESO_R1_B			MTK_M4U_ID(SMI_L17_ID, 11)

245
#define M4U_L17_P12_CRZO_R1_B			MTK_M4U_ID(SMI_L17_ID, 12)

246
#define M4U_L17_P13_LTMSO_R1_B			MTK_M4U_ID(SMI_L17_ID, 13)

247
#define M4U_L17_P14_RSSO_R1_B			MTK_M4U_ID(SMI_L17_ID, 14)

248
#define M4U_L17_P15_AAHO_R1_B			MTK_M4U_ID(SMI_L17_ID, 15)

249
#define M4U_L17_P16_LSCI_R1_B			MTK_M4U_ID(SMI_L17_ID, 16)

250


251
/* Larb19 -- ipesys */

252
#define M4U_L19_P0_DVS_RDMA			MTK_M4U_ID(SMI_L19_ID, 0)

253
#define M4U_L19_P1_DVS_WDMA			MTK_M4U_ID(SMI_L19_ID, 1)

254
#define M4U_L19_P2_DVP_RDMA			MTK_M4U_ID(SMI_L19_ID, 2)

255
#define M4U_L19_P3_DVP_WDMA			MTK_M4U_ID(SMI_L19_ID, 3)

256


257
/* Larb20 -- ipesys */

258
#define M4U_L20_P0_FDVT_RDA_0			MTK_M4U_ID(SMI_L20_ID, 0)

259
#define M4U_L20_P1_FDVT_RDB_0			MTK_M4U_ID(SMI_L20_ID, 1)

260
#define M4U_L20_P2_FDVT_WRA_0			MTK_M4U_ID(SMI_L20_ID, 2)

261
#define M4U_L20_P3_FDVT_WRB_0			MTK_M4U_ID(SMI_L20_ID, 3)

262
#define M4U_L20_P4_RSC_RDMA			MTK_M4U_ID(SMI_L20_ID, 4)

263
#define M4U_L20_P5_RSC_WDMA			MTK_M4U_ID(SMI_L20_ID, 5)

264


265
/* fake larb21 for gce */

266
#define M4U_L21_GCE_DM				MTK_M4U_ID(21, 0)

267
#define M4U_L21_GCE_MM				MTK_M4U_ID(21, 1)

268


269
/* fake larb & port for svp and dual svp and wfd */

270
#define M4U_PORT_SVP_HEAP			MTK_M4U_ID(22, 0)

271
#define M4U_PORT_DUAL_SVP_HEAP			MTK_M4U_ID(22, 1)

272
#define M4U_PORT_WFD_HEAP			MTK_M4U_ID(22, 2)

273


274
/* fake larb0 for apu */

275
#define M4U_L0_APU_DATA				MTK_M4U_ID(0, 0)

276
#define M4U_L0_APU_CODE				MTK_M4U_ID(0, 1)

277
#define M4U_L0_APU_SECURE			MTK_M4U_ID(0, 2)

278
#define M4U_L0_APU_VLM				MTK_M4U_ID(0, 3)

279


280
/* infra/peri */

281
#define IFR_IOMMU_PORT_PCIE_0			MTK_IFAIOMMU_PERI_ID(0, 26)

282


283
#endif

284


285