Path: blob/master/include/dt-bindings/memory/mt8167-larb-port.h
26288 views
/* SPDX-License-Identifier: GPL-2.0 */1/*2* Copyright (c) 2020 MediaTek Inc.3* Copyright (c) 2020 BayLibre, SAS4* Author: Honghui Zhang <[email protected]>5* Author: Fabien Parent <[email protected]>6*/7#ifndef _DT_BINDINGS_MEMORY_MT8167_LARB_PORT_H_8#define _DT_BINDINGS_MEMORY_MT8167_LARB_PORT_H_910#include <dt-bindings/memory/mtk-memory-port.h>1112#define M4U_LARB0_ID 013#define M4U_LARB1_ID 114#define M4U_LARB2_ID 21516/* larb0 */17#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)18#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1)19#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2)20#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 3)21#define M4U_PORT_MDP_RDMA MTK_M4U_ID(M4U_LARB0_ID, 4)22#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 5)23#define M4U_PORT_MDP_WROT MTK_M4U_ID(M4U_LARB0_ID, 6)24#define M4U_PORT_DISP_FAKE MTK_M4U_ID(M4U_LARB0_ID, 7)2526/* larb1*/27#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB1_ID, 0)28#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB1_ID, 1)29#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB1_ID, 2)30#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB1_ID, 3)31#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB1_ID, 4)32#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB1_ID, 5)33#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 6)34#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB1_ID, 7)35#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB1_ID, 8)36#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 9)37#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 10)38#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 11)39#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 12)4041/* larb2*/42#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0)43#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 1)44#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 2)45#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 3)46#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 4)47#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 5)48#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 6)4950#endif515253