Path: blob/master/include/dt-bindings/memory/tegra186-mc.h
26285 views
#ifndef DT_BINDINGS_MEMORY_TEGRA186_MC_H1#define DT_BINDINGS_MEMORY_TEGRA186_MC_H23/* special clients */4#define TEGRA186_SID_INVALID 0x005#define TEGRA186_SID_PASSTHROUGH 0x7f67/* host1x clients */8#define TEGRA186_SID_HOST1X 0x019#define TEGRA186_SID_CSI 0x0210#define TEGRA186_SID_VIC 0x0311#define TEGRA186_SID_VI 0x0412#define TEGRA186_SID_ISP 0x0513#define TEGRA186_SID_NVDEC 0x0614#define TEGRA186_SID_NVENC 0x0715#define TEGRA186_SID_NVJPG 0x0816#define TEGRA186_SID_NVDISPLAY 0x0917#define TEGRA186_SID_TSEC 0x0a18#define TEGRA186_SID_TSECB 0x0b19#define TEGRA186_SID_SE 0x0c20#define TEGRA186_SID_SE1 0x0d21#define TEGRA186_SID_SE2 0x0e22#define TEGRA186_SID_SE3 0x0f2324/* GPU clients */25#define TEGRA186_SID_GPU 0x102627/* other SoC clients */28#define TEGRA186_SID_AFI 0x1129#define TEGRA186_SID_HDA 0x1230#define TEGRA186_SID_ETR 0x1331#define TEGRA186_SID_EQOS 0x1432#define TEGRA186_SID_UFSHC 0x1533#define TEGRA186_SID_AON 0x1634#define TEGRA186_SID_SDMMC4 0x1735#define TEGRA186_SID_SDMMC3 0x1836#define TEGRA186_SID_SDMMC2 0x1937#define TEGRA186_SID_SDMMC1 0x1a38#define TEGRA186_SID_XUSB_HOST 0x1b39#define TEGRA186_SID_XUSB_DEV 0x1c40#define TEGRA186_SID_SATA 0x1d41#define TEGRA186_SID_APE 0x1e42#define TEGRA186_SID_SCE 0x1f4344/* GPC DMA clients */45#define TEGRA186_SID_GPCDMA_0 0x2046#define TEGRA186_SID_GPCDMA_1 0x2147#define TEGRA186_SID_GPCDMA_2 0x2248#define TEGRA186_SID_GPCDMA_3 0x2349#define TEGRA186_SID_GPCDMA_4 0x2450#define TEGRA186_SID_GPCDMA_5 0x2551#define TEGRA186_SID_GPCDMA_6 0x2652#define TEGRA186_SID_GPCDMA_7 0x275354/* APE DMA clients */55#define TEGRA186_SID_APE_1 0x2856#define TEGRA186_SID_APE_2 0x295758/* camera RTCPU */59#define TEGRA186_SID_RCE 0x2a6061/* camera RTCPU on host1x address space */62#define TEGRA186_SID_RCE_1X 0x2b6364/* APE DMA clients */65#define TEGRA186_SID_APE_3 0x2c6667/* camera RTCPU running on APE */68#define TEGRA186_SID_APE_CAM 0x2d69#define TEGRA186_SID_APE_CAM_1X 0x2e7071/*72* The BPMP has its SID value hardcoded in the firmware. Changing it requires73* considerable effort.74*/75#define TEGRA186_SID_BPMP 0x327677/* for SMMU tests */78#define TEGRA186_SID_SMMU_TEST 0x337980/* host1x virtualization channels */81#define TEGRA186_SID_HOST1X_CTX0 0x3882#define TEGRA186_SID_HOST1X_CTX1 0x3983#define TEGRA186_SID_HOST1X_CTX2 0x3a84#define TEGRA186_SID_HOST1X_CTX3 0x3b85#define TEGRA186_SID_HOST1X_CTX4 0x3c86#define TEGRA186_SID_HOST1X_CTX5 0x3d87#define TEGRA186_SID_HOST1X_CTX6 0x3e88#define TEGRA186_SID_HOST1X_CTX7 0x3f8990/* host1x command buffers */91#define TEGRA186_SID_HOST1X_VM0 0x4092#define TEGRA186_SID_HOST1X_VM1 0x4193#define TEGRA186_SID_HOST1X_VM2 0x4294#define TEGRA186_SID_HOST1X_VM3 0x4395#define TEGRA186_SID_HOST1X_VM4 0x4496#define TEGRA186_SID_HOST1X_VM5 0x4597#define TEGRA186_SID_HOST1X_VM6 0x4698#define TEGRA186_SID_HOST1X_VM7 0x4799100/* SE data buffers */101#define TEGRA186_SID_SE_VM0 0x48102#define TEGRA186_SID_SE_VM1 0x49103#define TEGRA186_SID_SE_VM2 0x4a104#define TEGRA186_SID_SE_VM3 0x4b105#define TEGRA186_SID_SE_VM4 0x4c106#define TEGRA186_SID_SE_VM5 0x4d107#define TEGRA186_SID_SE_VM6 0x4e108#define TEGRA186_SID_SE_VM7 0x4f109110/*111* memory client IDs112*/113114/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */115#define TEGRA186_MEMORY_CLIENT_PTCR 0x00116/* PCIE reads */117#define TEGRA186_MEMORY_CLIENT_AFIR 0x0e118/* High-definition audio (HDA) reads */119#define TEGRA186_MEMORY_CLIENT_HDAR 0x15120/* Host channel data reads */121#define TEGRA186_MEMORY_CLIENT_HOST1XDMAR 0x16122#define TEGRA186_MEMORY_CLIENT_NVENCSRD 0x1c123/* SATA reads */124#define TEGRA186_MEMORY_CLIENT_SATAR 0x1f125/* Reads from Cortex-A9 4 CPU cores via the L2 cache */126#define TEGRA186_MEMORY_CLIENT_MPCORER 0x27127#define TEGRA186_MEMORY_CLIENT_NVENCSWR 0x2b128/* PCIE writes */129#define TEGRA186_MEMORY_CLIENT_AFIW 0x31130/* High-definition audio (HDA) writes */131#define TEGRA186_MEMORY_CLIENT_HDAW 0x35132/* Writes from Cortex-A9 4 CPU cores via the L2 cache */133#define TEGRA186_MEMORY_CLIENT_MPCOREW 0x39134/* SATA writes */135#define TEGRA186_MEMORY_CLIENT_SATAW 0x3d136/* ISP Read client for Crossbar A */137#define TEGRA186_MEMORY_CLIENT_ISPRA 0x44138/* ISP Write client for Crossbar A */139#define TEGRA186_MEMORY_CLIENT_ISPWA 0x46140/* ISP Write client Crossbar B */141#define TEGRA186_MEMORY_CLIENT_ISPWB 0x47142/* XUSB reads */143#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTR 0x4a144/* XUSB_HOST writes */145#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTW 0x4b146/* XUSB reads */147#define TEGRA186_MEMORY_CLIENT_XUSB_DEVR 0x4c148/* XUSB_DEV writes */149#define TEGRA186_MEMORY_CLIENT_XUSB_DEVW 0x4d150/* TSEC Memory Return Data Client Description */151#define TEGRA186_MEMORY_CLIENT_TSECSRD 0x54152/* TSEC Memory Write Client Description */153#define TEGRA186_MEMORY_CLIENT_TSECSWR 0x55154/* 3D, ltcx reads instance 0 */155#define TEGRA186_MEMORY_CLIENT_GPUSRD 0x58156/* 3D, ltcx writes instance 0 */157#define TEGRA186_MEMORY_CLIENT_GPUSWR 0x59158/* sdmmca memory read client */159#define TEGRA186_MEMORY_CLIENT_SDMMCRA 0x60160/* sdmmcbmemory read client */161#define TEGRA186_MEMORY_CLIENT_SDMMCRAA 0x61162/* sdmmc memory read client */163#define TEGRA186_MEMORY_CLIENT_SDMMCR 0x62164/* sdmmcd memory read client */165#define TEGRA186_MEMORY_CLIENT_SDMMCRAB 0x63166/* sdmmca memory write client */167#define TEGRA186_MEMORY_CLIENT_SDMMCWA 0x64168/* sdmmcb memory write client */169#define TEGRA186_MEMORY_CLIENT_SDMMCWAA 0x65170/* sdmmc memory write client */171#define TEGRA186_MEMORY_CLIENT_SDMMCW 0x66172/* sdmmcd memory write client */173#define TEGRA186_MEMORY_CLIENT_SDMMCWAB 0x67174#define TEGRA186_MEMORY_CLIENT_VICSRD 0x6c175#define TEGRA186_MEMORY_CLIENT_VICSWR 0x6d176/* VI Write client */177#define TEGRA186_MEMORY_CLIENT_VIW 0x72178#define TEGRA186_MEMORY_CLIENT_NVDECSRD 0x78179#define TEGRA186_MEMORY_CLIENT_NVDECSWR 0x79180/* Audio Processing (APE) engine reads */181#define TEGRA186_MEMORY_CLIENT_APER 0x7a182/* Audio Processing (APE) engine writes */183#define TEGRA186_MEMORY_CLIENT_APEW 0x7b184#define TEGRA186_MEMORY_CLIENT_NVJPGSRD 0x7e185#define TEGRA186_MEMORY_CLIENT_NVJPGSWR 0x7f186/* SE Memory Return Data Client Description */187#define TEGRA186_MEMORY_CLIENT_SESRD 0x80188/* SE Memory Write Client Description */189#define TEGRA186_MEMORY_CLIENT_SESWR 0x81190/* ETR reads */191#define TEGRA186_MEMORY_CLIENT_ETRR 0x84192/* ETR writes */193#define TEGRA186_MEMORY_CLIENT_ETRW 0x85194/* TSECB Memory Return Data Client Description */195#define TEGRA186_MEMORY_CLIENT_TSECSRDB 0x86196/* TSECB Memory Write Client Description */197#define TEGRA186_MEMORY_CLIENT_TSECSWRB 0x87198/* 3D, ltcx reads instance 1 */199#define TEGRA186_MEMORY_CLIENT_GPUSRD2 0x88200/* 3D, ltcx writes instance 1 */201#define TEGRA186_MEMORY_CLIENT_GPUSWR2 0x89202/* AXI Switch read client */203#define TEGRA186_MEMORY_CLIENT_AXISR 0x8c204/* AXI Switch write client */205#define TEGRA186_MEMORY_CLIENT_AXISW 0x8d206/* EQOS read client */207#define TEGRA186_MEMORY_CLIENT_EQOSR 0x8e208/* EQOS write client */209#define TEGRA186_MEMORY_CLIENT_EQOSW 0x8f210/* UFSHC read client */211#define TEGRA186_MEMORY_CLIENT_UFSHCR 0x90212/* UFSHC write client */213#define TEGRA186_MEMORY_CLIENT_UFSHCW 0x91214/* NVDISPLAY read client */215#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR 0x92216/* BPMP read client */217#define TEGRA186_MEMORY_CLIENT_BPMPR 0x93218/* BPMP write client */219#define TEGRA186_MEMORY_CLIENT_BPMPW 0x94220/* BPMPDMA read client */221#define TEGRA186_MEMORY_CLIENT_BPMPDMAR 0x95222/* BPMPDMA write client */223#define TEGRA186_MEMORY_CLIENT_BPMPDMAW 0x96224/* AON read client */225#define TEGRA186_MEMORY_CLIENT_AONR 0x97226/* AON write client */227#define TEGRA186_MEMORY_CLIENT_AONW 0x98228/* AONDMA read client */229#define TEGRA186_MEMORY_CLIENT_AONDMAR 0x99230/* AONDMA write client */231#define TEGRA186_MEMORY_CLIENT_AONDMAW 0x9a232/* SCE read client */233#define TEGRA186_MEMORY_CLIENT_SCER 0x9b234/* SCE write client */235#define TEGRA186_MEMORY_CLIENT_SCEW 0x9c236/* SCEDMA read client */237#define TEGRA186_MEMORY_CLIENT_SCEDMAR 0x9d238/* SCEDMA write client */239#define TEGRA186_MEMORY_CLIENT_SCEDMAW 0x9e240/* APEDMA read client */241#define TEGRA186_MEMORY_CLIENT_APEDMAR 0x9f242/* APEDMA write client */243#define TEGRA186_MEMORY_CLIENT_APEDMAW 0xa0244/* NVDISPLAY read client instance 2 */245#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 0xa1246#define TEGRA186_MEMORY_CLIENT_VICSRD1 0xa2247#define TEGRA186_MEMORY_CLIENT_NVDECSRD1 0xa3248249#endif250251252