Path: blob/master/include/dt-bindings/memory/tegra194-mc.h
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#ifndef DT_BINDINGS_MEMORY_TEGRA194_MC_H1#define DT_BINDINGS_MEMORY_TEGRA194_MC_H23/* special clients */4#define TEGRA194_SID_INVALID 0x005#define TEGRA194_SID_PASSTHROUGH 0x7f67/* host1x clients */8#define TEGRA194_SID_HOST1X 0x019#define TEGRA194_SID_CSI 0x0210#define TEGRA194_SID_VIC 0x0311#define TEGRA194_SID_VI 0x0412#define TEGRA194_SID_ISP 0x0513#define TEGRA194_SID_NVDEC 0x0614#define TEGRA194_SID_NVENC 0x0715#define TEGRA194_SID_NVJPG 0x0816#define TEGRA194_SID_NVDISPLAY 0x0917#define TEGRA194_SID_TSEC 0x0a18#define TEGRA194_SID_TSECB 0x0b19#define TEGRA194_SID_SE 0x0c20#define TEGRA194_SID_SE1 0x0d21#define TEGRA194_SID_SE2 0x0e22#define TEGRA194_SID_SE3 0x0f2324/* GPU clients */25#define TEGRA194_SID_GPU 0x102627/* other SoC clients */28#define TEGRA194_SID_AFI 0x1129#define TEGRA194_SID_HDA 0x1230#define TEGRA194_SID_ETR 0x1331#define TEGRA194_SID_EQOS 0x1432#define TEGRA194_SID_UFSHC 0x1533#define TEGRA194_SID_AON 0x1634#define TEGRA194_SID_SDMMC4 0x1735#define TEGRA194_SID_SDMMC3 0x1836#define TEGRA194_SID_SDMMC2 0x1937#define TEGRA194_SID_SDMMC1 0x1a38#define TEGRA194_SID_XUSB_HOST 0x1b39#define TEGRA194_SID_XUSB_DEV 0x1c40#define TEGRA194_SID_SATA 0x1d41#define TEGRA194_SID_APE 0x1e42#define TEGRA194_SID_SCE 0x1f4344/* GPC DMA clients */45#define TEGRA194_SID_GPCDMA_0 0x2046#define TEGRA194_SID_GPCDMA_1 0x2147#define TEGRA194_SID_GPCDMA_2 0x2248#define TEGRA194_SID_GPCDMA_3 0x2349#define TEGRA194_SID_GPCDMA_4 0x2450#define TEGRA194_SID_GPCDMA_5 0x2551#define TEGRA194_SID_GPCDMA_6 0x2652#define TEGRA194_SID_GPCDMA_7 0x275354/* APE DMA clients */55#define TEGRA194_SID_APE_1 0x2856#define TEGRA194_SID_APE_2 0x295758/* camera RTCPU */59#define TEGRA194_SID_RCE 0x2a6061/* camera RTCPU on host1x address space */62#define TEGRA194_SID_RCE_1X 0x2b6364/* APE DMA clients */65#define TEGRA194_SID_APE_3 0x2c6667/* camera RTCPU running on APE */68#define TEGRA194_SID_APE_CAM 0x2d69#define TEGRA194_SID_APE_CAM_1X 0x2e7071#define TEGRA194_SID_RCE_RM 0x2f72#define TEGRA194_SID_VI_FALCON 0x3073#define TEGRA194_SID_ISP_FALCON 0x317475/*76* The BPMP has its SID value hardcoded in the firmware. Changing it requires77* considerable effort.78*/79#define TEGRA194_SID_BPMP 0x328081/* for SMMU tests */82#define TEGRA194_SID_SMMU_TEST 0x338384/* host1x virtualization channels */85#define TEGRA194_SID_HOST1X_CTX0 0x3886#define TEGRA194_SID_HOST1X_CTX1 0x3987#define TEGRA194_SID_HOST1X_CTX2 0x3a88#define TEGRA194_SID_HOST1X_CTX3 0x3b89#define TEGRA194_SID_HOST1X_CTX4 0x3c90#define TEGRA194_SID_HOST1X_CTX5 0x3d91#define TEGRA194_SID_HOST1X_CTX6 0x3e92#define TEGRA194_SID_HOST1X_CTX7 0x3f9394/* host1x command buffers */95#define TEGRA194_SID_HOST1X_VM0 0x4096#define TEGRA194_SID_HOST1X_VM1 0x4197#define TEGRA194_SID_HOST1X_VM2 0x4298#define TEGRA194_SID_HOST1X_VM3 0x4399#define TEGRA194_SID_HOST1X_VM4 0x44100#define TEGRA194_SID_HOST1X_VM5 0x45101#define TEGRA194_SID_HOST1X_VM6 0x46102#define TEGRA194_SID_HOST1X_VM7 0x47103104/* SE data buffers */105#define TEGRA194_SID_SE_VM0 0x48106#define TEGRA194_SID_SE_VM1 0x49107#define TEGRA194_SID_SE_VM2 0x4a108#define TEGRA194_SID_SE_VM3 0x4b109#define TEGRA194_SID_SE_VM4 0x4c110#define TEGRA194_SID_SE_VM5 0x4d111#define TEGRA194_SID_SE_VM6 0x4e112#define TEGRA194_SID_SE_VM7 0x4f113114#define TEGRA194_SID_MIU 0x50115116#define TEGRA194_SID_NVDLA0 0x51117#define TEGRA194_SID_NVDLA1 0x52118119#define TEGRA194_SID_PVA0 0x53120#define TEGRA194_SID_PVA1 0x54121#define TEGRA194_SID_NVENC1 0x55122#define TEGRA194_SID_PCIE0 0x56123#define TEGRA194_SID_PCIE1 0x57124#define TEGRA194_SID_PCIE2 0x58125#define TEGRA194_SID_PCIE3 0x59126#define TEGRA194_SID_PCIE4 0x5a127#define TEGRA194_SID_PCIE5 0x5b128#define TEGRA194_SID_NVDEC1 0x5c129130#define TEGRA194_SID_XUSB_VF0 0x5d131#define TEGRA194_SID_XUSB_VF1 0x5e132#define TEGRA194_SID_XUSB_VF2 0x5f133#define TEGRA194_SID_XUSB_VF3 0x60134135#define TEGRA194_SID_RCE_VM3 0x61136#define TEGRA194_SID_VI_VM2 0x62137#define TEGRA194_SID_VI_VM3 0x63138#define TEGRA194_SID_RCE_SERVER 0x64139140/*141* memory client IDs142*/143144/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */145#define TEGRA194_MEMORY_CLIENT_PTCR 0x00146/* MSS internal memqual MIU7 read clients */147#define TEGRA194_MEMORY_CLIENT_MIU7R 0x01148/* MSS internal memqual MIU7 write clients */149#define TEGRA194_MEMORY_CLIENT_MIU7W 0x02150/* High-definition audio (HDA) read clients */151#define TEGRA194_MEMORY_CLIENT_HDAR 0x15152/* Host channel data read clients */153#define TEGRA194_MEMORY_CLIENT_HOST1XDMAR 0x16154#define TEGRA194_MEMORY_CLIENT_NVENCSRD 0x1c155/* SATA read clients */156#define TEGRA194_MEMORY_CLIENT_SATAR 0x1f157/* Reads from Cortex-A9 4 CPU cores via the L2 cache */158#define TEGRA194_MEMORY_CLIENT_MPCORER 0x27159#define TEGRA194_MEMORY_CLIENT_NVENCSWR 0x2b160/* High-definition audio (HDA) write clients */161#define TEGRA194_MEMORY_CLIENT_HDAW 0x35162/* Writes from Cortex-A9 4 CPU cores via the L2 cache */163#define TEGRA194_MEMORY_CLIENT_MPCOREW 0x39164/* SATA write clients */165#define TEGRA194_MEMORY_CLIENT_SATAW 0x3d166/* ISP read client for Crossbar A */167#define TEGRA194_MEMORY_CLIENT_ISPRA 0x44168/* ISP read client 1 for Crossbar A */169#define TEGRA194_MEMORY_CLIENT_ISPFALR 0x45170/* ISP Write client for Crossbar A */171#define TEGRA194_MEMORY_CLIENT_ISPWA 0x46172/* ISP Write client Crossbar B */173#define TEGRA194_MEMORY_CLIENT_ISPWB 0x47174/* XUSB_HOST read clients */175#define TEGRA194_MEMORY_CLIENT_XUSB_HOSTR 0x4a176/* XUSB_HOST write clients */177#define TEGRA194_MEMORY_CLIENT_XUSB_HOSTW 0x4b178/* XUSB read clients */179#define TEGRA194_MEMORY_CLIENT_XUSB_DEVR 0x4c180/* XUSB_DEV write clients */181#define TEGRA194_MEMORY_CLIENT_XUSB_DEVW 0x4d182/* sdmmca memory read client */183#define TEGRA194_MEMORY_CLIENT_SDMMCRA 0x60184/* sdmmc memory read client */185#define TEGRA194_MEMORY_CLIENT_SDMMCR 0x62186/* sdmmcd memory read client */187#define TEGRA194_MEMORY_CLIENT_SDMMCRAB 0x63188/* sdmmca memory write client */189#define TEGRA194_MEMORY_CLIENT_SDMMCWA 0x64190/* sdmmc memory write client */191#define TEGRA194_MEMORY_CLIENT_SDMMCW 0x66192/* sdmmcd memory write client */193#define TEGRA194_MEMORY_CLIENT_SDMMCWAB 0x67194#define TEGRA194_MEMORY_CLIENT_VICSRD 0x6c195#define TEGRA194_MEMORY_CLIENT_VICSWR 0x6d196/* VI Write client */197#define TEGRA194_MEMORY_CLIENT_VIW 0x72198#define TEGRA194_MEMORY_CLIENT_NVDECSRD 0x78199#define TEGRA194_MEMORY_CLIENT_NVDECSWR 0x79200/* Audio Processing (APE) engine read clients */201#define TEGRA194_MEMORY_CLIENT_APER 0x7a202/* Audio Processing (APE) engine write clients */203#define TEGRA194_MEMORY_CLIENT_APEW 0x7b204#define TEGRA194_MEMORY_CLIENT_NVJPGSRD 0x7e205#define TEGRA194_MEMORY_CLIENT_NVJPGSWR 0x7f206/* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */207#define TEGRA194_MEMORY_CLIENT_AXIAPR 0x82208/* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */209#define TEGRA194_MEMORY_CLIENT_AXIAPW 0x83210/* ETR read clients */211#define TEGRA194_MEMORY_CLIENT_ETRR 0x84212/* ETR write clients */213#define TEGRA194_MEMORY_CLIENT_ETRW 0x85214/* AXI Switch read client */215#define TEGRA194_MEMORY_CLIENT_AXISR 0x8c216/* AXI Switch write client */217#define TEGRA194_MEMORY_CLIENT_AXISW 0x8d218/* EQOS read client */219#define TEGRA194_MEMORY_CLIENT_EQOSR 0x8e220/* EQOS write client */221#define TEGRA194_MEMORY_CLIENT_EQOSW 0x8f222/* UFSHC read client */223#define TEGRA194_MEMORY_CLIENT_UFSHCR 0x90224/* UFSHC write client */225#define TEGRA194_MEMORY_CLIENT_UFSHCW 0x91226/* NVDISPLAY read client */227#define TEGRA194_MEMORY_CLIENT_NVDISPLAYR 0x92228/* BPMP read client */229#define TEGRA194_MEMORY_CLIENT_BPMPR 0x93230/* BPMP write client */231#define TEGRA194_MEMORY_CLIENT_BPMPW 0x94232/* BPMPDMA read client */233#define TEGRA194_MEMORY_CLIENT_BPMPDMAR 0x95234/* BPMPDMA write client */235#define TEGRA194_MEMORY_CLIENT_BPMPDMAW 0x96236/* AON read client */237#define TEGRA194_MEMORY_CLIENT_AONR 0x97238/* AON write client */239#define TEGRA194_MEMORY_CLIENT_AONW 0x98240/* AONDMA read client */241#define TEGRA194_MEMORY_CLIENT_AONDMAR 0x99242/* AONDMA write client */243#define TEGRA194_MEMORY_CLIENT_AONDMAW 0x9a244/* SCE read client */245#define TEGRA194_MEMORY_CLIENT_SCER 0x9b246/* SCE write client */247#define TEGRA194_MEMORY_CLIENT_SCEW 0x9c248/* SCEDMA read client */249#define TEGRA194_MEMORY_CLIENT_SCEDMAR 0x9d250/* SCEDMA write client */251#define TEGRA194_MEMORY_CLIENT_SCEDMAW 0x9e252/* APEDMA read client */253#define TEGRA194_MEMORY_CLIENT_APEDMAR 0x9f254/* APEDMA write client */255#define TEGRA194_MEMORY_CLIENT_APEDMAW 0xa0256/* NVDISPLAY read client instance 2 */257#define TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 0xa1258#define TEGRA194_MEMORY_CLIENT_VICSRD1 0xa2259#define TEGRA194_MEMORY_CLIENT_NVDECSRD1 0xa3260/* MSS internal memqual MIU0 read clients */261#define TEGRA194_MEMORY_CLIENT_MIU0R 0xa6262/* MSS internal memqual MIU0 write clients */263#define TEGRA194_MEMORY_CLIENT_MIU0W 0xa7264/* MSS internal memqual MIU1 read clients */265#define TEGRA194_MEMORY_CLIENT_MIU1R 0xa8266/* MSS internal memqual MIU1 write clients */267#define TEGRA194_MEMORY_CLIENT_MIU1W 0xa9268/* MSS internal memqual MIU2 read clients */269#define TEGRA194_MEMORY_CLIENT_MIU2R 0xae270/* MSS internal memqual MIU2 write clients */271#define TEGRA194_MEMORY_CLIENT_MIU2W 0xaf272/* MSS internal memqual MIU3 read clients */273#define TEGRA194_MEMORY_CLIENT_MIU3R 0xb0274/* MSS internal memqual MIU3 write clients */275#define TEGRA194_MEMORY_CLIENT_MIU3W 0xb1276/* MSS internal memqual MIU4 read clients */277#define TEGRA194_MEMORY_CLIENT_MIU4R 0xb2278/* MSS internal memqual MIU4 write clients */279#define TEGRA194_MEMORY_CLIENT_MIU4W 0xb3280#define TEGRA194_MEMORY_CLIENT_DPMUR 0xb4281#define TEGRA194_MEMORY_CLIENT_DPMUW 0xb5282#define TEGRA194_MEMORY_CLIENT_NVL0R 0xb6283#define TEGRA194_MEMORY_CLIENT_NVL0W 0xb7284#define TEGRA194_MEMORY_CLIENT_NVL1R 0xb8285#define TEGRA194_MEMORY_CLIENT_NVL1W 0xb9286#define TEGRA194_MEMORY_CLIENT_NVL2R 0xba287#define TEGRA194_MEMORY_CLIENT_NVL2W 0xbb288/* VI FLACON read clients */289#define TEGRA194_MEMORY_CLIENT_VIFALR 0xbc290/* VIFAL write clients */291#define TEGRA194_MEMORY_CLIENT_VIFALW 0xbd292/* DLA0ARDA read clients */293#define TEGRA194_MEMORY_CLIENT_DLA0RDA 0xbe294/* DLA0 Falcon read clients */295#define TEGRA194_MEMORY_CLIENT_DLA0FALRDB 0xbf296/* DLA0 write clients */297#define TEGRA194_MEMORY_CLIENT_DLA0WRA 0xc0298/* DLA0 write clients */299#define TEGRA194_MEMORY_CLIENT_DLA0FALWRB 0xc1300/* DLA1ARDA read clients */301#define TEGRA194_MEMORY_CLIENT_DLA1RDA 0xc2302/* DLA1 Falcon read clients */303#define TEGRA194_MEMORY_CLIENT_DLA1FALRDB 0xc3304/* DLA1 write clients */305#define TEGRA194_MEMORY_CLIENT_DLA1WRA 0xc4306/* DLA1 write clients */307#define TEGRA194_MEMORY_CLIENT_DLA1FALWRB 0xc5308/* PVA0RDA read clients */309#define TEGRA194_MEMORY_CLIENT_PVA0RDA 0xc6310/* PVA0RDB read clients */311#define TEGRA194_MEMORY_CLIENT_PVA0RDB 0xc7312/* PVA0RDC read clients */313#define TEGRA194_MEMORY_CLIENT_PVA0RDC 0xc8314/* PVA0WRA write clients */315#define TEGRA194_MEMORY_CLIENT_PVA0WRA 0xc9316/* PVA0WRB write clients */317#define TEGRA194_MEMORY_CLIENT_PVA0WRB 0xca318/* PVA0WRC write clients */319#define TEGRA194_MEMORY_CLIENT_PVA0WRC 0xcb320/* PVA1RDA read clients */321#define TEGRA194_MEMORY_CLIENT_PVA1RDA 0xcc322/* PVA1RDB read clients */323#define TEGRA194_MEMORY_CLIENT_PVA1RDB 0xcd324/* PVA1RDC read clients */325#define TEGRA194_MEMORY_CLIENT_PVA1RDC 0xce326/* PVA1WRA write clients */327#define TEGRA194_MEMORY_CLIENT_PVA1WRA 0xcf328/* PVA1WRB write clients */329#define TEGRA194_MEMORY_CLIENT_PVA1WRB 0xd0330/* PVA1WRC write clients */331#define TEGRA194_MEMORY_CLIENT_PVA1WRC 0xd1332/* RCE read client */333#define TEGRA194_MEMORY_CLIENT_RCER 0xd2334/* RCE write client */335#define TEGRA194_MEMORY_CLIENT_RCEW 0xd3336/* RCEDMA read client */337#define TEGRA194_MEMORY_CLIENT_RCEDMAR 0xd4338/* RCEDMA write client */339#define TEGRA194_MEMORY_CLIENT_RCEDMAW 0xd5340#define TEGRA194_MEMORY_CLIENT_NVENC1SRD 0xd6341#define TEGRA194_MEMORY_CLIENT_NVENC1SWR 0xd7342/* PCIE0 read clients */343#define TEGRA194_MEMORY_CLIENT_PCIE0R 0xd8344/* PCIE0 write clients */345#define TEGRA194_MEMORY_CLIENT_PCIE0W 0xd9346/* PCIE1 read clients */347#define TEGRA194_MEMORY_CLIENT_PCIE1R 0xda348/* PCIE1 write clients */349#define TEGRA194_MEMORY_CLIENT_PCIE1W 0xdb350/* PCIE2 read clients */351#define TEGRA194_MEMORY_CLIENT_PCIE2AR 0xdc352/* PCIE2 write clients */353#define TEGRA194_MEMORY_CLIENT_PCIE2AW 0xdd354/* PCIE3 read clients */355#define TEGRA194_MEMORY_CLIENT_PCIE3R 0xde356/* PCIE3 write clients */357#define TEGRA194_MEMORY_CLIENT_PCIE3W 0xdf358/* PCIE4 read clients */359#define TEGRA194_MEMORY_CLIENT_PCIE4R 0xe0360/* PCIE4 write clients */361#define TEGRA194_MEMORY_CLIENT_PCIE4W 0xe1362/* PCIE5 read clients */363#define TEGRA194_MEMORY_CLIENT_PCIE5R 0xe2364/* PCIE5 write clients */365#define TEGRA194_MEMORY_CLIENT_PCIE5W 0xe3366/* ISP read client 1 for Crossbar A */367#define TEGRA194_MEMORY_CLIENT_ISPFALW 0xe4368#define TEGRA194_MEMORY_CLIENT_NVL3R 0xe5369#define TEGRA194_MEMORY_CLIENT_NVL3W 0xe6370#define TEGRA194_MEMORY_CLIENT_NVL4R 0xe7371#define TEGRA194_MEMORY_CLIENT_NVL4W 0xe8372/* DLA0ARDA1 read clients */373#define TEGRA194_MEMORY_CLIENT_DLA0RDA1 0xe9374/* DLA1ARDA1 read clients */375#define TEGRA194_MEMORY_CLIENT_DLA1RDA1 0xea376/* PVA0RDA1 read clients */377#define TEGRA194_MEMORY_CLIENT_PVA0RDA1 0xeb378/* PVA0RDB1 read clients */379#define TEGRA194_MEMORY_CLIENT_PVA0RDB1 0xec380/* PVA1RDA1 read clients */381#define TEGRA194_MEMORY_CLIENT_PVA1RDA1 0xed382/* PVA1RDB1 read clients */383#define TEGRA194_MEMORY_CLIENT_PVA1RDB1 0xee384/* PCIE5r1 read clients */385#define TEGRA194_MEMORY_CLIENT_PCIE5R1 0xef386#define TEGRA194_MEMORY_CLIENT_NVENCSRD1 0xf0387#define TEGRA194_MEMORY_CLIENT_NVENC1SRD1 0xf1388/* ISP read client for Crossbar A */389#define TEGRA194_MEMORY_CLIENT_ISPRA1 0xf2390/* PCIE0 read clients */391#define TEGRA194_MEMORY_CLIENT_PCIE0R1 0xf3392#define TEGRA194_MEMORY_CLIENT_NVL0RHP 0xf4393#define TEGRA194_MEMORY_CLIENT_NVL1RHP 0xf5394#define TEGRA194_MEMORY_CLIENT_NVL2RHP 0xf6395#define TEGRA194_MEMORY_CLIENT_NVL3RHP 0xf7396#define TEGRA194_MEMORY_CLIENT_NVL4RHP 0xf8397#define TEGRA194_MEMORY_CLIENT_NVDEC1SRD 0xf9398#define TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 0xfa399#define TEGRA194_MEMORY_CLIENT_NVDEC1SWR 0xfb400/* MSS internal memqual MIU5 read clients */401#define TEGRA194_MEMORY_CLIENT_MIU5R 0xfc402/* MSS internal memqual MIU5 write clients */403#define TEGRA194_MEMORY_CLIENT_MIU5W 0xfd404/* MSS internal memqual MIU6 read clients */405#define TEGRA194_MEMORY_CLIENT_MIU6R 0xfe406/* MSS internal memqual MIU6 write clients */407#define TEGRA194_MEMORY_CLIENT_MIU6W 0xff408409#endif410411412