Path: blob/master/include/dt-bindings/memory/tegra234-mc.h
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */1/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */23#ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H4#define DT_BINDINGS_MEMORY_TEGRA234_MC_H56/* special clients */7#define TEGRA234_SID_INVALID 0x008#define TEGRA234_SID_PASSTHROUGH 0x7f910/* ISO stream IDs */11#define TEGRA234_SID_ISO_NVDISPLAY 0x0112#define TEGRA234_SID_ISO_VI 0x0213#define TEGRA234_SID_ISO_VIFALC 0x0314#define TEGRA234_SID_ISO_VI2 0x0415#define TEGRA234_SID_ISO_VI2FALC 0x0516#define TEGRA234_SID_ISO_VI_VM2 0x0617#define TEGRA234_SID_ISO_VI2_VM2 0x071819/* NISO0 stream IDs */20#define TEGRA234_SID_AON 0x0121#define TEGRA234_SID_APE 0x0222#define TEGRA234_SID_HDA 0x0323#define TEGRA234_SID_GPCDMA 0x0424#define TEGRA234_SID_ETR 0x0525#define TEGRA234_SID_MGBE 0x0626#define TEGRA234_SID_NVDISPLAY 0x0727#define TEGRA234_SID_DCE 0x0828#define TEGRA234_SID_PSC 0x0929#define TEGRA234_SID_RCE 0x0a30#define TEGRA234_SID_SCE 0x0b31#define TEGRA234_SID_UFSHC 0x0c32#define TEGRA234_SID_APE_1 0x0d33#define TEGRA234_SID_GPCDMA_1 0x0e34#define TEGRA234_SID_GPCDMA_2 0x0f35#define TEGRA234_SID_GPCDMA_3 0x1036#define TEGRA234_SID_GPCDMA_4 0x1137#define TEGRA234_SID_PCIE0 0x1238#define TEGRA234_SID_PCIE4 0x1339#define TEGRA234_SID_PCIE5 0x1440#define TEGRA234_SID_PCIE6 0x1541#define TEGRA234_SID_RCE_VM2 0x1642#define TEGRA234_SID_RCE_SERVER 0x1743#define TEGRA234_SID_SMMU_TEST 0x1844#define TEGRA234_SID_UFS_1 0x1945#define TEGRA234_SID_UFS_2 0x1a46#define TEGRA234_SID_UFS_3 0x1b47#define TEGRA234_SID_UFS_4 0x1c48#define TEGRA234_SID_UFS_5 0x1d49#define TEGRA234_SID_UFS_6 0x1e50#define TEGRA234_SID_PCIE9 0x1f51#define TEGRA234_SID_VSE_GPCDMA_VM0 0x2052#define TEGRA234_SID_VSE_GPCDMA_VM1 0x2153#define TEGRA234_SID_VSE_GPCDMA_VM2 0x2254#define TEGRA234_SID_NVDLA1 0x2355#define TEGRA234_SID_NVENC 0x2456#define TEGRA234_SID_NVJPG1 0x2557#define TEGRA234_SID_OFA 0x2658#define TEGRA234_SID_MGBE_VF1 0x4959#define TEGRA234_SID_MGBE_VF2 0x4a60#define TEGRA234_SID_MGBE_VF3 0x4b61#define TEGRA234_SID_MGBE_VF4 0x4c62#define TEGRA234_SID_MGBE_VF5 0x4d63#define TEGRA234_SID_MGBE_VF6 0x4e64#define TEGRA234_SID_MGBE_VF7 0x4f65#define TEGRA234_SID_MGBE_VF8 0x5066#define TEGRA234_SID_MGBE_VF9 0x5167#define TEGRA234_SID_MGBE_VF10 0x5268#define TEGRA234_SID_MGBE_VF11 0x5369#define TEGRA234_SID_MGBE_VF12 0x5470#define TEGRA234_SID_MGBE_VF13 0x5571#define TEGRA234_SID_MGBE_VF14 0x5672#define TEGRA234_SID_MGBE_VF15 0x5773#define TEGRA234_SID_MGBE_VF16 0x5874#define TEGRA234_SID_MGBE_VF17 0x5975#define TEGRA234_SID_MGBE_VF18 0x5a76#define TEGRA234_SID_MGBE_VF19 0x5b77#define TEGRA234_SID_MGBE_VF20 0x5c78#define TEGRA234_SID_APE_2 0x5e79#define TEGRA234_SID_APE_3 0x5f80#define TEGRA234_SID_UFS_7 0x6081#define TEGRA234_SID_UFS_8 0x6182#define TEGRA234_SID_UFS_9 0x6283#define TEGRA234_SID_UFS_10 0x6384#define TEGRA234_SID_UFS_11 0x6485#define TEGRA234_SID_UFS_12 0x6586#define TEGRA234_SID_UFS_13 0x6687#define TEGRA234_SID_UFS_14 0x6788#define TEGRA234_SID_UFS_15 0x6889#define TEGRA234_SID_UFS_16 0x6990#define TEGRA234_SID_UFS_17 0x6a91#define TEGRA234_SID_UFS_18 0x6b92#define TEGRA234_SID_UFS_19 0x6c93#define TEGRA234_SID_UFS_20 0x6d94#define TEGRA234_SID_GPCDMA_5 0x6e95#define TEGRA234_SID_GPCDMA_6 0x6f96#define TEGRA234_SID_GPCDMA_7 0x7097#define TEGRA234_SID_GPCDMA_8 0x7198#define TEGRA234_SID_GPCDMA_9 0x7299100/* NISO1 stream IDs */101#define TEGRA234_SID_SDMMC1A 0x01102#define TEGRA234_SID_SDMMC4 0x02103#define TEGRA234_SID_EQOS 0x03104#define TEGRA234_SID_HWMP_PMA 0x04105#define TEGRA234_SID_PCIE1 0x05106#define TEGRA234_SID_PCIE2 0x06107#define TEGRA234_SID_PCIE3 0x07108#define TEGRA234_SID_PCIE7 0x08109#define TEGRA234_SID_PCIE8 0x09110#define TEGRA234_SID_PCIE10 0x0b111#define TEGRA234_SID_QSPI0 0x0c112#define TEGRA234_SID_QSPI1 0x0d113#define TEGRA234_SID_XUSB_HOST 0x0e114#define TEGRA234_SID_XUSB_DEV 0x0f115#define TEGRA234_SID_BPMP 0x10116#define TEGRA234_SID_FSI 0x11117#define TEGRA234_SID_PVA0_VM0 0x12118#define TEGRA234_SID_PVA0_VM1 0x13119#define TEGRA234_SID_PVA0_VM2 0x14120#define TEGRA234_SID_PVA0_VM3 0x15121#define TEGRA234_SID_PVA0_VM4 0x16122#define TEGRA234_SID_PVA0_VM5 0x17123#define TEGRA234_SID_PVA0_VM6 0x18124#define TEGRA234_SID_PVA0_VM7 0x19125#define TEGRA234_SID_XUSB_VF0 0x1a126#define TEGRA234_SID_XUSB_VF1 0x1b127#define TEGRA234_SID_XUSB_VF2 0x1c128#define TEGRA234_SID_XUSB_VF3 0x1d129#define TEGRA234_SID_EQOS_VF1 0x1e130#define TEGRA234_SID_EQOS_VF2 0x1f131#define TEGRA234_SID_EQOS_VF3 0x20132#define TEGRA234_SID_EQOS_VF4 0x21133#define TEGRA234_SID_ISP_VM2 0x22134#define TEGRA234_SID_HOST1X 0x27135#define TEGRA234_SID_ISP 0x28136#define TEGRA234_SID_NVDEC 0x29137#define TEGRA234_SID_NVJPG 0x2a138#define TEGRA234_SID_NVDLA0 0x2b139#define TEGRA234_SID_PVA0 0x2c140#define TEGRA234_SID_SES_SE0 0x2d141#define TEGRA234_SID_SES_SE1 0x2e142#define TEGRA234_SID_SES_SE2 0x2f143#define TEGRA234_SID_SEU1_SE0 0x30144#define TEGRA234_SID_SEU1_SE1 0x31145#define TEGRA234_SID_SEU1_SE2 0x32146#define TEGRA234_SID_TSEC 0x33147#define TEGRA234_SID_VIC 0x34148#define TEGRA234_SID_HC_VM0 0x3d149#define TEGRA234_SID_HC_VM1 0x3e150#define TEGRA234_SID_HC_VM2 0x3f151#define TEGRA234_SID_HC_VM3 0x40152#define TEGRA234_SID_HC_VM4 0x41153#define TEGRA234_SID_HC_VM5 0x42154#define TEGRA234_SID_HC_VM6 0x43155#define TEGRA234_SID_HC_VM7 0x44156#define TEGRA234_SID_SE_VM0 0x45157#define TEGRA234_SID_SE_VM1 0x46158#define TEGRA234_SID_SE_VM2 0x47159#define TEGRA234_SID_ISPFALC 0x48160#define TEGRA234_SID_NISO1_SMMU_TEST 0x49161#define TEGRA234_SID_TSEC_VM0 0x4a162163/* Shared stream IDs */164#define TEGRA234_SID_HOST1X_CTX0 0x35165#define TEGRA234_SID_HOST1X_CTX1 0x36166#define TEGRA234_SID_HOST1X_CTX2 0x37167#define TEGRA234_SID_HOST1X_CTX3 0x38168#define TEGRA234_SID_HOST1X_CTX4 0x39169#define TEGRA234_SID_HOST1X_CTX5 0x3a170#define TEGRA234_SID_HOST1X_CTX6 0x3b171#define TEGRA234_SID_HOST1X_CTX7 0x3c172173/*174* memory client IDs175*/176177/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */178#define TEGRA234_MEMORY_CLIENT_PTCR 0x00179/* MSS internal memqual MIU7 read clients */180#define TEGRA234_MEMORY_CLIENT_MIU7R 0x01181/* MSS internal memqual MIU7 write clients */182#define TEGRA234_MEMORY_CLIENT_MIU7W 0x02183/* MSS internal memqual MIU8 read clients */184#define TEGRA234_MEMORY_CLIENT_MIU8R 0x03185/* MSS internal memqual MIU8 write clients */186#define TEGRA234_MEMORY_CLIENT_MIU8W 0x04187/* MSS internal memqual MIU9 read clients */188#define TEGRA234_MEMORY_CLIENT_MIU9R 0x05189/* MSS internal memqual MIU9 write clients */190#define TEGRA234_MEMORY_CLIENT_MIU9W 0x06191/* MSS internal memqual MIU10 read clients */192#define TEGRA234_MEMORY_CLIENT_MIU10R 0x07193/* MSS internal memqual MIU10 write clients */194#define TEGRA234_MEMORY_CLIENT_MIU10W 0x08195/* MSS internal memqual MIU11 read clients */196#define TEGRA234_MEMORY_CLIENT_MIU11R 0x09197/* MSS internal memqual MIU11 write clients */198#define TEGRA234_MEMORY_CLIENT_MIU11W 0x0a199/* MSS internal memqual MIU12 read clients */200#define TEGRA234_MEMORY_CLIENT_MIU12R 0x0b201/* MSS internal memqual MIU12 write clients */202#define TEGRA234_MEMORY_CLIENT_MIU12W 0x0c203/* MSS internal memqual MIU13 read clients */204#define TEGRA234_MEMORY_CLIENT_MIU13R 0x0d205/* MSS internal memqual MIU13 write clients */206#define TEGRA234_MEMORY_CLIENT_MIU13W 0x0e207#define TEGRA234_MEMORY_CLIENT_NVL5RHP 0x13208#define TEGRA234_MEMORY_CLIENT_NVL5R 0x14209/* High-definition audio (HDA) read clients */210#define TEGRA234_MEMORY_CLIENT_HDAR 0x15211/* Host channel data read clients */212#define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16213#define TEGRA234_MEMORY_CLIENT_NVL5W 0x17214#define TEGRA234_MEMORY_CLIENT_NVL6RHP 0x18215#define TEGRA234_MEMORY_CLIENT_NVL6R 0x19216#define TEGRA234_MEMORY_CLIENT_NVL6W 0x1a217#define TEGRA234_MEMORY_CLIENT_NVL7RHP 0x1b218#define TEGRA234_MEMORY_CLIENT_NVENCSRD 0x1c219#define TEGRA234_MEMORY_CLIENT_NVL7R 0x1d220#define TEGRA234_MEMORY_CLIENT_NVL7W 0x1e221#define TEGRA234_MEMORY_CLIENT_NVL8RHP 0x20222#define TEGRA234_MEMORY_CLIENT_NVL8R 0x21223#define TEGRA234_MEMORY_CLIENT_NVL8W 0x22224#define TEGRA234_MEMORY_CLIENT_NVL9RHP 0x23225#define TEGRA234_MEMORY_CLIENT_NVL9R 0x24226#define TEGRA234_MEMORY_CLIENT_NVL9W 0x25227/* PCIE6 read clients */228#define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28229/* PCIE6 write clients */230#define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29231/* PCIE7 read clients */232#define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a233#define TEGRA234_MEMORY_CLIENT_NVENCSWR 0x2b234/* DLA0ARDB read clients */235#define TEGRA234_MEMORY_CLIENT_DLA0RDB 0x2c236/* DLA0ARDB1 read clients */237#define TEGRA234_MEMORY_CLIENT_DLA0RDB1 0x2d238/* DLA0 writes */239#define TEGRA234_MEMORY_CLIENT_DLA0WRB 0x2e240/* DLA1ARDB read clients */241#define TEGRA234_MEMORY_CLIENT_DLA1RDB 0x2f242/* PCIE7 write clients */243#define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30244/* PCIE8 read clients */245#define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32246/* High-definition audio (HDA) write clients */247#define TEGRA234_MEMORY_CLIENT_HDAW 0x35248/* Writes from Cortex-A9 4 CPU cores via the L2 cache */249#define TEGRA234_MEMORY_CLIENT_MPCOREW 0x39250/* OFAA client */251#define TEGRA234_MEMORY_CLIENT_OFAR1 0x3a252/* PCIE8 write clients */253#define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b254/* PCIE9 read clients */255#define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c256/* PCIE6r1 read clients */257#define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d258/* PCIE9 write clients */259#define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e260/* PCIE10 read clients */261#define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f262/* PCIE10 write clients */263#define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40264/* ISP read client for Crossbar A */265#define TEGRA234_MEMORY_CLIENT_ISPRA 0x44266/* ISP read client 1 for Crossbar A */267#define TEGRA234_MEMORY_CLIENT_ISPFALR 0x45268/* ISP Write client for Crossbar A */269#define TEGRA234_MEMORY_CLIENT_ISPWA 0x46270/* ISP Write client Crossbar B */271#define TEGRA234_MEMORY_CLIENT_ISPWB 0x47272/* PCIE10r1 read clients */273#define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48274/* PCIE7r1 read clients */275#define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49276/* XUSB_HOST read clients */277#define TEGRA234_MEMORY_CLIENT_XUSB_HOSTR 0x4a278/* XUSB_HOST write clients */279#define TEGRA234_MEMORY_CLIENT_XUSB_HOSTW 0x4b280/* XUSB read clients */281#define TEGRA234_MEMORY_CLIENT_XUSB_DEVR 0x4c282/* XUSB_DEV write clients */283#define TEGRA234_MEMORY_CLIENT_XUSB_DEVW 0x4d284/* TSEC Memory Return Data Client Description */285#define TEGRA234_MEMORY_CLIENT_TSECSRD 0x54286/* TSEC Memory Write Client Description */287#define TEGRA234_MEMORY_CLIENT_TSECSWR 0x55288/* XSPI writes */289#define TEGRA234_MEMORY_CLIENT_XSPI1W 0x56290/* MGBE0 read client */291#define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58292/* MGBEB read client */293#define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59294/* MGBEC read client */295#define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a296/* MGBED read client */297#define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b298/* MGBE0 write client */299#define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c300/* OFAA client */301#define TEGRA234_MEMORY_CLIENT_OFAR 0x5d302/* OFAA writes */303#define TEGRA234_MEMORY_CLIENT_OFAW 0x5e304/* MGBEB write client */305#define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f306/* sdmmca memory read client */307#define TEGRA234_MEMORY_CLIENT_SDMMCRA 0x60308/* MGBEC write client */309#define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61310/* sdmmcd memory read client */311#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63312/* sdmmca memory write client */313#define TEGRA234_MEMORY_CLIENT_SDMMCWA 0x64314/* MGBED write client */315#define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65316/* sdmmcd memory write client */317#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67318/* SE Memory Return Data Client Description */319#define TEGRA234_MEMORY_CLIENT_SEU1RD 0x68320/* SE Memory Write Client Description */321#define TEGRA234_MEMORY_CLIENT_SUE1WR 0x69322#define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c323#define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d324/* DLA1ARDB1 read clients */325#define TEGRA234_MEMORY_CLIENT_DLA1RDB1 0x6e326/* DLA1 writes */327#define TEGRA234_MEMORY_CLIENT_DLA1WRB 0x6f328/* VI FLACON read clients */329#define TEGRA234_MEMORY_CLIENT_VI2FALR 0x71330/* VI Write client */331#define TEGRA234_MEMORY_CLIENT_VI2W 0x70332/* VI Write client */333#define TEGRA234_MEMORY_CLIENT_VIW 0x72334/* NISO display read client */335#define TEGRA234_MEMORY_CLIENT_NVDISPNISOR 0x73336/* NVDISPNISO writes */337#define TEGRA234_MEMORY_CLIENT_NVDISPNISOW 0x74338/* XSPI client */339#define TEGRA234_MEMORY_CLIENT_XSPI0R 0x75340/* XSPI writes */341#define TEGRA234_MEMORY_CLIENT_XSPI0W 0x76342/* XSPI client */343#define TEGRA234_MEMORY_CLIENT_XSPI1R 0x77344#define TEGRA234_MEMORY_CLIENT_NVDECSRD 0x78345#define TEGRA234_MEMORY_CLIENT_NVDECSWR 0x79346/* Audio Processing (APE) engine read clients */347#define TEGRA234_MEMORY_CLIENT_APER 0x7a348/* Audio Processing (APE) engine write clients */349#define TEGRA234_MEMORY_CLIENT_APEW 0x7b350/* VI2FAL writes */351#define TEGRA234_MEMORY_CLIENT_VI2FALW 0x7c352#define TEGRA234_MEMORY_CLIENT_NVJPGSRD 0x7e353#define TEGRA234_MEMORY_CLIENT_NVJPGSWR 0x7f354/* SE Memory Return Data Client Description */355#define TEGRA234_MEMORY_CLIENT_SESRD 0x80356/* SE Memory Write Client Description */357#define TEGRA234_MEMORY_CLIENT_SESWR 0x81358/* AXI AP and DFD-AUX0/1 read clients Both share the same interface on the on MSS */359#define TEGRA234_MEMORY_CLIENT_AXIAPR 0x82360/* AXI AP and DFD-AUX0/1 write clients Both sahre the same interface on MSS */361#define TEGRA234_MEMORY_CLIENT_AXIAPW 0x83362/* ETR read clients */363#define TEGRA234_MEMORY_CLIENT_ETRR 0x84364/* ETR write clients */365#define TEGRA234_MEMORY_CLIENT_ETRW 0x85366/* AXI Switch read client */367#define TEGRA234_MEMORY_CLIENT_AXISR 0x8c368/* AXI Switch write client */369#define TEGRA234_MEMORY_CLIENT_AXISW 0x8d370/* EQOS read client */371#define TEGRA234_MEMORY_CLIENT_EQOSR 0x8e372/* EQOS write client */373#define TEGRA234_MEMORY_CLIENT_EQOSW 0x8f374/* UFSHC read client */375#define TEGRA234_MEMORY_CLIENT_UFSHCR 0x90376/* UFSHC write client */377#define TEGRA234_MEMORY_CLIENT_UFSHCW 0x91378/* NVDISPLAY read client */379#define TEGRA234_MEMORY_CLIENT_NVDISPLAYR 0x92380/* BPMP read client */381#define TEGRA234_MEMORY_CLIENT_BPMPR 0x93382/* BPMP write client */383#define TEGRA234_MEMORY_CLIENT_BPMPW 0x94384/* BPMPDMA read client */385#define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95386/* BPMPDMA write client */387#define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96388/* AON read client */389#define TEGRA234_MEMORY_CLIENT_AONR 0x97390/* AON write client */391#define TEGRA234_MEMORY_CLIENT_AONW 0x98392/* AONDMA read client */393#define TEGRA234_MEMORY_CLIENT_AONDMAR 0x99394/* AONDMA write client */395#define TEGRA234_MEMORY_CLIENT_AONDMAW 0x9a396/* SCE read client */397#define TEGRA234_MEMORY_CLIENT_SCER 0x9b398/* SCE write client */399#define TEGRA234_MEMORY_CLIENT_SCEW 0x9c400/* SCEDMA read client */401#define TEGRA234_MEMORY_CLIENT_SCEDMAR 0x9d402/* SCEDMA write client */403#define TEGRA234_MEMORY_CLIENT_SCEDMAW 0x9e404/* APEDMA read client */405#define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f406/* APEDMA write client */407#define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0408/* NVDISPLAY read client instance 2 */409#define TEGRA234_MEMORY_CLIENT_NVDISPLAYR1 0xa1410#define TEGRA234_MEMORY_CLIENT_VICSRD1 0xa2411/* MSS internal memqual MIU0 read clients */412#define TEGRA234_MEMORY_CLIENT_MIU0R 0xa6413/* MSS internal memqual MIU0 write clients */414#define TEGRA234_MEMORY_CLIENT_MIU0W 0xa7415/* MSS internal memqual MIU1 read clients */416#define TEGRA234_MEMORY_CLIENT_MIU1R 0xa8417/* MSS internal memqual MIU1 write clients */418#define TEGRA234_MEMORY_CLIENT_MIU1W 0xa9419/* MSS internal memqual MIU2 read clients */420#define TEGRA234_MEMORY_CLIENT_MIU2R 0xae421/* MSS internal memqual MIU2 write clients */422#define TEGRA234_MEMORY_CLIENT_MIU2W 0xaf423/* MSS internal memqual MIU3 read clients */424#define TEGRA234_MEMORY_CLIENT_MIU3R 0xb0425/* MSS internal memqual MIU3 write clients */426#define TEGRA234_MEMORY_CLIENT_MIU3W 0xb1427/* MSS internal memqual MIU4 read clients */428#define TEGRA234_MEMORY_CLIENT_MIU4R 0xb2429/* MSS internal memqual MIU4 write clients */430#define TEGRA234_MEMORY_CLIENT_MIU4W 0xb3431#define TEGRA234_MEMORY_CLIENT_DPMUR 0xb4432#define TEGRA234_MEMORY_CLIENT_DPMUW 0xb5433#define TEGRA234_MEMORY_CLIENT_NVL0R 0xb6434#define TEGRA234_MEMORY_CLIENT_NVL0W 0xb7435#define TEGRA234_MEMORY_CLIENT_NVL1R 0xb8436#define TEGRA234_MEMORY_CLIENT_NVL1W 0xb9437#define TEGRA234_MEMORY_CLIENT_NVL2R 0xba438#define TEGRA234_MEMORY_CLIENT_NVL2W 0xbb439/* VI FLACON read clients */440#define TEGRA234_MEMORY_CLIENT_VIFALR 0xbc441/* VIFAL write clients */442#define TEGRA234_MEMORY_CLIENT_VIFALW 0xbd443/* DLA0ARDA read clients */444#define TEGRA234_MEMORY_CLIENT_DLA0RDA 0xbe445/* DLA0 Falcon read clients */446#define TEGRA234_MEMORY_CLIENT_DLA0FALRDB 0xbf447/* DLA0 write clients */448#define TEGRA234_MEMORY_CLIENT_DLA0WRA 0xc0449/* DLA0 write clients */450#define TEGRA234_MEMORY_CLIENT_DLA0FALWRB 0xc1451/* DLA1ARDA read clients */452#define TEGRA234_MEMORY_CLIENT_DLA1RDA 0xc2453/* DLA1 Falcon read clients */454#define TEGRA234_MEMORY_CLIENT_DLA1FALRDB 0xc3455/* DLA1 write clients */456#define TEGRA234_MEMORY_CLIENT_DLA1WRA 0xc4457/* DLA1 write clients */458#define TEGRA234_MEMORY_CLIENT_DLA1FALWRB 0xc5459/* PVA0RDA read clients */460#define TEGRA234_MEMORY_CLIENT_PVA0RDA 0xc6461/* PVA0RDB read clients */462#define TEGRA234_MEMORY_CLIENT_PVA0RDB 0xc7463/* PVA0RDC read clients */464#define TEGRA234_MEMORY_CLIENT_PVA0RDC 0xc8465/* PVA0WRA write clients */466#define TEGRA234_MEMORY_CLIENT_PVA0WRA 0xc9467/* PVA0WRB write clients */468#define TEGRA234_MEMORY_CLIENT_PVA0WRB 0xca469/* PVA0WRC write clients */470#define TEGRA234_MEMORY_CLIENT_PVA0WRC 0xcb471/* RCE read client */472#define TEGRA234_MEMORY_CLIENT_RCER 0xd2473/* RCE write client */474#define TEGRA234_MEMORY_CLIENT_RCEW 0xd3475/* RCEDMA read client */476#define TEGRA234_MEMORY_CLIENT_RCEDMAR 0xd4477/* RCEDMA write client */478#define TEGRA234_MEMORY_CLIENT_RCEDMAW 0xd5479/* PCIE0 read clients */480#define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8481/* PCIE0 write clients */482#define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9483/* PCIE1 read clients */484#define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda485/* PCIE1 write clients */486#define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb487/* PCIE2 read clients */488#define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc489/* PCIE2 write clients */490#define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd491/* PCIE3 read clients */492#define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde493/* PCIE3 write clients */494#define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf495/* PCIE4 read clients */496#define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0497/* PCIE4 write clients */498#define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1499/* PCIE5 read clients */500#define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2501/* PCIE5 write clients */502#define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3503/* ISP read client 1 for Crossbar A */504#define TEGRA234_MEMORY_CLIENT_ISPFALW 0xe4505#define TEGRA234_MEMORY_CLIENT_NVL3R 0xe5506#define TEGRA234_MEMORY_CLIENT_NVL3W 0xe6507#define TEGRA234_MEMORY_CLIENT_NVL4R 0xe7508#define TEGRA234_MEMORY_CLIENT_NVL4W 0xe8509/* DLA0ARDA1 read clients */510#define TEGRA234_MEMORY_CLIENT_DLA0RDA1 0xe9511/* DLA1ARDA1 read clients */512#define TEGRA234_MEMORY_CLIENT_DLA1RDA1 0xea513/* PVA0RDA1 read clients */514#define TEGRA234_MEMORY_CLIENT_PVA0RDA1 0xeb515/* PVA0RDB1 read clients */516#define TEGRA234_MEMORY_CLIENT_PVA0RDB1 0xec517/* PCIE5r1 read clients */518#define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef519#define TEGRA234_MEMORY_CLIENT_NVENCSRD1 0xf0520/* ISP read client for Crossbar A */521#define TEGRA234_MEMORY_CLIENT_ISPRA1 0xf2522#define TEGRA234_MEMORY_CLIENT_NVL0RHP 0xf4523#define TEGRA234_MEMORY_CLIENT_NVL1RHP 0xf5524#define TEGRA234_MEMORY_CLIENT_NVL2RHP 0xf6525#define TEGRA234_MEMORY_CLIENT_NVL3RHP 0xf7526#define TEGRA234_MEMORY_CLIENT_NVL4RHP 0xf8527/* MSS internal memqual MIU5 read clients */528#define TEGRA234_MEMORY_CLIENT_MIU5R 0xfc529/* MSS internal memqual MIU5 write clients */530#define TEGRA234_MEMORY_CLIENT_MIU5W 0xfd531/* MSS internal memqual MIU6 read clients */532#define TEGRA234_MEMORY_CLIENT_MIU6R 0xfe533/* MSS internal memqual MIU6 write clients */534#define TEGRA234_MEMORY_CLIENT_MIU6W 0xff535#define TEGRA234_MEMORY_CLIENT_NVJPG1SRD 0x123536#define TEGRA234_MEMORY_CLIENT_NVJPG1SWR 0x124537538/* ICC ID's for dummy MC clients used to represent CPU Clusters */539#define TEGRA_ICC_MC_CPU_CLUSTER0 1003540#define TEGRA_ICC_MC_CPU_CLUSTER1 1004541#define TEGRA_ICC_MC_CPU_CLUSTER2 1005542543#endif544545546