Path: blob/master/include/dt-bindings/power/mediatek,mt8189-power.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */1/*2* Copyright (c) 2025 MediaTek Inc.3* Author: Qiqi Wang <[email protected]>4*/56#ifndef _DT_BINDINGS_POWER_MT8189_POWER_H7#define _DT_BINDINGS_POWER_MT8189_POWER_H89/* SPM */10#define MT8189_POWER_DOMAIN_CONN 011#define MT8189_POWER_DOMAIN_AUDIO 112#define MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT 213#define MT8189_POWER_DOMAIN_ADSP_INFRA 314#define MT8189_POWER_DOMAIN_ADSP_AO 415#define MT8189_POWER_DOMAIN_MM_INFRA 516#define MT8189_POWER_DOMAIN_ISP_IMG1 617#define MT8189_POWER_DOMAIN_ISP_IMG2 718#define MT8189_POWER_DOMAIN_ISP_IPE 819#define MT8189_POWER_DOMAIN_VDE0 920#define MT8189_POWER_DOMAIN_VEN0 1021#define MT8189_POWER_DOMAIN_CAM_MAIN 1122#define MT8189_POWER_DOMAIN_CAM_SUBA 1223#define MT8189_POWER_DOMAIN_CAM_SUBB 1324#define MT8189_POWER_DOMAIN_MDP0 1425#define MT8189_POWER_DOMAIN_DISP 1526#define MT8189_POWER_DOMAIN_DP_TX 1627#define MT8189_POWER_DOMAIN_CSI_RX 1728#define MT8189_POWER_DOMAIN_SSUSB 1829#define MT8189_POWER_DOMAIN_MFG0 1930#define MT8189_POWER_DOMAIN_MFG1 2031#define MT8189_POWER_DOMAIN_MFG2 2132#define MT8189_POWER_DOMAIN_MFG3 2233#define MT8189_POWER_DOMAIN_EDP_TX_DORMANT 2334#define MT8189_POWER_DOMAIN_PCIE 2435#define MT8189_POWER_DOMAIN_PCIE_PHY 253637#endif /* _DT_BINDINGS_POWER_MT8189_POWER_H */383940