Path: blob/master/include/dt-bindings/power/mt8195-power.h
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */1/*2* Copyright (c) 2021 MediaTek Inc.3* Author: Chun-Jie Chen <[email protected]>4*/56#ifndef _DT_BINDINGS_POWER_MT8195_POWER_H7#define _DT_BINDINGS_POWER_MT8195_POWER_H89#define MT8195_POWER_DOMAIN_PCIE_MAC_P0 010#define MT8195_POWER_DOMAIN_PCIE_MAC_P1 111#define MT8195_POWER_DOMAIN_PCIE_PHY 212#define MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY 313#define MT8195_POWER_DOMAIN_CSI_RX_TOP 414#define MT8195_POWER_DOMAIN_ETHER 515#define MT8195_POWER_DOMAIN_ADSP 616#define MT8195_POWER_DOMAIN_AUDIO 717#define MT8195_POWER_DOMAIN_MFG0 818#define MT8195_POWER_DOMAIN_MFG1 919#define MT8195_POWER_DOMAIN_MFG2 1020#define MT8195_POWER_DOMAIN_MFG3 1121#define MT8195_POWER_DOMAIN_MFG4 1222#define MT8195_POWER_DOMAIN_MFG5 1323#define MT8195_POWER_DOMAIN_MFG6 1424#define MT8195_POWER_DOMAIN_VPPSYS0 1525#define MT8195_POWER_DOMAIN_VDOSYS0 1626#define MT8195_POWER_DOMAIN_VPPSYS1 1727#define MT8195_POWER_DOMAIN_VDOSYS1 1828#define MT8195_POWER_DOMAIN_DP_TX 1929#define MT8195_POWER_DOMAIN_EPD_TX 2030#define MT8195_POWER_DOMAIN_HDMI_TX 2131#define MT8195_POWER_DOMAIN_WPESYS 2232#define MT8195_POWER_DOMAIN_VDEC0 2333#define MT8195_POWER_DOMAIN_VDEC1 2434#define MT8195_POWER_DOMAIN_VDEC2 2535#define MT8195_POWER_DOMAIN_VENC 2636#define MT8195_POWER_DOMAIN_VENC_CORE1 2737#define MT8195_POWER_DOMAIN_IMG 2838#define MT8195_POWER_DOMAIN_DIP 2939#define MT8195_POWER_DOMAIN_IPE 3040#define MT8195_POWER_DOMAIN_CAM 3141#define MT8195_POWER_DOMAIN_CAM_RAWA 3242#define MT8195_POWER_DOMAIN_CAM_RAWB 3343#define MT8195_POWER_DOMAIN_CAM_MRAW 344445#endif /* _DT_BINDINGS_POWER_MT8195_POWER_H */464748