Path: blob/master/include/dt-bindings/reset/altr,rst-mgr-a10.h
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/* SPDX-License-Identifier: GPL-2.0-only */1/*2* Copyright (c) 2014, Steffen Trumtrar <[email protected]>3*/45#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H6#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H78/* MPUMODRST */9#define CPU0_RESET 010#define CPU1_RESET 111#define WDS_RESET 212#define SCUPER_RESET 31314/* PER0MODRST */15#define EMAC0_RESET 3216#define EMAC1_RESET 3317#define EMAC2_RESET 3418#define USB0_RESET 3519#define USB1_RESET 3620#define NAND_RESET 3721#define QSPI_RESET 3822#define SDMMC_RESET 3923#define EMAC0_OCP_RESET 4024#define EMAC1_OCP_RESET 4125#define EMAC2_OCP_RESET 4226#define USB0_OCP_RESET 4327#define USB1_OCP_RESET 4428#define NAND_OCP_RESET 4529#define QSPI_OCP_RESET 4630#define SDMMC_OCP_RESET 4731#define DMA_RESET 4832#define SPIM0_RESET 4933#define SPIM1_RESET 5034#define SPIS0_RESET 5135#define SPIS1_RESET 5236#define DMA_OCP_RESET 5337#define EMAC_PTP_RESET 5438/* 55 is empty*/39#define DMAIF0_RESET 5640#define DMAIF1_RESET 5741#define DMAIF2_RESET 5842#define DMAIF3_RESET 5943#define DMAIF4_RESET 6044#define DMAIF5_RESET 6145#define DMAIF6_RESET 6246#define DMAIF7_RESET 634748/* PER1MODRST */49#define L4WD0_RESET 6450#define L4WD1_RESET 6551#define L4SYSTIMER0_RESET 6652#define L4SYSTIMER1_RESET 6753#define SPTIMER0_RESET 6854#define SPTIMER1_RESET 6955/* 70-71 is reserved */56#define I2C0_RESET 7257#define I2C1_RESET 7358#define I2C2_RESET 7459#define I2C3_RESET 7560#define I2C4_RESET 7661/* 77-79 is reserved */62#define UART0_RESET 8063#define UART1_RESET 8164/* 82-87 is reserved */65#define GPIO0_RESET 8866#define GPIO1_RESET 8967#define GPIO2_RESET 906869/* BRGMODRST */70#define HPS2FPGA_RESET 9671#define LWHPS2FPGA_RESET 9772#define FPGA2HPS_RESET 9873#define F2SSDRAM0_RESET 9974#define F2SSDRAM1_RESET 10075#define F2SSDRAM2_RESET 10176#define DDRSCH_RESET 1027778/* SYSMODRST*/79#define ROM_RESET 12880#define OCRAM_RESET 12981/* 130 is reserved */82#define FPGAMGR_RESET 13183#define S2F_RESET 13284#define SYSDBG_RESET 13385#define OCRAM_OCP_RESET 1348687/* COLDMODRST */88#define CLKMGRCOLD_RESET 16089/* 161-162 is reserved */90#define S2FCOLD_RESET 16391#define TIMESTAMPCOLD_RESET 16492#define TAPCOLD_RESET 16593#define HMCCOLD_RESET 16694#define IOMGRCOLD_RESET 1679596/* NRSTMODRST */97#define NRSTPINOE_RESET 1929899/* DBGMODRST */100#define DBG_RESET 224101#endif102103104