CoCalc -- altr,rst-mgr-s10.h

GitHub Repository: torvalds/linux
Path: blob/master/include/dt-bindings/reset/altr,rst-mgr-s10.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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 * Copyright (C) 2016 Intel Corporation. All rights reserved
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 * Copyright (C) 2016 Altera Corporation. All rights reserved
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 *
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 * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h"
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 */
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#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
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#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
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/* MPUMODRST */
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#define CPU0_RESET		0
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#define CPU1_RESET		1
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#define CPU2_RESET		2
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#define CPU3_RESET		3
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/* PER0MODRST */
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#define EMAC0_RESET		32
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#define EMAC1_RESET		33
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#define EMAC2_RESET		34
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#define USB0_RESET		35
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#define USB1_RESET		36
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#define NAND_RESET		37
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/* 38 is empty */
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#define SDMMC_RESET		39
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#define EMAC0_OCP_RESET		40
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#define EMAC1_OCP_RESET		41
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#define EMAC2_OCP_RESET		42
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#define USB0_OCP_RESET		43
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#define USB1_OCP_RESET		44
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#define NAND_OCP_RESET		45
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/* 46 is empty */
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#define SDMMC_OCP_RESET		47
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#define DMA_RESET		48
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#define SPIM0_RESET		49
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#define SPIM1_RESET		50
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#define SPIS0_RESET		51
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#define SPIS1_RESET		52
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#define DMA_OCP_RESET		53
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#define EMAC_PTP_RESET		54
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/* 55 is empty*/
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#define DMAIF0_RESET		56
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#define DMAIF1_RESET		57
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#define DMAIF2_RESET		58
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#define DMAIF3_RESET		59
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#define DMAIF4_RESET		60
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#define DMAIF5_RESET		61
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#define DMAIF6_RESET		62
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#define DMAIF7_RESET		63
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/* PER1MODRST */
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#define WATCHDOG0_RESET		64
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#define WATCHDOG1_RESET		65
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#define WATCHDOG2_RESET		66
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#define WATCHDOG3_RESET		67
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#define L4SYSTIMER0_RESET	68
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#define L4SYSTIMER1_RESET	69
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#define SPTIMER0_RESET		70
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#define SPTIMER1_RESET		71
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#define I2C0_RESET		72
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#define I2C1_RESET		73
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#define I2C2_RESET		74
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#define I2C3_RESET		75
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#define I2C4_RESET		76
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#define I3C0_RESET		77
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#define I3C1_RESET		78
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/* 79 is empty */
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#define UART0_RESET		80
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#define UART1_RESET		81
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/* 82-87 is empty */
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#define GPIO0_RESET		88
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#define GPIO1_RESET		89
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#define WATCHDOG4_RESET		90
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/* BRGMODRST */
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#define SOC2FPGA_RESET		96
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#define LWHPS2FPGA_RESET	97
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#define FPGA2SOC_RESET		98
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#define F2SSDRAM0_RESET		99
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#define F2SSDRAM1_RESET		100
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#define F2SSDRAM2_RESET		101
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#define DDRSCH_RESET		102
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/* COLDMODRST */
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#define CPUPO0_RESET		160
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#define CPUPO1_RESET		161
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#define CPUPO2_RESET		162
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#define CPUPO3_RESET		163
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/* 164-167 is empty */
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#define L2_RESET		168
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/* DBGMODRST */
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#define DBG_RESET		224
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#define CSDAP_RESET		225
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/* TAPMODRST */
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#define TAP_RESET		256
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#endif
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