CoCalc -- amlogic,meson8b-reset.h

GitHub Repository: torvalds/linux
Path: blob/master/include/dt-bindings/reset/amlogic,meson8b-reset.h
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/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/*
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 * Copyright (c) 2016 BayLibre, SAS.
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 * Author: Neil Armstrong <[email protected]>
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 */
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#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H
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#define _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H
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/*	RESET0					*/
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#define RESET_HIU			0
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#define RESET_VLD			1
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#define RESET_IQIDCT			2
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#define RESET_MC			3
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/*					8	*/
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#define RESET_VIU			5
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#define RESET_AIU			6
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#define RESET_MCPU			7
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#define RESET_CCPU			8
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#define RESET_PMUX			9
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#define RESET_VENC			10
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#define RESET_ASSIST			11
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#define RESET_AFIFO2			12
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#define RESET_MDEC			13
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#define RESET_VLD_PART			14
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#define RESET_VIFIFO			15
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/*					16-31	*/
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/*	RESET1					*/
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/*					32	*/
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#define RESET_DEMUX			33
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#define RESET_USB_OTG			34
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#define RESET_DDR			35
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#define RESET_VDAC_1			36
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#define RESET_BT656			37
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#define RESET_AHB_SRAM			38
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#define RESET_AHB_BRIDGE		39
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#define RESET_PARSER			40
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#define RESET_BLKMV			41
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#define RESET_ISA			42
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#define RESET_ETHERNET			43
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#define RESET_ABUF			44
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#define RESET_AHB_DATA			45
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#define RESET_AHB_CNTL			46
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#define RESET_ROM_BOOT			47
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/*					48-63	*/
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/*	RESET2					*/
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#define RESET_VD_RMEM			64
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#define RESET_AUDIN			65
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#define RESET_DBLK			66
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#define RESET_PIC_DC			67
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#define RESET_PSC			68
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#define RESET_NAND			69
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#define RESET_GE2D			70
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#define RESET_PARSER_REG		71
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#define RESET_PARSER_FETCH		72
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#define RESET_PARSER_CTL		73
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#define RESET_PARSER_TOP		74
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#define RESET_HDMI_APB			75
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#define RESET_AUDIO_APB			76
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#define RESET_MEDIA_CPU			77
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#define RESET_MALI			78
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#define RESET_HDMI_SYSTEM_RESET		79
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/*					80-95	*/
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/*	RESET3					*/
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#define RESET_RING_OSCILLATOR		96
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#define RESET_SYS_CPU_0			97
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#define RESET_EFUSE			98
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#define RESET_SYS_CPU_BVCI		99
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#define RESET_AIFIFO			100
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#define RESET_AUDIO_PLL_MODULATOR	101
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#define RESET_AHB_BRIDGE_CNTL		102
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#define RESET_SYS_CPU_1			103
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#define RESET_AUDIO_DAC			104
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#define RESET_DEMUX_TOP			105
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#define RESET_DEMUX_DES			106
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#define RESET_DEMUX_S2P_0		107
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#define RESET_DEMUX_S2P_1		108
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#define RESET_DEMUX_RESET_0		109
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#define RESET_DEMUX_RESET_1		110
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#define RESET_DEMUX_RESET_2		111
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/*					112-127	*/
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/*	RESET4					*/
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#define RESET_PL310			128
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#define RESET_A5_APB			129
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#define RESET_A5_AXI			130
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#define RESET_A5			131
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#define RESET_DVIN			132
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#define RESET_RDMA			133
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#define RESET_VENCI			134
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#define RESET_VENCP			135
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#define RESET_VENCT			136
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#define RESET_VDAC_4			137
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#define RESET_RTC			138
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#define RESET_A5_DEBUG			139
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#define RESET_VDI6			140
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#define RESET_VENCL			141
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/*					142-159	*/
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/*	RESET5					*/
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#define RESET_DDR_PLL			160
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#define RESET_MISC_PLL			161
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#define RESET_SYS_PLL			162
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#define RESET_HPLL_PLL			163
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#define RESET_AUDIO_PLL			164
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#define RESET_VID2_PLL			165
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/*					166-191	*/
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/*	RESET6					*/
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#define RESET_PERIPHS_GENERAL		192
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#define RESET_PERIPHS_IR_REMOTE		193
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#define RESET_PERIPHS_SMART_CARD	194
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#define RESET_PERIPHS_SAR_ADC		195
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#define RESET_PERIPHS_I2C_MASTER_0	196
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#define RESET_PERIPHS_I2C_MASTER_1	197
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#define RESET_PERIPHS_I2C_SLAVE		198
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#define RESET_PERIPHS_STREAM_INTERFACE	199
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#define RESET_PERIPHS_SDIO		200
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#define RESET_PERIPHS_UART_0		201
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#define RESET_PERIPHS_UART_1		202
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#define RESET_PERIPHS_ASYNC_0		203
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#define RESET_PERIPHS_ASYNC_1		204
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#define RESET_PERIPHS_SPI_0		205
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#define RESET_PERIPHS_SPI_1		206
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#define RESET_PERIPHS_LED_PWM		207
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/*					208-223	*/
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/*	RESET7					*/
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/*					224-255	*/
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#endif
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