Path: blob/master/include/dt-bindings/reset/imx7-reset.h
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/* SPDX-License-Identifier: GPL-2.0-only */1/*2* Copyright (C) 2017 Impinj, Inc.3*4* Author: Andrey Smirnov <[email protected]>5*/67#ifndef DT_BINDING_RESET_IMX7_H8#define DT_BINDING_RESET_IMX7_H910#define IMX7_RESET_A7_CORE_POR_RESET0 011#define IMX7_RESET_A7_CORE_POR_RESET1 112#define IMX7_RESET_A7_CORE_RESET0 213#define IMX7_RESET_A7_CORE_RESET1 314#define IMX7_RESET_A7_DBG_RESET0 415#define IMX7_RESET_A7_DBG_RESET1 516#define IMX7_RESET_A7_ETM_RESET0 617#define IMX7_RESET_A7_ETM_RESET1 718#define IMX7_RESET_A7_SOC_DBG_RESET 819#define IMX7_RESET_A7_L2RESET 920#define IMX7_RESET_SW_M4C_RST 1021#define IMX7_RESET_SW_M4P_RST 1122#define IMX7_RESET_EIM_RST 1223#define IMX7_RESET_HSICPHY_PORT_RST 1324#define IMX7_RESET_USBPHY1_POR 1425#define IMX7_RESET_USBPHY1_PORT_RST 1526#define IMX7_RESET_USBPHY2_POR 1627#define IMX7_RESET_USBPHY2_PORT_RST 1728#define IMX7_RESET_MIPI_PHY_MRST 1829#define IMX7_RESET_MIPI_PHY_SRST 193031/*32* IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN33* and PCIEPHY_G_RST34*/35#define IMX7_RESET_PCIEPHY 2036#define IMX7_RESET_PCIEPHY_PERST 213738/*39* IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it40* can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht41* of as one42*/43#define IMX7_RESET_PCIE_CTRL_APPS_EN 2244#define IMX7_RESET_DDRC_PRST 2345#define IMX7_RESET_DDRC_CORE_RST 244647#define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 254849#define IMX7_RESET_NUM 265051#endif52535455