CoCalc -- imx8ulp-pcc-reset.h

GitHub Repository: torvalds/linux
Path: blob/master/include/dt-bindings/reset/imx8ulp-pcc-reset.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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 * Copyright 2021 NXP
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 */
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#ifndef DT_BINDING_PCC_RESET_IMX8ULP_H
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#define DT_BINDING_PCC_RESET_IMX8ULP_H
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/* PCC3 */
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#define PCC3_WDOG3_SWRST	0
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#define PCC3_WDOG4_SWRST	1
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#define PCC3_LPIT1_SWRST	2
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#define PCC3_TPM4_SWRST		3
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#define PCC3_TPM5_SWRST		4
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#define PCC3_FLEXIO1_SWRST	5
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#define PCC3_I3C2_SWRST		6
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#define PCC3_LPI2C4_SWRST	7
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#define PCC3_LPI2C5_SWRST	8
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#define PCC3_LPUART4_SWRST	9
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#define PCC3_LPUART5_SWRST	10
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#define PCC3_LPSPI4_SWRST	11
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#define PCC3_LPSPI5_SWRST	12
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/* PCC4 */
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#define PCC4_FLEXSPI2_SWRST	0
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#define PCC4_TPM6_SWRST		1
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#define PCC4_TPM7_SWRST		2
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#define PCC4_LPI2C6_SWRST	3
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#define PCC4_LPI2C7_SWRST	4
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#define PCC4_LPUART6_SWRST	5
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#define PCC4_LPUART7_SWRST	6
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#define PCC4_SAI4_SWRST		7
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#define PCC4_SAI5_SWRST		8
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#define PCC4_USDHC0_SWRST	9
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#define PCC4_USDHC1_SWRST	10
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#define PCC4_USDHC2_SWRST	11
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#define PCC4_USB0_SWRST		12
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#define PCC4_USB0_PHY_SWRST	13
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#define PCC4_USB1_SWRST		14
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#define PCC4_USB1_PHY_SWRST	15
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#define PCC4_ENET_SWRST		16
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/* PCC5 */
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#define PCC5_TPM8_SWRST		0
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#define PCC5_SAI6_SWRST		1
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#define PCC5_SAI7_SWRST		2
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#define PCC5_SPDIF_SWRST	3
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#define PCC5_ISI_SWRST		4
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#define PCC5_CSI_REGS_SWRST	5
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#define PCC5_CSI_SWRST		6
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#define PCC5_DSI_SWRST		7
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#define PCC5_WDOG5_SWRST	8
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#define PCC5_EPDC_SWRST		9
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#define PCC5_PXP_SWRST		10
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#define PCC5_GPU2D_SWRST	11
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#define PCC5_GPU3D_SWRST	12
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#define PCC5_DC_NANO_SWRST	13
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#endif /*DT_BINDING_RESET_IMX8ULP_H */
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