Path: blob/master/include/dt-bindings/reset/mediatek,mt6735-pericfg.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */12#ifndef _DT_BINDINGS_RESET_MT6735_PERICFG_H3#define _DT_BINDINGS_RESET_MT6735_PERICFG_H45#define MT6735_PERI_RST0_UART0 06#define MT6735_PERI_RST0_UART1 17#define MT6735_PERI_RST0_UART2 28#define MT6735_PERI_RST0_UART3 39#define MT6735_PERI_RST0_UART4 410#define MT6735_PERI_RST0_BTIF 511#define MT6735_PERI_RST0_DISP_PWM_PERI 612#define MT6735_PERI_RST0_PWM 713#define MT6735_PERI_RST0_AUXADC 814#define MT6735_PERI_RST0_DMA 915#define MT6735_PERI_RST0_IRDA 1016#define MT6735_PERI_RST0_IRTX 1117#define MT6735_PERI_RST0_THERM 1218#define MT6735_PERI_RST0_MSDC2 1319#define MT6735_PERI_RST0_MSDC3 1420#define MT6735_PERI_RST0_MSDC0 1521#define MT6735_PERI_RST0_MSDC1 1622#define MT6735_PERI_RST0_I2C0 1723#define MT6735_PERI_RST0_I2C1 1824#define MT6735_PERI_RST0_I2C2 1925#define MT6735_PERI_RST0_I2C3 2026#define MT6735_PERI_RST0_USB 212728#define MT6735_PERI_RST1_SPI0 222930#endif313233