Path: blob/master/include/dt-bindings/reset/mediatek,mt6795-resets.h
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */1/*2* Copyright (c) 2022 Collabora Ltd.3* Author: AngeloGioacchino Del Regno <[email protected]>4*/56#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT67957#define _DT_BINDINGS_RESET_CONTROLLER_MT679589/* INFRACFG resets */10#define MT6795_INFRA_RST0_SCPSYS_RST 011#define MT6795_INFRA_RST0_PMIC_WRAP_RST 112#define MT6795_INFRA_RST1_MIPI_DSI_RST 213#define MT6795_INFRA_RST1_MIPI_CSI_RST 314#define MT6795_INFRA_RST1_MM_IOMMU_RST 41516/* MMSYS resets */17#define MT6795_MMSYS_SW0_RST_B_SMI_COMMON 018#define MT6795_MMSYS_SW0_RST_B_SMI_LARB 119#define MT6795_MMSYS_SW0_RST_B_CAM_MDP 220#define MT6795_MMSYS_SW0_RST_B_MDP_RDMA0 321#define MT6795_MMSYS_SW0_RST_B_MDP_RDMA1 422#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ0 523#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ1 624#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ2 725#define MT6795_MMSYS_SW0_RST_B_MDP_TDSHP0 826#define MT6795_MMSYS_SW0_RST_B_MDP_TDSHP1 927#define MT6795_MMSYS_SW0_RST_B_MDP_WDMA 1028#define MT6795_MMSYS_SW0_RST_B_MDP_WROT0 1129#define MT6795_MMSYS_SW0_RST_B_MDP_WROT1 1230#define MT6795_MMSYS_SW0_RST_B_MDP_CROP 133132/* PERICFG resets */33#define MT6795_PERI_NFI_SW_RST 034#define MT6795_PERI_THERM_SW_RST 135#define MT6795_PERI_MSDC1_SW_RST 23637/* TOPRGU resets */38#define MT6795_TOPRGU_INFRA_SW_RST 039#define MT6795_TOPRGU_MM_SW_RST 140#define MT6795_TOPRGU_MFG_SW_RST 241#define MT6795_TOPRGU_VENC_SW_RST 342#define MT6795_TOPRGU_VDEC_SW_RST 443#define MT6795_TOPRGU_IMG_SW_RST 544#define MT6795_TOPRGU_DDRPHY_SW_RST 645#define MT6795_TOPRGU_MD_SW_RST 746#define MT6795_TOPRGU_INFRA_AO_SW_RST 847#define MT6795_TOPRGU_MD_LITE_SW_RST 948#define MT6795_TOPRGU_APMIXED_SW_RST 1049#define MT6795_TOPRGU_PWRAP_SPI_CTL_RST 1150#define MT6795_TOPRGU_SW_RST_NUM 125152#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT6795 */535455