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torvalds
GitHub Repository: torvalds/linux
Path: blob/master/include/dt-bindings/thermal/mediatek,lvts-thermal.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023 MediaTek Inc.
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* Author: Balsam CHIHI <[email protected]>
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*/
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#ifndef __MEDIATEK_LVTS_DT_H
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#define __MEDIATEK_LVTS_DT_H
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#define MT7987_CPU 0
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#define MT7987_ETH2P5G 1
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#define MT7988_CPU_0 0
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#define MT7988_CPU_1 1
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#define MT7988_ETH2P5G_0 2
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#define MT7988_ETH2P5G_1 3
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#define MT7988_TOPS_0 4
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#define MT7988_TOPS_1 5
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#define MT7988_ETHWARP_0 6
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#define MT7988_ETHWARP_1 7
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#define MT8186_LITTLE_CPU0 0
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#define MT8186_LITTLE_CPU1 1
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#define MT8186_LITTLE_CPU2 2
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#define MT8186_CAM 3
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#define MT8186_BIG_CPU0 4
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#define MT8186_BIG_CPU1 5
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#define MT8186_NNA 6
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#define MT8186_ADSP 7
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#define MT8186_GPU 8
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#define MT8188_MCU_LITTLE_CPU0 0
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#define MT8188_MCU_LITTLE_CPU1 1
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#define MT8188_MCU_LITTLE_CPU2 2
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#define MT8188_MCU_LITTLE_CPU3 3
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#define MT8188_MCU_BIG_CPU0 4
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#define MT8188_MCU_BIG_CPU1 5
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#define MT8188_AP_APU 0
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#define MT8188_AP_GPU0 1
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#define MT8188_AP_GPU1 2
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#define MT8188_AP_ADSP 3
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#define MT8188_AP_VDO 4
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#define MT8188_AP_INFRA 5
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#define MT8188_AP_CAM1 6
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#define MT8188_AP_CAM2 7
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#define MT8195_MCU_BIG_CPU0 0
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#define MT8195_MCU_BIG_CPU1 1
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#define MT8195_MCU_BIG_CPU2 2
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#define MT8195_MCU_BIG_CPU3 3
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#define MT8195_MCU_LITTLE_CPU0 4
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#define MT8195_MCU_LITTLE_CPU1 5
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#define MT8195_MCU_LITTLE_CPU2 6
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#define MT8195_MCU_LITTLE_CPU3 7
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#define MT8195_AP_VPU0 8
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#define MT8195_AP_VPU1 9
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#define MT8195_AP_GPU0 10
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#define MT8195_AP_GPU1 11
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#define MT8195_AP_VDEC 12
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#define MT8195_AP_IMG 13
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#define MT8195_AP_INFRA 14
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#define MT8195_AP_CAM0 15
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#define MT8195_AP_CAM1 16
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#define MT8192_MCU_BIG_CPU0 0
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#define MT8192_MCU_BIG_CPU1 1
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#define MT8192_MCU_BIG_CPU2 2
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#define MT8192_MCU_BIG_CPU3 3
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#define MT8192_MCU_LITTLE_CPU0 4
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#define MT8192_MCU_LITTLE_CPU1 5
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#define MT8192_MCU_LITTLE_CPU2 6
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#define MT8192_MCU_LITTLE_CPU3 7
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#define MT8192_AP_VPU0 8
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#define MT8192_AP_VPU1 9
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#define MT8192_AP_GPU0 10
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#define MT8192_AP_GPU1 11
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#define MT8192_AP_INFRA 12
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#define MT8192_AP_CAM 13
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#define MT8192_AP_MD0 14
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#define MT8192_AP_MD1 15
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#define MT8192_AP_MD2 16
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#define MT8196_MCU_MEDIUM_CPU6_0 0
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#define MT8196_MCU_MEDIUM_CPU6_1 1
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#define MT8196_MCU_DSU2 2
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#define MT8196_MCU_DSU3 3
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#define MT8196_MCU_LITTLE_CPU3 4
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#define MT8196_MCU_LITTLE_CPU0 5
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#define MT8196_MCU_LITTLE_CPU1 6
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#define MT8196_MCU_LITTLE_CPU2 7
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#define MT8196_MCU_MEDIUM_CPU4_0 8
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#define MT8196_MCU_MEDIUM_CPU4_1 9
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#define MT8196_MCU_MEDIUM_CPU5_0 10
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#define MT8196_MCU_MEDIUM_CPU5_1 11
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#define MT8196_MCU_DSU0 12
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#define MT8196_MCU_DSU1 13
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#define MT8196_MCU_BIG_CPU7_0 14
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#define MT8196_MCU_BIG_CPU7_1 15
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#define MT8196_AP_TOP0 0
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#define MT8196_AP_TOP1 1
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#define MT8196_AP_TOP2 2
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#define MT8196_AP_TOP3 3
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#define MT8196_AP_BOT0 4
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#define MT8196_AP_BOT1 5
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#define MT8196_AP_BOT2 6
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#define MT8196_AP_BOT3 7
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#endif /* __MEDIATEK_LVTS_DT_H */
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