/* SPDX-License-Identifier: GPL-2.0 */1/*2* tda1997x - NXP HDMI receiver3*4* Copyright 2017 Tim Harvey <[email protected]>5*6*/78#ifndef _TDA1997X_9#define _TDA1997X_1011/* Platform Data */12struct tda1997x_platform_data {13enum v4l2_mbus_type vidout_bus_type;14u32 vidout_bus_width;15u8 vidout_port_cfg[9];16/* pin polarity (1=invert) */17bool vidout_inv_de;18bool vidout_inv_hs;19bool vidout_inv_vs;20bool vidout_inv_pclk;21/* clock delays (0=-8, 1=-7 ... 15=+7 pixels) */22u8 vidout_delay_hs;23u8 vidout_delay_vs;24u8 vidout_delay_de;25u8 vidout_delay_pclk;26/* sync selections (controls how sync pins are derived) */27u8 vidout_sel_hs;28u8 vidout_sel_vs;29u8 vidout_sel_de;3031/* Audio Port Output */32int audout_format;33u32 audout_mclk_fs; /* clock multiplier */34u32 audout_width; /* 13 or 32 bit */35u32 audout_layout; /* layout0=AP0 layout1=AP0,AP1,AP2,AP3 */36bool audout_layoutauto; /* audio layout dictated by pkt header */37bool audout_invert_clk; /* data valid on rising edge of BCLK */38bool audio_auto_mute; /* enable hardware audio auto-mute */39};4041#endif424344