/* SPDX-License-Identifier: GPL-2.0-or-later */1/* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics2* Digitizer with Horizontal PLL registers3*4* Copyright (C) 2009 Texas Instruments Inc5* Author: Santiago Nunez-Corrales <[email protected]>6*7* This code is partially based upon the TVP5150 driver8* written by Mauro Carvalho Chehab <[email protected]>,9* the TVP514x driver written by Vaibhav Hiremath <[email protected]>10* and the TVP7002 driver in the TI LSP 2.10.00.1411*/12#ifndef _TVP7002_H_13#define _TVP7002_H_1415#define TVP7002_MODULE_NAME "tvp7002"1617/**18* struct tvp7002_config - Platform dependent data19*@clk_polarity: Clock polarity20* 0 - Data clocked out on rising edge of DATACLK signal21* 1 - Data clocked out on falling edge of DATACLK signal22*@hs_polarity: HSYNC polarity23* 0 - Active low HSYNC output, 1 - Active high HSYNC output24*@vs_polarity: VSYNC Polarity25* 0 - Active low VSYNC output, 1 - Active high VSYNC output26*@fid_polarity: Active-high Field ID polarity.27* 0 - The field ID output is set to logic 1 for an odd field28* (field 1) and set to logic 0 for an even field (field 0).29* 1 - Operation with polarity inverted.30*@sog_polarity: Active high Sync on Green output polarity.31* 0 - Normal operation, 1 - Operation with polarity inverted32*/33struct tvp7002_config {34bool clk_polarity;35bool hs_polarity;36bool vs_polarity;37bool fid_polarity;38bool sog_polarity;39};40#endif414243