Book a Demo!
CoCalc Logo Icon
StoreFeaturesDocsShareSupportNewsAboutPoliciesSign UpSign In
torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/include/soc/spacemit/k1-syscon.h
26288 views
1
/* SPDX-License-Identifier: GPL-2.0-only */

2


3
/* SpacemiT clock and reset driver definitions for the K1 SoC */

4


5
#ifndef __SOC_K1_SYSCON_H__

6
#define __SOC_K1_SYSCON_H__

7


8
/* Auxiliary device used to represent a CCU reset controller */

9
struct spacemit_ccu_adev {

10
	struct auxiliary_device adev;

11
	struct regmap *regmap;

12
};

13


14
static inline struct spacemit_ccu_adev *

15
to_spacemit_ccu_adev(struct auxiliary_device *adev)

16
{

17
	return container_of(adev, struct spacemit_ccu_adev, adev);

18
}

19


20
/* APBS register offset */

21
#define APBS_PLL1_SWCR1			0x100

22
#define APBS_PLL1_SWCR2			0x104

23
#define APBS_PLL1_SWCR3			0x108

24
#define APBS_PLL2_SWCR1			0x118

25
#define APBS_PLL2_SWCR2			0x11c

26
#define APBS_PLL2_SWCR3			0x120

27
#define APBS_PLL3_SWCR1			0x124

28
#define APBS_PLL3_SWCR2			0x128

29
#define APBS_PLL3_SWCR3			0x12c

30


31
/* MPMU register offset */

32
#define MPMU_POSR			0x0010

33
#define  POSR_PLL1_LOCK			BIT(27)

34
#define  POSR_PLL2_LOCK			BIT(28)

35
#define  POSR_PLL3_LOCK			BIT(29)

36
#define MPMU_SUCCR			0x0014

37
#define MPMU_ISCCR			0x0044

38
#define MPMU_WDTPCR			0x0200

39
#define MPMU_RIPCCR			0x0210

40
#define MPMU_ACGR			0x1024

41
#define MPMU_APBCSCR			0x1050

42
#define MPMU_SUCCR_1			0x10b0

43


44
/* APBC register offset */

45
#define APBC_UART1_CLK_RST		0x00

46
#define APBC_UART2_CLK_RST		0x04

47
#define APBC_GPIO_CLK_RST		0x08

48
#define APBC_PWM0_CLK_RST		0x0c

49
#define APBC_PWM1_CLK_RST		0x10

50
#define APBC_PWM2_CLK_RST		0x14

51
#define APBC_PWM3_CLK_RST		0x18

52
#define APBC_TWSI8_CLK_RST		0x20

53
#define APBC_UART3_CLK_RST		0x24

54
#define APBC_RTC_CLK_RST		0x28

55
#define APBC_TWSI0_CLK_RST		0x2c

56
#define APBC_TWSI1_CLK_RST		0x30

57
#define APBC_TIMERS1_CLK_RST		0x34

58
#define APBC_TWSI2_CLK_RST		0x38

59
#define APBC_AIB_CLK_RST		0x3c

60
#define APBC_TWSI4_CLK_RST		0x40

61
#define APBC_TIMERS2_CLK_RST		0x44

62
#define APBC_ONEWIRE_CLK_RST		0x48

63
#define APBC_TWSI5_CLK_RST		0x4c

64
#define APBC_DRO_CLK_RST		0x58

65
#define APBC_IR_CLK_RST			0x5c

66
#define APBC_TWSI6_CLK_RST		0x60

67
#define APBC_COUNTER_CLK_SEL		0x64

68
#define APBC_TWSI7_CLK_RST		0x68

69
#define APBC_TSEN_CLK_RST		0x6c

70
#define APBC_UART4_CLK_RST		0x70

71
#define APBC_UART5_CLK_RST		0x74

72
#define APBC_UART6_CLK_RST		0x78

73
#define APBC_SSP3_CLK_RST		0x7c

74
#define APBC_SSPA0_CLK_RST		0x80

75
#define APBC_SSPA1_CLK_RST		0x84

76
#define APBC_IPC_AP2AUD_CLK_RST		0x90

77
#define APBC_UART7_CLK_RST		0x94

78
#define APBC_UART8_CLK_RST		0x98

79
#define APBC_UART9_CLK_RST		0x9c

80
#define APBC_CAN0_CLK_RST		0xa0

81
#define APBC_PWM4_CLK_RST		0xa8

82
#define APBC_PWM5_CLK_RST		0xac

83
#define APBC_PWM6_CLK_RST		0xb0

84
#define APBC_PWM7_CLK_RST		0xb4

85
#define APBC_PWM8_CLK_RST		0xb8

86
#define APBC_PWM9_CLK_RST		0xbc

87
#define APBC_PWM10_CLK_RST		0xc0

88
#define APBC_PWM11_CLK_RST		0xc4

89
#define APBC_PWM12_CLK_RST		0xc8

90
#define APBC_PWM13_CLK_RST		0xcc

91
#define APBC_PWM14_CLK_RST		0xd0

92
#define APBC_PWM15_CLK_RST		0xd4

93
#define APBC_PWM16_CLK_RST		0xd8

94
#define APBC_PWM17_CLK_RST		0xdc

95
#define APBC_PWM18_CLK_RST		0xe0

96
#define APBC_PWM19_CLK_RST		0xe4

97


98
/* APMU register offset */

99
#define APMU_JPG_CLK_RES_CTRL		0x020

100
#define APMU_CSI_CCIC2_CLK_RES_CTRL	0x024

101
#define APMU_ISP_CLK_RES_CTRL		0x038

102
#define APMU_LCD_CLK_RES_CTRL1		0x044

103
#define APMU_LCD_SPI_CLK_RES_CTRL	0x048

104
#define APMU_LCD_CLK_RES_CTRL2		0x04c

105
#define APMU_CCIC_CLK_RES_CTRL		0x050

106
#define APMU_SDH0_CLK_RES_CTRL		0x054

107
#define APMU_SDH1_CLK_RES_CTRL		0x058

108
#define APMU_USB_CLK_RES_CTRL		0x05c

109
#define APMU_QSPI_CLK_RES_CTRL		0x060

110
#define APMU_DMA_CLK_RES_CTRL		0x064

111
#define APMU_AES_CLK_RES_CTRL		0x068

112
#define APMU_VPU_CLK_RES_CTRL		0x0a4

113
#define APMU_GPU_CLK_RES_CTRL		0x0cc

114
#define APMU_SDH2_CLK_RES_CTRL		0x0e0

115
#define APMU_PMUA_MC_CTRL		0x0e8

116
#define APMU_PMU_CC2_AP			0x100

117
#define APMU_PMUA_EM_CLK_RES_CTRL	0x104

118
#define APMU_AUDIO_CLK_RES_CTRL		0x14c

119
#define APMU_HDMI_CLK_RES_CTRL		0x1b8

120
#define APMU_CCI550_CLK_CTRL		0x300

121
#define APMU_ACLK_CLK_CTRL		0x388

122
#define APMU_CPU_C0_CLK_CTRL		0x38C

123
#define APMU_CPU_C1_CLK_CTRL		0x390

124
#define APMU_PCIE_CLK_RES_CTRL_0	0x3cc

125
#define APMU_PCIE_CLK_RES_CTRL_1	0x3d4

126
#define APMU_PCIE_CLK_RES_CTRL_2	0x3dc

127
#define APMU_EMAC0_CLK_RES_CTRL		0x3e4

128
#define APMU_EMAC1_CLK_RES_CTRL		0x3ec

129


130
/* RCPU register offsets */

131
#define RCPU_SSP0_CLK_RST		0x0028

132
#define RCPU_I2C0_CLK_RST		0x0030

133
#define RCPU_UART1_CLK_RST		0x003c

134
#define RCPU_CAN_CLK_RST		0x0048

135
#define RCPU_IR_CLK_RST			0x004c

136
#define RCPU_UART0_CLK_RST		0x00d8

137
#define AUDIO_HDMI_CLK_CTRL		0x2044

138


139
/* RCPU2 register offsets */

140
#define RCPU2_PWM0_CLK_RST		0x0000

141
#define RCPU2_PWM1_CLK_RST		0x0004

142
#define RCPU2_PWM2_CLK_RST		0x0008

143
#define RCPU2_PWM3_CLK_RST		0x000c

144
#define RCPU2_PWM4_CLK_RST		0x0010

145
#define RCPU2_PWM5_CLK_RST		0x0014

146
#define RCPU2_PWM6_CLK_RST		0x0018

147
#define RCPU2_PWM7_CLK_RST		0x001c

148
#define RCPU2_PWM8_CLK_RST		0x0020

149
#define RCPU2_PWM9_CLK_RST		0x0024

150


151
/* APBC2 register offsets */

152
#define APBC2_UART1_CLK_RST		0x0000

153
#define APBC2_SSP2_CLK_RST		0x0004

154
#define APBC2_TWSI3_CLK_RST		0x0008

155
#define APBC2_RTC_CLK_RST		0x000c

156
#define APBC2_TIMERS0_CLK_RST		0x0010

157
#define APBC2_KPC_CLK_RST		0x0014

158
#define APBC2_GPIO_CLK_RST		0x001c

159


160
#endif /* __SOC_K1_SYSCON_H__ */

161


162