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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/include/soc/spacemit/k1-syscon.h
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/* SPDX-License-Identifier: GPL-2.0-only */

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/* SpacemiT clock and reset driver definitions for the K1 SoC */

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#ifndef __SOC_K1_SYSCON_H__

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#define __SOC_K1_SYSCON_H__

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/* Auxiliary device used to represent a CCU reset controller */

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struct spacemit_ccu_adev {

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	struct auxiliary_device adev;

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	struct regmap *regmap;

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};

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static inline struct spacemit_ccu_adev *

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to_spacemit_ccu_adev(struct auxiliary_device *adev)

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{

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	return container_of(adev, struct spacemit_ccu_adev, adev);

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}

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/* APBS register offset */

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#define APBS_PLL1_SWCR1			0x100

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#define APBS_PLL1_SWCR2			0x104

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#define APBS_PLL1_SWCR3			0x108

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#define APBS_PLL2_SWCR1			0x118

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#define APBS_PLL2_SWCR2			0x11c

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#define APBS_PLL2_SWCR3			0x120

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#define APBS_PLL3_SWCR1			0x124

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#define APBS_PLL3_SWCR2			0x128

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#define APBS_PLL3_SWCR3			0x12c

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/* MPMU register offset */

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#define MPMU_POSR			0x0010

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#define MPMU_FCCR			0x0008

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#define  POSR_PLL1_LOCK			BIT(27)

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#define  POSR_PLL2_LOCK			BIT(28)

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#define  POSR_PLL3_LOCK			BIT(29)

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#define MPMU_SUCCR			0x0014

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#define MPMU_ISCCR			0x0044

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#define MPMU_WDTPCR			0x0200

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#define MPMU_RIPCCR			0x0210

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#define MPMU_ACGR			0x1024

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#define MPMU_APBCSCR			0x1050

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#define MPMU_SUCCR_1			0x10b0

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/* APBC register offset */

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#define APBC_UART1_CLK_RST		0x00

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#define APBC_UART2_CLK_RST		0x04

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#define APBC_GPIO_CLK_RST		0x08

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#define APBC_PWM0_CLK_RST		0x0c

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#define APBC_PWM1_CLK_RST		0x10

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#define APBC_PWM2_CLK_RST		0x14

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#define APBC_PWM3_CLK_RST		0x18

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#define APBC_TWSI8_CLK_RST		0x20

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#define APBC_UART3_CLK_RST		0x24

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#define APBC_RTC_CLK_RST		0x28

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#define APBC_TWSI0_CLK_RST		0x2c

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#define APBC_TWSI1_CLK_RST		0x30

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#define APBC_TIMERS1_CLK_RST		0x34

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#define APBC_TWSI2_CLK_RST		0x38

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#define APBC_AIB_CLK_RST		0x3c

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#define APBC_TWSI4_CLK_RST		0x40

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#define APBC_TIMERS2_CLK_RST		0x44

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#define APBC_ONEWIRE_CLK_RST		0x48

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#define APBC_TWSI5_CLK_RST		0x4c

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#define APBC_DRO_CLK_RST		0x58

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#define APBC_IR_CLK_RST			0x5c

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#define APBC_TWSI6_CLK_RST		0x60

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#define APBC_COUNTER_CLK_SEL		0x64

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#define APBC_TWSI7_CLK_RST		0x68

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#define APBC_TSEN_CLK_RST		0x6c

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#define APBC_UART4_CLK_RST		0x70

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#define APBC_UART5_CLK_RST		0x74

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#define APBC_UART6_CLK_RST		0x78

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#define APBC_SSP3_CLK_RST		0x7c

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#define APBC_SSPA0_CLK_RST		0x80

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#define APBC_SSPA1_CLK_RST		0x84

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#define APBC_IPC_AP2AUD_CLK_RST		0x90

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#define APBC_UART7_CLK_RST		0x94

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#define APBC_UART8_CLK_RST		0x98

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#define APBC_UART9_CLK_RST		0x9c

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#define APBC_CAN0_CLK_RST		0xa0

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#define APBC_PWM4_CLK_RST		0xa8

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#define APBC_PWM5_CLK_RST		0xac

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#define APBC_PWM6_CLK_RST		0xb0

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#define APBC_PWM7_CLK_RST		0xb4

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#define APBC_PWM8_CLK_RST		0xb8

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#define APBC_PWM9_CLK_RST		0xbc

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#define APBC_PWM10_CLK_RST		0xc0

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#define APBC_PWM11_CLK_RST		0xc4

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#define APBC_PWM12_CLK_RST		0xc8

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#define APBC_PWM13_CLK_RST		0xcc

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#define APBC_PWM14_CLK_RST		0xd0

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#define APBC_PWM15_CLK_RST		0xd4

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#define APBC_PWM16_CLK_RST		0xd8

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#define APBC_PWM17_CLK_RST		0xdc

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#define APBC_PWM18_CLK_RST		0xe0

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#define APBC_PWM19_CLK_RST		0xe4

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/* APMU register offset */

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#define APMU_JPG_CLK_RES_CTRL		0x020

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#define APMU_CSI_CCIC2_CLK_RES_CTRL	0x024

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#define APMU_ISP_CLK_RES_CTRL		0x038

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#define APMU_LCD_CLK_RES_CTRL1		0x044

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#define APMU_LCD_SPI_CLK_RES_CTRL	0x048

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#define APMU_LCD_CLK_RES_CTRL2		0x04c

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#define APMU_CCIC_CLK_RES_CTRL		0x050

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#define APMU_SDH0_CLK_RES_CTRL		0x054

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#define APMU_SDH1_CLK_RES_CTRL		0x058

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#define APMU_USB_CLK_RES_CTRL		0x05c

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#define APMU_QSPI_CLK_RES_CTRL		0x060

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#define APMU_DMA_CLK_RES_CTRL		0x064

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#define APMU_AES_CLK_RES_CTRL		0x068

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#define APMU_VPU_CLK_RES_CTRL		0x0a4

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#define APMU_GPU_CLK_RES_CTRL		0x0cc

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#define APMU_SDH2_CLK_RES_CTRL		0x0e0

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#define APMU_PMUA_MC_CTRL		0x0e8

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#define APMU_PMU_CC2_AP			0x100

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#define APMU_PMUA_EM_CLK_RES_CTRL	0x104

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#define APMU_AUDIO_CLK_RES_CTRL		0x14c

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#define APMU_HDMI_CLK_RES_CTRL		0x1b8

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#define APMU_CCI550_CLK_CTRL		0x300

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#define APMU_ACLK_CLK_CTRL		0x388

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#define APMU_CPU_C0_CLK_CTRL		0x38C

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#define APMU_CPU_C1_CLK_CTRL		0x390

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#define APMU_PCIE_CLK_RES_CTRL_0	0x3cc

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#define APMU_PCIE_CLK_RES_CTRL_1	0x3d4

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#define APMU_PCIE_CLK_RES_CTRL_2	0x3dc

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#define APMU_EMAC0_CLK_RES_CTRL		0x3e4

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#define APMU_EMAC1_CLK_RES_CTRL		0x3ec

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/* RCPU register offsets */

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#define RCPU_SSP0_CLK_RST		0x0028

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#define RCPU_I2C0_CLK_RST		0x0030

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#define RCPU_UART1_CLK_RST		0x003c

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#define RCPU_CAN_CLK_RST		0x0048

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#define RCPU_IR_CLK_RST			0x004c

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#define RCPU_UART0_CLK_RST		0x00d8

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#define AUDIO_HDMI_CLK_CTRL		0x2044

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/* RCPU2 register offsets */

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#define RCPU2_PWM0_CLK_RST		0x0000

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#define RCPU2_PWM1_CLK_RST		0x0004

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#define RCPU2_PWM2_CLK_RST		0x0008

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#define RCPU2_PWM3_CLK_RST		0x000c

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#define RCPU2_PWM4_CLK_RST		0x0010

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#define RCPU2_PWM5_CLK_RST		0x0014

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#define RCPU2_PWM6_CLK_RST		0x0018

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#define RCPU2_PWM7_CLK_RST		0x001c

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#define RCPU2_PWM8_CLK_RST		0x0020

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#define RCPU2_PWM9_CLK_RST		0x0024

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/* APBC2 register offsets */

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#define APBC2_UART1_CLK_RST		0x0000

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#define APBC2_SSP2_CLK_RST		0x0004

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#define APBC2_TWSI3_CLK_RST		0x0008

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#define APBC2_RTC_CLK_RST		0x000c

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#define APBC2_TIMERS0_CLK_RST		0x0010

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#define APBC2_KPC_CLK_RST		0x0014

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#define APBC2_GPIO_CLK_RST		0x001c

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#endif /* __SOC_K1_SYSCON_H__ */

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