/* SPDX-License-Identifier: GPL-2.0-or-later */1#ifndef __SOUND_CS4231_REGS_H2#define __SOUND_CS4231_REGS_H34/*5* Copyright (c) by Jaroslav Kysela <[email protected]>6* Definitions for CS4231 & InterWave chips & compatible chips registers7*/89/* IO ports */1011#define CS4231P(x) (c_d_c_CS4231##x)1213#define c_d_c_CS4231REGSEL 014#define c_d_c_CS4231REG 115#define c_d_c_CS4231STATUS 216#define c_d_c_CS4231PIO 31718/* codec registers */1920#define CS4231_LEFT_INPUT 0x00 /* left input control */21#define CS4231_RIGHT_INPUT 0x01 /* right input control */22#define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */23#define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */24#define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */25#define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */26#define CS4231_LEFT_OUTPUT 0x06 /* left output control register */27#define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */28#define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */29#define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */30#define CS4231_PIN_CTRL 0x0a /* pin control */31#define CS4231_TEST_INIT 0x0b /* test and initialization */32#define CS4231_MISC_INFO 0x0c /* miscellaneous information */33#define CS4231_LOOPBACK 0x0d /* loopback control */34#define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */35#define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */36#define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */37#define AD1845_AF1_MIC_LEFT 0x10 /* alternate #1 feature + MIC left */38#define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */39#define AD1845_AF2_MIC_RIGHT 0x11 /* alternate #2 feature + MIC right */40#define CS4231_LEFT_LINE_IN 0x12 /* left line input control */41#define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */42#define CS4231_TIMER_LOW 0x14 /* timer low byte */43#define CS4231_TIMER_HIGH 0x15 /* timer high byte */44#define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */45#define AD1845_UPR_FREQ_SEL 0x16 /* upper byte of frequency select */46#define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */47#define AD1845_LWR_FREQ_SEL 0x17 /* lower byte of frequency select */48#define CS4236_EXT_REG 0x17 /* extended register access */49#define CS4231_IRQ_STATUS 0x18 /* irq status register */50#define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */51#define CS4231_VERSION 0x19 /* CS4231(A) - version values */52#define CS4231_MONO_CTRL 0x1a /* mono input/output control */53#define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */54#define AD1845_PWR_DOWN 0x1b /* power down control */55#define CS4235_LEFT_MASTER 0x1b /* left master output control */56#define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */57#define AD1845_CLOCK 0x1d /* crystal clock select and total power down */58#define CS4235_RIGHT_MASTER 0x1d /* right master output control */59#define CS4231_REC_UPR_CNT 0x1e /* record upper count */60#define CS4231_REC_LWR_CNT 0x1f /* record lower count */6162/* definitions for codec register select port - CODECP( REGSEL ) */6364#define CS4231_INIT 0x80 /* CODEC is initializing */65#define CS4231_MCE 0x40 /* mode change enable */66#define CS4231_TRD 0x20 /* transfer request disable */6768/* definitions for codec status register - CODECP( STATUS ) */6970#define CS4231_GLOBALIRQ 0x01 /* IRQ is active */7172/* definitions for codec irq status */7374#define CS4231_PLAYBACK_IRQ 0x1075#define CS4231_RECORD_IRQ 0x2076#define CS4231_TIMER_IRQ 0x4077#define CS4231_ALL_IRQS 0x7078#define CS4231_REC_UNDERRUN 0x0879#define CS4231_REC_OVERRUN 0x0480#define CS4231_PLY_OVERRUN 0x0281#define CS4231_PLY_UNDERRUN 0x018283/* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */8485#define CS4231_ENABLE_MIC_GAIN 0x208687#define CS4231_MIXS_LINE 0x0088#define CS4231_MIXS_AUX1 0x4089#define CS4231_MIXS_MIC 0x8090#define CS4231_MIXS_ALL 0xc09192/* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */9394#define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */95#define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */96#define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */97#define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */98#define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */99#define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */100#define CS4231_STEREO 0x10 /* stereo mode */101/* bits 3-1 define frequency divisor */102#define CS4231_XTAL1 0x00 /* 24.576 crystal */103#define CS4231_XTAL2 0x01 /* 16.9344 crystal */104105/* definitions for interface control register - CS4231_IFACE_CTRL */106107#define CS4231_RECORD_PIO 0x80 /* record PIO enable */108#define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */109#define CS4231_CALIB_MODE 0x18 /* calibration mode bits */110#define CS4231_AUTOCALIB 0x08 /* auto calibrate */111#define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */112#define CS4231_RECORD_ENABLE 0x02 /* record enable */113#define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */114115/* definitions for pin control register - CS4231_PIN_CTRL */116117#define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */118#define CS4231_XCTL1 0x40 /* external control #1 */119#define CS4231_XCTL0 0x80 /* external control #0 */120121/* definitions for test and init register - CS4231_TEST_INIT */122123#define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */124#define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */125126/* definitions for misc control register - CS4231_MISC_INFO */127128#define CS4231_MODE2 0x40 /* MODE 2 */129#define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */130#define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */131132/* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */133134#define CS4231_DACZ 0x01 /* zero DAC when underrun */135#define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */136#define CS4231_OLB 0x80 /* output level bit */137138/* definitions for Extended Registers - CS4236+ */139140#define CS4236_REG(i23val) (((i23val << 2) & 0x10) | ((i23val >> 4) & 0x0f))141#define CS4236_I23VAL(reg) ((((reg)&0xf) << 4) | (((reg)&0x10) >> 2) | 0x8)142143#define CS4236_LEFT_LINE 0x08 /* left LINE alternate volume */144#define CS4236_RIGHT_LINE 0x18 /* right LINE alternate volume */145#define CS4236_LEFT_MIC 0x28 /* left MIC volume */146#define CS4236_RIGHT_MIC 0x38 /* right MIC volume */147#define CS4236_LEFT_MIX_CTRL 0x48 /* synthesis and left input mixer control */148#define CS4236_RIGHT_MIX_CTRL 0x58 /* right input mixer control */149#define CS4236_LEFT_FM 0x68 /* left FM volume */150#define CS4236_RIGHT_FM 0x78 /* right FM volume */151#define CS4236_LEFT_DSP 0x88 /* left DSP serial port volume */152#define CS4236_RIGHT_DSP 0x98 /* right DSP serial port volume */153#define CS4236_RIGHT_LOOPBACK 0xa8 /* right loopback monitor volume */154#define CS4236_DAC_MUTE 0xb8 /* DAC mute and IFSE enable */155#define CS4236_ADC_RATE 0xc8 /* indenpendent ADC sample frequency */156#define CS4236_DAC_RATE 0xd8 /* indenpendent DAC sample frequency */157#define CS4236_LEFT_MASTER 0xe8 /* left master digital audio volume */158#define CS4236_RIGHT_MASTER 0xf8 /* right master digital audio volume */159#define CS4236_LEFT_WAVE 0x0c /* left wavetable serial port volume */160#define CS4236_RIGHT_WAVE 0x1c /* right wavetable serial port volume */161#define CS4236_VERSION 0x9c /* chip version and ID */162163/* definitions for extended registers - OPTI93X */164#define OPTi931_AUX_LEFT_INPUT 0x10165#define OPTi931_AUX_RIGHT_INPUT 0x11166#define OPTi93X_MIC_LEFT_INPUT 0x14167#define OPTi93X_MIC_RIGHT_INPUT 0x15168#define OPTi93X_OUT_LEFT 0x16169#define OPTi93X_OUT_RIGHT 0x17170171#endif /* __SOUND_CS4231_REGS_H */172173174