/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */1/*2* Copyright (C) 2015 Etnaviv Project3*4* This program is free software; you can redistribute it and/or modify it5* under the terms of the GNU General Public License version 2 as published by6* the Free Software Foundation.7*8* This program is distributed in the hope that it will be useful, but WITHOUT9* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or10* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for11* more details.12*13* You should have received a copy of the GNU General Public License along with14* this program. If not, see <http://www.gnu.org/licenses/>.15*/1617#ifndef __ETNAVIV_DRM_H__18#define __ETNAVIV_DRM_H__1920#include "drm.h"2122#if defined(__cplusplus)23extern "C" {24#endif2526/* Please note that modifications to all structs defined here are27* subject to backwards-compatibility constraints:28* 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit29* user/kernel compatibility30* 2) Keep fields aligned to their size31* 3) Because of how drm_ioctl() works, we can add new fields at32* the end of an ioctl if some care is taken: drm_ioctl() will33* zero out the new fields at the tail of the ioctl, so a zero34* value should have a backwards compatible meaning. And for35* output params, userspace won't see the newly added output36* fields.. so that has to be somehow ok.37*/3839/* timeouts are specified in clock-monotonic absolute times (to simplify40* restarting interrupted ioctls). The following struct is logically the41* same as 'struct timespec' but 32/64b ABI safe.42*/43struct drm_etnaviv_timespec {44__s64 tv_sec; /* seconds */45__s64 tv_nsec; /* nanoseconds */46};4748#define ETNAVIV_PARAM_GPU_MODEL 0x0149#define ETNAVIV_PARAM_GPU_REVISION 0x0250#define ETNAVIV_PARAM_GPU_FEATURES_0 0x0351#define ETNAVIV_PARAM_GPU_FEATURES_1 0x0452#define ETNAVIV_PARAM_GPU_FEATURES_2 0x0553#define ETNAVIV_PARAM_GPU_FEATURES_3 0x0654#define ETNAVIV_PARAM_GPU_FEATURES_4 0x0755#define ETNAVIV_PARAM_GPU_FEATURES_5 0x0856#define ETNAVIV_PARAM_GPU_FEATURES_6 0x0957#define ETNAVIV_PARAM_GPU_FEATURES_7 0x0a58#define ETNAVIV_PARAM_GPU_FEATURES_8 0x0b59#define ETNAVIV_PARAM_GPU_FEATURES_9 0x0c60#define ETNAVIV_PARAM_GPU_FEATURES_10 0x0d61#define ETNAVIV_PARAM_GPU_FEATURES_11 0x0e62#define ETNAVIV_PARAM_GPU_FEATURES_12 0x0f6364#define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x1065#define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x1166#define ETNAVIV_PARAM_GPU_THREAD_COUNT 0x1267#define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x1368#define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x1469#define ETNAVIV_PARAM_GPU_PIXEL_PIPES 0x1570#define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x1671#define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x1772#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x1873#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x1974#define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a75#define ETNAVIV_PARAM_SOFTPIN_START_ADDR 0x1b76#define ETNAVIV_PARAM_GPU_PRODUCT_ID 0x1c77#define ETNAVIV_PARAM_GPU_CUSTOMER_ID 0x1d78#define ETNAVIV_PARAM_GPU_ECO_ID 0x1e7980#define ETNA_MAX_PIPES 48182struct drm_etnaviv_param {83__u32 pipe; /* in */84__u32 param; /* in, ETNAVIV_PARAM_x */85__u64 value; /* out (get_param) or in (set_param) */86};8788/*89* GEM buffers:90*/9192#define ETNA_BO_CACHE_MASK 0x000f000093/* cache modes */94#define ETNA_BO_CACHED 0x0001000095#define ETNA_BO_WC 0x0002000096#define ETNA_BO_UNCACHED 0x0004000097/* map flags */98#define ETNA_BO_FORCE_MMU 0x0010000099100struct drm_etnaviv_gem_new {101__u64 size; /* in */102__u32 flags; /* in, mask of ETNA_BO_x */103__u32 handle; /* out */104};105106struct drm_etnaviv_gem_info {107__u32 handle; /* in */108__u32 pad;109__u64 offset; /* out, offset to pass to mmap() */110};111112#define ETNA_PREP_READ 0x01113#define ETNA_PREP_WRITE 0x02114#define ETNA_PREP_NOSYNC 0x04115116struct drm_etnaviv_gem_cpu_prep {117__u32 handle; /* in */118__u32 op; /* in, mask of ETNA_PREP_x */119struct drm_etnaviv_timespec timeout; /* in */120};121122struct drm_etnaviv_gem_cpu_fini {123__u32 handle; /* in */124__u32 flags; /* in, placeholder for now, no defined values */125};126127/*128* Cmdstream Submission:129*/130131/* The value written into the cmdstream is logically:132* relocbuf->gpuaddr + reloc_offset133*134* NOTE that reloc's must be sorted by order of increasing submit_offset,135* otherwise EINVAL.136*/137struct drm_etnaviv_gem_submit_reloc {138__u32 submit_offset; /* in, offset from submit_bo */139__u32 reloc_idx; /* in, index of reloc_bo buffer */140__u64 reloc_offset; /* in, offset from start of reloc_bo */141__u32 flags; /* in, placeholder for now, no defined values */142};143144/* Each buffer referenced elsewhere in the cmdstream submit (ie. the145* cmdstream buffer(s) themselves or reloc entries) has one (and only146* one) entry in the submit->bos[] table.147*148* As a optimization, the current buffer (gpu virtual address) can be149* passed back through the 'presumed' field. If on a subsequent reloc,150* userspace passes back a 'presumed' address that is still valid,151* then patching the cmdstream for this entry is skipped. This can152* avoid kernel needing to map/access the cmdstream bo in the common153* case.154* If the submit is a softpin submit (ETNA_SUBMIT_SOFTPIN) the 'presumed'155* field is interpreted as the fixed location to map the bo into the gpu156* virtual address space. If the kernel is unable to map the buffer at157* this location the submit will fail. This means userspace is responsible158* for the whole gpu virtual address management.159*/160#define ETNA_SUBMIT_BO_READ 0x0001161#define ETNA_SUBMIT_BO_WRITE 0x0002162struct drm_etnaviv_gem_submit_bo {163__u32 flags; /* in, mask of ETNA_SUBMIT_BO_x */164__u32 handle; /* in, GEM handle */165__u64 presumed; /* in/out, presumed buffer address */166};167168/* performance monitor request (pmr) */169#define ETNA_PM_PROCESS_PRE 0x0001170#define ETNA_PM_PROCESS_POST 0x0002171struct drm_etnaviv_gem_submit_pmr {172__u32 flags; /* in, when to process request (ETNA_PM_PROCESS_x) */173__u8 domain; /* in, pm domain */174__u8 pad;175__u16 signal; /* in, pm signal */176__u32 sequence; /* in, sequence number */177__u32 read_offset; /* in, offset from read_bo */178__u32 read_idx; /* in, index of read_bo buffer */179};180181/* Each cmdstream submit consists of a table of buffers involved, and182* one or more cmdstream buffers. This allows for conditional execution183* (context-restore), and IB buffers needed for per tile/bin draw cmds.184*/185#define ETNA_SUBMIT_NO_IMPLICIT 0x0001186#define ETNA_SUBMIT_FENCE_FD_IN 0x0002187#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004188#define ETNA_SUBMIT_SOFTPIN 0x0008189#define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | \190ETNA_SUBMIT_FENCE_FD_IN | \191ETNA_SUBMIT_FENCE_FD_OUT| \192ETNA_SUBMIT_SOFTPIN)193#define ETNA_PIPE_3D 0x00194#define ETNA_PIPE_2D 0x01195#define ETNA_PIPE_VG 0x02196struct drm_etnaviv_gem_submit {197__u32 fence; /* out */198__u32 pipe; /* in */199__u32 exec_state; /* in, initial execution state (ETNA_PIPE_x) */200__u32 nr_bos; /* in, number of submit_bo's */201__u32 nr_relocs; /* in, number of submit_reloc's */202__u32 stream_size; /* in, cmdstream size */203__u64 bos; /* in, ptr to array of submit_bo's */204__u64 relocs; /* in, ptr to array of submit_reloc's */205__u64 stream; /* in, ptr to cmdstream */206__u32 flags; /* in, mask of ETNA_SUBMIT_x */207__s32 fence_fd; /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */208__u64 pmrs; /* in, ptr to array of submit_pmr's */209__u32 nr_pmrs; /* in, number of submit_pmr's */210__u32 pad;211};212213/* The normal way to synchronize with the GPU is just to CPU_PREP on214* a buffer if you need to access it from the CPU (other cmdstream215* submission from same or other contexts, PAGE_FLIP ioctl, etc, all216* handle the required synchronization under the hood). This ioctl217* mainly just exists as a way to implement the gallium pipe_fence218* APIs without requiring a dummy bo to synchronize on.219*/220#define ETNA_WAIT_NONBLOCK 0x01221struct drm_etnaviv_wait_fence {222__u32 pipe; /* in */223__u32 fence; /* in */224__u32 flags; /* in, mask of ETNA_WAIT_x */225__u32 pad;226struct drm_etnaviv_timespec timeout; /* in */227};228229#define ETNA_USERPTR_READ 0x01230#define ETNA_USERPTR_WRITE 0x02231struct drm_etnaviv_gem_userptr {232__u64 user_ptr; /* in, page aligned user pointer */233__u64 user_size; /* in, page aligned user size */234__u32 flags; /* in, flags */235__u32 handle; /* out, non-zero handle */236};237238struct drm_etnaviv_gem_wait {239__u32 pipe; /* in */240__u32 handle; /* in, bo to be waited for */241__u32 flags; /* in, mask of ETNA_WAIT_x */242__u32 pad;243struct drm_etnaviv_timespec timeout; /* in */244};245246/*247* Performance Monitor (PM):248*/249250struct drm_etnaviv_pm_domain {251__u32 pipe; /* in */252__u8 iter; /* in/out, select pm domain at index iter */253__u8 id; /* out, id of domain */254__u16 nr_signals; /* out, how many signals does this domain provide */255char name[64]; /* out, name of domain */256};257258struct drm_etnaviv_pm_signal {259__u32 pipe; /* in */260__u8 domain; /* in, pm domain index */261__u8 pad;262__u16 iter; /* in/out, select pm source at index iter */263__u16 id; /* out, id of signal */264char name[64]; /* out, name of domain */265};266267#define DRM_ETNAVIV_GET_PARAM 0x00268/* placeholder:269#define DRM_ETNAVIV_SET_PARAM 0x01270*/271#define DRM_ETNAVIV_GEM_NEW 0x02272#define DRM_ETNAVIV_GEM_INFO 0x03273#define DRM_ETNAVIV_GEM_CPU_PREP 0x04274#define DRM_ETNAVIV_GEM_CPU_FINI 0x05275#define DRM_ETNAVIV_GEM_SUBMIT 0x06276#define DRM_ETNAVIV_WAIT_FENCE 0x07277#define DRM_ETNAVIV_GEM_USERPTR 0x08278#define DRM_ETNAVIV_GEM_WAIT 0x09279#define DRM_ETNAVIV_PM_QUERY_DOM 0x0a280#define DRM_ETNAVIV_PM_QUERY_SIG 0x0b281#define DRM_ETNAVIV_NUM_IOCTLS 0x0c282283#define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)284#define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)285#define DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info)286#define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep)287#define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini)288#define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit)289#define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)290#define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)291#define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)292#define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)293#define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)294295#if defined(__cplusplus)296}297#endif298299#endif /* __ETNAVIV_DRM_H__ */300301302