CoCalc -- sha1-armv4-large.S

GitHub Repository: torvalds/linux
Path: blob/master/lib/crypto/arm/sha1-armv4-large.S
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#define __ARM_ARCH__ __LINUX_ARM_ARCH__
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@ SPDX-License-Identifier: GPL-2.0
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@ This code is taken from the OpenSSL project but the author (Andy Polyakov)
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@ has relicensed it under the GPLv2. Therefore this program is free software;
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@ you can redistribute it and/or modify it under the terms of the GNU General
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@ Public License version 2 as published by the Free Software Foundation.
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@
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@ The original headers, including the original license headers, are
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@ included below for completeness.
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@ ====================================================================
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@ Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
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@ project. The module is, however, dual licensed under OpenSSL and
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@ CRYPTOGAMS licenses depending on where you obtain it. For further
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@ details see https://www.openssl.org/~appro/cryptogams/.
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@ ====================================================================
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@ sha1_block procedure for ARMv4.
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@
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@ January 2007.
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@ Size/performance trade-off
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@ ====================================================================
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@ impl		size in bytes	comp cycles[*]	measured performance
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@ ====================================================================
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@ thumb		304		3212		4420
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@ armv4-small	392/+29%	1958/+64%	2250/+96%
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@ armv4-compact	740/+89%	1552/+26%	1840/+22%
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@ armv4-large	1420/+92%	1307/+19%	1370/+34%[***]
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@ full unroll	~5100/+260%	~1260/+4%	~1300/+5%
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@ ====================================================================
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@ thumb		= same as 'small' but in Thumb instructions[**] and
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@		  with recurring code in two private functions;
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@ small		= detached Xload/update, loops are folded;
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@ compact	= detached Xload/update, 5x unroll;
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@ large		= interleaved Xload/update, 5x unroll;
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@ full unroll	= interleaved Xload/update, full unroll, estimated[!];
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@
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@ [*]	Manually counted instructions in "grand" loop body. Measured
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@	performance is affected by prologue and epilogue overhead,
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@	i-cache availability, branch penalties, etc.
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@ [**]	While each Thumb instruction is twice smaller, they are not as
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@	diverse as ARM ones: e.g., there are only two arithmetic
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@	instructions with 3 arguments, no [fixed] rotate, addressing
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@	modes are limited. As result it takes more instructions to do
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@	the same job in Thumb, therefore the code is never twice as
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@	small and always slower.
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@ [***]	which is also ~35% better than compiler generated code. Dual-
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@	issue Cortex A8 core was measured to process input block in
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@	~990 cycles.
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@ August 2010.
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@
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@ Rescheduling for dual-issue pipeline resulted in 13% improvement on
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@ Cortex A8 core and in absolute terms ~870 cycles per input block
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@ [or 13.6 cycles per byte].
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@ February 2011.
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@
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@ Profiler-assisted and platform-specific optimization resulted in 10%
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@ improvement on Cortex A8 core and 12.2 cycles per byte.
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#include <linux/linkage.h>
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.text
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.align	2
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ENTRY(sha1_block_data_order)
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	stmdb	sp!,{r4-r12,lr}
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	add	r2,r1,r2,lsl#6	@ r2 to point at the end of r1
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	ldmia	r0,{r3,r4,r5,r6,r7}
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.Lloop:
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	ldr	r8,.LK_00_19
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	mov	r14,sp
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	sub	sp,sp,#15*4
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	mov	r5,r5,ror#30
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	mov	r6,r6,ror#30
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	mov	r7,r7,ror#30		@ [6]
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.L_00_15:
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#if __ARM_ARCH__<7
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	ldrb	r10,[r1,#2]
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	ldrb	r9,[r1,#3]
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	ldrb	r11,[r1,#1]
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	add	r7,r8,r7,ror#2			@ E+=K_00_19
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	ldrb	r12,[r1],#4
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	orr	r9,r9,r10,lsl#8
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	eor	r10,r5,r6			@ F_xx_xx
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	orr	r9,r9,r11,lsl#16
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	add	r7,r7,r3,ror#27			@ E+=ROR(A,27)
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	orr	r9,r9,r12,lsl#24
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#else
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	ldr	r9,[r1],#4			@ handles unaligned
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	add	r7,r8,r7,ror#2			@ E+=K_00_19
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	eor	r10,r5,r6			@ F_xx_xx
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	add	r7,r7,r3,ror#27			@ E+=ROR(A,27)
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#ifdef __ARMEL__
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	rev	r9,r9				@ byte swap
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#endif
100
#endif
101
	and	r10,r4,r10,ror#2
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	add	r7,r7,r9			@ E+=X[i]
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	eor	r10,r10,r6,ror#2		@ F_00_19(B,C,D)
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	str	r9,[r14,#-4]!
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	add	r7,r7,r10			@ E+=F_00_19(B,C,D)
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#if __ARM_ARCH__<7
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	ldrb	r10,[r1,#2]
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	ldrb	r9,[r1,#3]
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	ldrb	r11,[r1,#1]
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	add	r6,r8,r6,ror#2			@ E+=K_00_19
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	ldrb	r12,[r1],#4
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	orr	r9,r9,r10,lsl#8
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	eor	r10,r4,r5			@ F_xx_xx
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	orr	r9,r9,r11,lsl#16
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	add	r6,r6,r7,ror#27			@ E+=ROR(A,27)
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	orr	r9,r9,r12,lsl#24
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#else
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	ldr	r9,[r1],#4			@ handles unaligned
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	add	r6,r8,r6,ror#2			@ E+=K_00_19
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	eor	r10,r4,r5			@ F_xx_xx
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	add	r6,r6,r7,ror#27			@ E+=ROR(A,27)
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#ifdef __ARMEL__
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	rev	r9,r9				@ byte swap
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#endif
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#endif
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	and	r10,r3,r10,ror#2
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	add	r6,r6,r9			@ E+=X[i]
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	eor	r10,r10,r5,ror#2		@ F_00_19(B,C,D)
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	str	r9,[r14,#-4]!
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	add	r6,r6,r10			@ E+=F_00_19(B,C,D)
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#if __ARM_ARCH__<7
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	ldrb	r10,[r1,#2]
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	ldrb	r9,[r1,#3]
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	ldrb	r11,[r1,#1]
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	add	r5,r8,r5,ror#2			@ E+=K_00_19
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	ldrb	r12,[r1],#4
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	orr	r9,r9,r10,lsl#8
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	eor	r10,r3,r4			@ F_xx_xx
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	orr	r9,r9,r11,lsl#16
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	add	r5,r5,r6,ror#27			@ E+=ROR(A,27)
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	orr	r9,r9,r12,lsl#24
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#else
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	ldr	r9,[r1],#4			@ handles unaligned
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	add	r5,r8,r5,ror#2			@ E+=K_00_19
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	eor	r10,r3,r4			@ F_xx_xx
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	add	r5,r5,r6,ror#27			@ E+=ROR(A,27)
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#ifdef __ARMEL__
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	rev	r9,r9				@ byte swap
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#endif
150
#endif
151
	and	r10,r7,r10,ror#2
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	add	r5,r5,r9			@ E+=X[i]
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	eor	r10,r10,r4,ror#2		@ F_00_19(B,C,D)
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	str	r9,[r14,#-4]!
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	add	r5,r5,r10			@ E+=F_00_19(B,C,D)
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#if __ARM_ARCH__<7
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	ldrb	r10,[r1,#2]
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	ldrb	r9,[r1,#3]
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	ldrb	r11,[r1,#1]
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	add	r4,r8,r4,ror#2			@ E+=K_00_19
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	ldrb	r12,[r1],#4
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	orr	r9,r9,r10,lsl#8
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	eor	r10,r7,r3			@ F_xx_xx
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	orr	r9,r9,r11,lsl#16
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	add	r4,r4,r5,ror#27			@ E+=ROR(A,27)
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	orr	r9,r9,r12,lsl#24
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#else
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	ldr	r9,[r1],#4			@ handles unaligned
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	add	r4,r8,r4,ror#2			@ E+=K_00_19
170
	eor	r10,r7,r3			@ F_xx_xx
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	add	r4,r4,r5,ror#27			@ E+=ROR(A,27)
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#ifdef __ARMEL__
173
	rev	r9,r9				@ byte swap
174
#endif
175
#endif
176
	and	r10,r6,r10,ror#2
177
	add	r4,r4,r9			@ E+=X[i]
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	eor	r10,r10,r3,ror#2		@ F_00_19(B,C,D)
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	str	r9,[r14,#-4]!
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	add	r4,r4,r10			@ E+=F_00_19(B,C,D)
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#if __ARM_ARCH__<7
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	ldrb	r10,[r1,#2]
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	ldrb	r9,[r1,#3]
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	ldrb	r11,[r1,#1]
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	add	r3,r8,r3,ror#2			@ E+=K_00_19
186
	ldrb	r12,[r1],#4
187
	orr	r9,r9,r10,lsl#8
188
	eor	r10,r6,r7			@ F_xx_xx
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	orr	r9,r9,r11,lsl#16
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	add	r3,r3,r4,ror#27			@ E+=ROR(A,27)
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	orr	r9,r9,r12,lsl#24
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#else
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	ldr	r9,[r1],#4			@ handles unaligned
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	add	r3,r8,r3,ror#2			@ E+=K_00_19
195
	eor	r10,r6,r7			@ F_xx_xx
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	add	r3,r3,r4,ror#27			@ E+=ROR(A,27)
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#ifdef __ARMEL__
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	rev	r9,r9				@ byte swap
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#endif
200
#endif
201
	and	r10,r5,r10,ror#2
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	add	r3,r3,r9			@ E+=X[i]
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	eor	r10,r10,r7,ror#2		@ F_00_19(B,C,D)
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	str	r9,[r14,#-4]!
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	add	r3,r3,r10			@ E+=F_00_19(B,C,D)
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	cmp	r14,sp
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	bne	.L_00_15		@ [((11+4)*5+2)*3]
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	sub	sp,sp,#25*4
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#if __ARM_ARCH__<7
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	ldrb	r10,[r1,#2]
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	ldrb	r9,[r1,#3]
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	ldrb	r11,[r1,#1]
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	add	r7,r8,r7,ror#2			@ E+=K_00_19
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	ldrb	r12,[r1],#4
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	orr	r9,r9,r10,lsl#8
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	eor	r10,r5,r6			@ F_xx_xx
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	orr	r9,r9,r11,lsl#16
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	add	r7,r7,r3,ror#27			@ E+=ROR(A,27)
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	orr	r9,r9,r12,lsl#24
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#else
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	ldr	r9,[r1],#4			@ handles unaligned
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	add	r7,r8,r7,ror#2			@ E+=K_00_19
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	eor	r10,r5,r6			@ F_xx_xx
224
	add	r7,r7,r3,ror#27			@ E+=ROR(A,27)
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#ifdef __ARMEL__
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	rev	r9,r9				@ byte swap
227
#endif
228
#endif
229
	and	r10,r4,r10,ror#2
230
	add	r7,r7,r9			@ E+=X[i]
231
	eor	r10,r10,r6,ror#2		@ F_00_19(B,C,D)
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	str	r9,[r14,#-4]!
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	add	r7,r7,r10			@ E+=F_00_19(B,C,D)
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	ldr	r9,[r14,#15*4]
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	ldr	r10,[r14,#13*4]
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	ldr	r11,[r14,#7*4]
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	add	r6,r8,r6,ror#2			@ E+=K_xx_xx
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	ldr	r12,[r14,#2*4]
239
	eor	r9,r9,r10
240
	eor	r11,r11,r12			@ 1 cycle stall
241
	eor	r10,r4,r5			@ F_xx_xx
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	mov	r9,r9,ror#31
243
	add	r6,r6,r7,ror#27			@ E+=ROR(A,27)
244
	eor	r9,r9,r11,ror#31
245
	str	r9,[r14,#-4]!
246
	and r10,r3,r10,ror#2					@ F_xx_xx
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						@ F_xx_xx
248
	add	r6,r6,r9			@ E+=X[i]
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	eor	r10,r10,r5,ror#2		@ F_00_19(B,C,D)
250
	add	r6,r6,r10			@ E+=F_00_19(B,C,D)
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	ldr	r9,[r14,#15*4]
252
	ldr	r10,[r14,#13*4]
253
	ldr	r11,[r14,#7*4]
254
	add	r5,r8,r5,ror#2			@ E+=K_xx_xx
255
	ldr	r12,[r14,#2*4]
256
	eor	r9,r9,r10
257
	eor	r11,r11,r12			@ 1 cycle stall
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	eor	r10,r3,r4			@ F_xx_xx
259
	mov	r9,r9,ror#31
260
	add	r5,r5,r6,ror#27			@ E+=ROR(A,27)
261
	eor	r9,r9,r11,ror#31
262
	str	r9,[r14,#-4]!
263
	and r10,r7,r10,ror#2					@ F_xx_xx
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						@ F_xx_xx
265
	add	r5,r5,r9			@ E+=X[i]
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	eor	r10,r10,r4,ror#2		@ F_00_19(B,C,D)
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	add	r5,r5,r10			@ E+=F_00_19(B,C,D)
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	ldr	r9,[r14,#15*4]
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	ldr	r10,[r14,#13*4]
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	ldr	r11,[r14,#7*4]
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	add	r4,r8,r4,ror#2			@ E+=K_xx_xx
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	ldr	r12,[r14,#2*4]
273
	eor	r9,r9,r10
274
	eor	r11,r11,r12			@ 1 cycle stall
275
	eor	r10,r7,r3			@ F_xx_xx
276
	mov	r9,r9,ror#31
277
	add	r4,r4,r5,ror#27			@ E+=ROR(A,27)
278
	eor	r9,r9,r11,ror#31
279
	str	r9,[r14,#-4]!
280
	and r10,r6,r10,ror#2					@ F_xx_xx
281
						@ F_xx_xx
282
	add	r4,r4,r9			@ E+=X[i]
283
	eor	r10,r10,r3,ror#2		@ F_00_19(B,C,D)
284
	add	r4,r4,r10			@ E+=F_00_19(B,C,D)
285
	ldr	r9,[r14,#15*4]
286
	ldr	r10,[r14,#13*4]
287
	ldr	r11,[r14,#7*4]
288
	add	r3,r8,r3,ror#2			@ E+=K_xx_xx
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	ldr	r12,[r14,#2*4]
290
	eor	r9,r9,r10
291
	eor	r11,r11,r12			@ 1 cycle stall
292
	eor	r10,r6,r7			@ F_xx_xx
293
	mov	r9,r9,ror#31
294
	add	r3,r3,r4,ror#27			@ E+=ROR(A,27)
295
	eor	r9,r9,r11,ror#31
296
	str	r9,[r14,#-4]!
297
	and r10,r5,r10,ror#2					@ F_xx_xx
298
						@ F_xx_xx
299
	add	r3,r3,r9			@ E+=X[i]
300
	eor	r10,r10,r7,ror#2		@ F_00_19(B,C,D)
301
	add	r3,r3,r10			@ E+=F_00_19(B,C,D)
302

303
	ldr	r8,.LK_20_39		@ [+15+16*4]
304
	cmn	sp,#0			@ [+3], clear carry to denote 20_39
305
.L_20_39_or_60_79:
306
	ldr	r9,[r14,#15*4]
307
	ldr	r10,[r14,#13*4]
308
	ldr	r11,[r14,#7*4]
309
	add	r7,r8,r7,ror#2			@ E+=K_xx_xx
310
	ldr	r12,[r14,#2*4]
311
	eor	r9,r9,r10
312
	eor	r11,r11,r12			@ 1 cycle stall
313
	eor	r10,r5,r6			@ F_xx_xx
314
	mov	r9,r9,ror#31
315
	add	r7,r7,r3,ror#27			@ E+=ROR(A,27)
316
	eor	r9,r9,r11,ror#31
317
	str	r9,[r14,#-4]!
318
	eor r10,r4,r10,ror#2					@ F_xx_xx
319
						@ F_xx_xx
320
	add	r7,r7,r9			@ E+=X[i]
321
	add	r7,r7,r10			@ E+=F_20_39(B,C,D)
322
	ldr	r9,[r14,#15*4]
323
	ldr	r10,[r14,#13*4]
324
	ldr	r11,[r14,#7*4]
325
	add	r6,r8,r6,ror#2			@ E+=K_xx_xx
326
	ldr	r12,[r14,#2*4]
327
	eor	r9,r9,r10
328
	eor	r11,r11,r12			@ 1 cycle stall
329
	eor	r10,r4,r5			@ F_xx_xx
330
	mov	r9,r9,ror#31
331
	add	r6,r6,r7,ror#27			@ E+=ROR(A,27)
332
	eor	r9,r9,r11,ror#31
333
	str	r9,[r14,#-4]!
334
	eor r10,r3,r10,ror#2					@ F_xx_xx
335
						@ F_xx_xx
336
	add	r6,r6,r9			@ E+=X[i]
337
	add	r6,r6,r10			@ E+=F_20_39(B,C,D)
338
	ldr	r9,[r14,#15*4]
339
	ldr	r10,[r14,#13*4]
340
	ldr	r11,[r14,#7*4]
341
	add	r5,r8,r5,ror#2			@ E+=K_xx_xx
342
	ldr	r12,[r14,#2*4]
343
	eor	r9,r9,r10
344
	eor	r11,r11,r12			@ 1 cycle stall
345
	eor	r10,r3,r4			@ F_xx_xx
346
	mov	r9,r9,ror#31
347
	add	r5,r5,r6,ror#27			@ E+=ROR(A,27)
348
	eor	r9,r9,r11,ror#31
349
	str	r9,[r14,#-4]!
350
	eor r10,r7,r10,ror#2					@ F_xx_xx
351
						@ F_xx_xx
352
	add	r5,r5,r9			@ E+=X[i]
353
	add	r5,r5,r10			@ E+=F_20_39(B,C,D)
354
	ldr	r9,[r14,#15*4]
355
	ldr	r10,[r14,#13*4]
356
	ldr	r11,[r14,#7*4]
357
	add	r4,r8,r4,ror#2			@ E+=K_xx_xx
358
	ldr	r12,[r14,#2*4]
359
	eor	r9,r9,r10
360
	eor	r11,r11,r12			@ 1 cycle stall
361
	eor	r10,r7,r3			@ F_xx_xx
362
	mov	r9,r9,ror#31
363
	add	r4,r4,r5,ror#27			@ E+=ROR(A,27)
364
	eor	r9,r9,r11,ror#31
365
	str	r9,[r14,#-4]!
366
	eor r10,r6,r10,ror#2					@ F_xx_xx
367
						@ F_xx_xx
368
	add	r4,r4,r9			@ E+=X[i]
369
	add	r4,r4,r10			@ E+=F_20_39(B,C,D)
370
	ldr	r9,[r14,#15*4]
371
	ldr	r10,[r14,#13*4]
372
	ldr	r11,[r14,#7*4]
373
	add	r3,r8,r3,ror#2			@ E+=K_xx_xx
374
	ldr	r12,[r14,#2*4]
375
	eor	r9,r9,r10
376
	eor	r11,r11,r12			@ 1 cycle stall
377
	eor	r10,r6,r7			@ F_xx_xx
378
	mov	r9,r9,ror#31
379
	add	r3,r3,r4,ror#27			@ E+=ROR(A,27)
380
	eor	r9,r9,r11,ror#31
381
	str	r9,[r14,#-4]!
382
	eor r10,r5,r10,ror#2					@ F_xx_xx
383
						@ F_xx_xx
384
	add	r3,r3,r9			@ E+=X[i]
385
	add	r3,r3,r10			@ E+=F_20_39(B,C,D)
386
 ARM(	teq	r14,sp		)	@ preserve carry
387
 THUMB(	mov	r11,sp		)
388
 THUMB(	teq	r14,r11		)	@ preserve carry
389
	bne	.L_20_39_or_60_79	@ [+((12+3)*5+2)*4]
390
	bcs	.L_done			@ [+((12+3)*5+2)*4], spare 300 bytes
391

392
	ldr	r8,.LK_40_59
393
	sub	sp,sp,#20*4		@ [+2]
394
.L_40_59:
395
	ldr	r9,[r14,#15*4]
396
	ldr	r10,[r14,#13*4]
397
	ldr	r11,[r14,#7*4]
398
	add	r7,r8,r7,ror#2			@ E+=K_xx_xx
399
	ldr	r12,[r14,#2*4]
400
	eor	r9,r9,r10
401
	eor	r11,r11,r12			@ 1 cycle stall
402
	eor	r10,r5,r6			@ F_xx_xx
403
	mov	r9,r9,ror#31
404
	add	r7,r7,r3,ror#27			@ E+=ROR(A,27)
405
	eor	r9,r9,r11,ror#31
406
	str	r9,[r14,#-4]!
407
	and r10,r4,r10,ror#2					@ F_xx_xx
408
	and r11,r5,r6					@ F_xx_xx
409
	add	r7,r7,r9			@ E+=X[i]
410
	add	r7,r7,r10			@ E+=F_40_59(B,C,D)
411
	add	r7,r7,r11,ror#2
412
	ldr	r9,[r14,#15*4]
413
	ldr	r10,[r14,#13*4]
414
	ldr	r11,[r14,#7*4]
415
	add	r6,r8,r6,ror#2			@ E+=K_xx_xx
416
	ldr	r12,[r14,#2*4]
417
	eor	r9,r9,r10
418
	eor	r11,r11,r12			@ 1 cycle stall
419
	eor	r10,r4,r5			@ F_xx_xx
420
	mov	r9,r9,ror#31
421
	add	r6,r6,r7,ror#27			@ E+=ROR(A,27)
422
	eor	r9,r9,r11,ror#31
423
	str	r9,[r14,#-4]!
424
	and r10,r3,r10,ror#2					@ F_xx_xx
425
	and r11,r4,r5					@ F_xx_xx
426
	add	r6,r6,r9			@ E+=X[i]
427
	add	r6,r6,r10			@ E+=F_40_59(B,C,D)
428
	add	r6,r6,r11,ror#2
429
	ldr	r9,[r14,#15*4]
430
	ldr	r10,[r14,#13*4]
431
	ldr	r11,[r14,#7*4]
432
	add	r5,r8,r5,ror#2			@ E+=K_xx_xx
433
	ldr	r12,[r14,#2*4]
434
	eor	r9,r9,r10
435
	eor	r11,r11,r12			@ 1 cycle stall
436
	eor	r10,r3,r4			@ F_xx_xx
437
	mov	r9,r9,ror#31
438
	add	r5,r5,r6,ror#27			@ E+=ROR(A,27)
439
	eor	r9,r9,r11,ror#31
440
	str	r9,[r14,#-4]!
441
	and r10,r7,r10,ror#2					@ F_xx_xx
442
	and r11,r3,r4					@ F_xx_xx
443
	add	r5,r5,r9			@ E+=X[i]
444
	add	r5,r5,r10			@ E+=F_40_59(B,C,D)
445
	add	r5,r5,r11,ror#2
446
	ldr	r9,[r14,#15*4]
447
	ldr	r10,[r14,#13*4]
448
	ldr	r11,[r14,#7*4]
449
	add	r4,r8,r4,ror#2			@ E+=K_xx_xx
450
	ldr	r12,[r14,#2*4]
451
	eor	r9,r9,r10
452
	eor	r11,r11,r12			@ 1 cycle stall
453
	eor	r10,r7,r3			@ F_xx_xx
454
	mov	r9,r9,ror#31
455
	add	r4,r4,r5,ror#27			@ E+=ROR(A,27)
456
	eor	r9,r9,r11,ror#31
457
	str	r9,[r14,#-4]!
458
	and r10,r6,r10,ror#2					@ F_xx_xx
459
	and r11,r7,r3					@ F_xx_xx
460
	add	r4,r4,r9			@ E+=X[i]
461
	add	r4,r4,r10			@ E+=F_40_59(B,C,D)
462
	add	r4,r4,r11,ror#2
463
	ldr	r9,[r14,#15*4]
464
	ldr	r10,[r14,#13*4]
465
	ldr	r11,[r14,#7*4]
466
	add	r3,r8,r3,ror#2			@ E+=K_xx_xx
467
	ldr	r12,[r14,#2*4]
468
	eor	r9,r9,r10
469
	eor	r11,r11,r12			@ 1 cycle stall
470
	eor	r10,r6,r7			@ F_xx_xx
471
	mov	r9,r9,ror#31
472
	add	r3,r3,r4,ror#27			@ E+=ROR(A,27)
473
	eor	r9,r9,r11,ror#31
474
	str	r9,[r14,#-4]!
475
	and r10,r5,r10,ror#2					@ F_xx_xx
476
	and r11,r6,r7					@ F_xx_xx
477
	add	r3,r3,r9			@ E+=X[i]
478
	add	r3,r3,r10			@ E+=F_40_59(B,C,D)
479
	add	r3,r3,r11,ror#2
480
	cmp	r14,sp
481
	bne	.L_40_59		@ [+((12+5)*5+2)*4]
482

483
	ldr	r8,.LK_60_79
484
	sub	sp,sp,#20*4
485
	cmp	sp,#0			@ set carry to denote 60_79
486
	b	.L_20_39_or_60_79	@ [+4], spare 300 bytes
487
.L_done:
488
	add	sp,sp,#80*4		@ "deallocate" stack frame
489
	ldmia	r0,{r8,r9,r10,r11,r12}
490
	add	r3,r8,r3
491
	add	r4,r9,r4
492
	add	r5,r10,r5,ror#2
493
	add	r6,r11,r6,ror#2
494
	add	r7,r12,r7,ror#2
495
	stmia	r0,{r3,r4,r5,r6,r7}
496
	teq	r1,r2
497
	bne	.Lloop			@ [+18], total 1307
498

499
	ldmia	sp!,{r4-r12,pc}
500
.align	2
501
.LK_00_19:	.word	0x5a827999
502
.LK_20_39:	.word	0x6ed9eba1
503
.LK_40_59:	.word	0x8f1bbcdc
504
.LK_60_79:	.word	0xca62c1d6
505
ENDPROC(sha1_block_data_order)
506
.asciz	"SHA1 block transform for ARMv4, CRYPTOGAMS by <[email protected]>"
507
.align	2
508

509
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