/* SPDX-License-Identifier: GPL-2.0 */1#ifndef __ASM_ARCH_REGS_AC97_H2#define __ASM_ARCH_REGS_AC97_H34/*5* AC97 Controller registers6*/78#define POCR (0x0000) /* PCM Out Control Register */9#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */10#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */1112#define PICR (0x0004) /* PCM In Control Register */13#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */14#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */1516#define MCCR (0x0008) /* Mic In Control Register */17#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */18#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */1920#define GCR (0x000C) /* Global Control Register */21#ifdef CONFIG_PXA3xx22#define GCR_CLKBPB (1 << 31) /* Internal clock enable */23#endif24#define GCR_nDMAEN (1 << 24) /* non DMA Enable */25#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */26#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */27#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */28#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */29#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */30#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */31#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */32#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */33#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */34#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */3536#define POSR (0x0010) /* PCM Out Status Register */37#define POSR_FIFOE (1 << 4) /* FIFO error */38#define POSR_FSR (1 << 2) /* FIFO Service Request */3940#define PISR (0x0014) /* PCM In Status Register */41#define PISR_FIFOE (1 << 4) /* FIFO error */42#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */43#define PISR_FSR (1 << 2) /* FIFO Service Request */4445#define MCSR (0x0018) /* Mic In Status Register */46#define MCSR_FIFOE (1 << 4) /* FIFO error */47#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */48#define MCSR_FSR (1 << 2) /* FIFO Service Request */4950#define GSR (0x001C) /* Global Status Register */51#define GSR_CDONE (1 << 19) /* Command Done */52#define GSR_SDONE (1 << 18) /* Status Done */53#define GSR_RDCS (1 << 15) /* Read Completion Status */54#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */55#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */56#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */57#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */58#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */59#define GSR_SCR (1 << 9) /* Secondary Codec Ready */60#define GSR_PCR (1 << 8) /* Primary Codec Ready */61#define GSR_MCINT (1 << 7) /* Mic In Interrupt */62#define GSR_POINT (1 << 6) /* PCM Out Interrupt */63#define GSR_PIINT (1 << 5) /* PCM In Interrupt */64#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */65#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */66#define GSR_MIINT (1 << 1) /* Modem In Interrupt */67#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */6869#define CAR (0x0020) /* CODEC Access Register */70#define CAR_CAIP (1 << 0) /* Codec Access In Progress */7172#define PCDR (0x0040) /* PCM FIFO Data Register */73#define MCDR (0x0060) /* Mic-in FIFO Data Register */7475#define MOCR (0x0100) /* Modem Out Control Register */76#define MOCR_FEIE (1 << 3) /* FIFO Error */77#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */7879#define MICR (0x0108) /* Modem In Control Register */80#define MICR_FEIE (1 << 3) /* FIFO Error */81#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */8283#define MOSR (0x0110) /* Modem Out Status Register */84#define MOSR_FIFOE (1 << 4) /* FIFO error */85#define MOSR_FSR (1 << 2) /* FIFO Service Request */8687#define MISR (0x0118) /* Modem In Status Register */88#define MISR_FIFOE (1 << 4) /* FIFO error */89#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */90#define MISR_FSR (1 << 2) /* FIFO Service Request */9192#define MODR (0x0140) /* Modem FIFO Data Register */9394#define PAC_REG_BASE (0x0200) /* Primary Audio Codec */95#define SAC_REG_BASE (0x0300) /* Secondary Audio Codec */96#define PMC_REG_BASE (0x0400) /* Primary Modem Codec */97#define SMC_REG_BASE (0x0500) /* Secondary Modem Codec */9899#endif /* __ASM_ARCH_REGS_AC97_H */100101102