CoCalc -- cs8409-tables.c

GitHub Repository: torvalds/linux
Path: blob/master/sound/hda/codecs/cirrus/cs8409-tables.c
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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 * cs8409-tables.c  --  HD audio codec driver for Cirrus Logic CS8409 HDA bridge chip
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 *
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 * Copyright (C) 2021 Cirrus Logic, Inc. and
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 *                    Cirrus Logic International Semiconductor Ltd.
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 *
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 * Author: Lucas Tanure <[email protected]>
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 */
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#include "cs8409.h"
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/******************************************************************************
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 *                          CS42L42 Specific Data
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 *
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 ******************************************************************************/
17

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static const DECLARE_TLV_DB_SCALE(cs42l42_dac_db_scale, CS42L42_HP_VOL_REAL_MIN * 100, 100, 1);
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static const DECLARE_TLV_DB_SCALE(cs42l42_adc_db_scale, CS42L42_AMIC_VOL_REAL_MIN * 100, 100, 1);
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const struct snd_kcontrol_new cs42l42_dac_volume_mixer = {
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	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
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	.index = 0,
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	.subdevice = (HDA_SUBDEV_AMP_FLAG | HDA_SUBDEV_NID_FLAG),
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	.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ),
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	.info = cs42l42_volume_info,
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	.get = cs42l42_volume_get,
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	.put = cs42l42_volume_put,
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	.tlv = { .p = cs42l42_dac_db_scale },
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	.private_value = HDA_COMPOSE_AMP_VAL_OFS(CS8409_PIN_ASP1_TRANSMITTER_A, 3, CS8409_CODEC0,
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			 HDA_OUTPUT, CS42L42_VOL_DAC) | HDA_AMP_VAL_MIN_MUTE
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};
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const struct snd_kcontrol_new cs42l42_adc_volume_mixer = {
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	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
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	.index = 0,
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	.subdevice = (HDA_SUBDEV_AMP_FLAG | HDA_SUBDEV_NID_FLAG),
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	.access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ),
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	.info = cs42l42_volume_info,
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	.get = cs42l42_volume_get,
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	.put = cs42l42_volume_put,
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	.tlv = { .p = cs42l42_adc_db_scale },
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	.private_value = HDA_COMPOSE_AMP_VAL_OFS(CS8409_PIN_ASP1_RECEIVER_A, 1, CS8409_CODEC0,
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			 HDA_INPUT, CS42L42_VOL_ADC) | HDA_AMP_VAL_MIN_MUTE
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};
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const struct hda_pcm_stream cs42l42_48k_pcm_analog_playback = {
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	.rates = SNDRV_PCM_RATE_48000, /* fixed rate */
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};
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const struct hda_pcm_stream cs42l42_48k_pcm_analog_capture = {
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	.rates = SNDRV_PCM_RATE_48000, /* fixed rate */
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};
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/******************************************************************************
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 *                   BULLSEYE / WARLOCK / CYBORG Specific Arrays
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 *                               CS8409/CS42L42
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 ******************************************************************************/
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const struct hda_verb cs8409_cs42l42_init_verbs[] = {
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	{ CS8409_PIN_AFG, AC_VERB_SET_GPIO_WAKE_MASK, 0x0018 },		/* WAKE from GPIO 3,4 */
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	{ CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_STATE, 0x0001 },	/* Enable VPW processing */
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	{ CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x0002 },	/* Configure GPIO 6,7 */
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	{ CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF,  0x0080 },	/* I2C mode */
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	{ CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x005b },	/* Set I2C bus speed */
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	{ CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF,  0x0200 },	/* 100kHz I2C_STO = 2 */
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	{} /* terminator */
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};
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static const struct hda_pintbl cs8409_cs42l42_pincfgs[] = {
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	{ CS8409_PIN_ASP1_TRANSMITTER_A, 0x042120f0 },	/* ASP-1-TX */
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	{ CS8409_PIN_ASP1_RECEIVER_A, 0x04a12050 },	/* ASP-1-RX */
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	{ CS8409_PIN_ASP2_TRANSMITTER_A, 0x901000f0 },	/* ASP-2-TX */
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	{ CS8409_PIN_DMIC1_IN, 0x90a00090 },		/* DMIC-1 */
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	{} /* terminator */
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};
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static const struct hda_pintbl cs8409_cs42l42_pincfgs_no_dmic[] = {
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	{ CS8409_PIN_ASP1_TRANSMITTER_A, 0x042120f0 },	/* ASP-1-TX */
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	{ CS8409_PIN_ASP1_RECEIVER_A, 0x04a12050 },	/* ASP-1-RX */
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	{ CS8409_PIN_ASP2_TRANSMITTER_A, 0x901000f0 },	/* ASP-2-TX */
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	{} /* terminator */
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};
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/* Vendor specific HW configuration for CS42L42 */
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static const struct cs8409_i2c_param cs42l42_init_reg_seq[] = {
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	{ CS42L42_I2C_TIMEOUT, 0xB0 },
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	{ CS42L42_ADC_CTL, 0x00 },
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	{ 0x1D02, 0x06 },
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	{ CS42L42_ADC_VOLUME, 0x9F },
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	{ CS42L42_OSC_SWITCH, 0x01 },
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	{ CS42L42_MCLK_CTL, 0x02 },
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	{ CS42L42_SRC_CTL, 0x03 },
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	{ CS42L42_MCLK_SRC_SEL, 0x00 },
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	{ CS42L42_ASP_FRM_CFG, 0x13 },
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	{ CS42L42_FSYNC_P_LOWER, 0xFF },
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	{ CS42L42_FSYNC_P_UPPER, 0x00 },
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	{ CS42L42_ASP_CLK_CFG, 0x20 },
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	{ CS42L42_SPDIF_CLK_CFG, 0x0D },
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	{ CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x02 },
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	{ CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
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	{ CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 },
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	{ CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x02 },
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	{ CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
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	{ CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x20 },
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	{ CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x02 },
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	{ CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 },
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	{ CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x80 },
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	{ CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x02 },
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	{ CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 },
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	{ CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0xA0 },
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	{ CS42L42_ASP_RX_DAI0_EN, 0x0C },
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	{ CS42L42_ASP_TX_CH_EN, 0x01 },
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	{ CS42L42_ASP_TX_CH_AP_RES, 0x02 },
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	{ CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
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	{ CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
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	{ CS42L42_ASP_TX_SZ_EN, 0x01 },
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	{ CS42L42_PWR_CTL1, 0x0A },
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	{ CS42L42_PWR_CTL2, 0x84 },
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	{ CS42L42_MIXER_CHA_VOL, 0x3F },
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	{ CS42L42_MIXER_CHB_VOL, 0x3F },
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	{ CS42L42_MIXER_ADC_VOL, 0x3f },
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	{ CS42L42_HP_CTL, 0x0D },
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	{ CS42L42_MIC_DET_CTL1, 0xB6 },
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	{ CS42L42_TIPSENSE_CTL, 0xC2 },
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	{ CS42L42_HS_CLAMP_DISABLE, 0x01 },
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	{ CS42L42_HS_SWITCH_CTL, 0xF3 },
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	{ CS42L42_PWR_CTL3, 0x20 },
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	{ CS42L42_RSENSE_CTL2, 0x00 },
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	{ CS42L42_RSENSE_CTL3, 0x00 },
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	{ CS42L42_TSENSE_CTL, 0x80 },
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	{ CS42L42_HS_BIAS_CTL, 0xC0 },
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	{ CS42L42_PWR_CTL1, 0x02, 10000 },
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	{ CS42L42_ADC_OVFL_INT_MASK, 0xff },
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	{ CS42L42_MIXER_INT_MASK, 0xff },
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	{ CS42L42_SRC_INT_MASK, 0xff },
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	{ CS42L42_ASP_RX_INT_MASK, 0xff },
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	{ CS42L42_ASP_TX_INT_MASK, 0xff },
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	{ CS42L42_CODEC_INT_MASK, 0xff },
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	{ CS42L42_SRCPL_INT_MASK, 0xff },
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	{ CS42L42_VPMON_INT_MASK, 0xff },
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	{ CS42L42_PLL_LOCK_INT_MASK, 0xff },
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	{ CS42L42_TSRS_PLUG_INT_MASK, 0xff },
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	{ CS42L42_DET_INT1_MASK, 0xff },
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	{ CS42L42_DET_INT2_MASK, 0xff },
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};
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/* Vendor specific hw configuration for CS8409 */
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const struct cs8409_cir_param cs8409_cs42l42_hw_cfg[] = {
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	/* +PLL1/2_EN, +I2C_EN */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0xb008 },
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	/* ASP1/2_EN=0, ASP1_STP=1 */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0002 },
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	/* ASP1/2_BUS_IDLE=10, +GPIO_I2C */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG3, 0x0a80 },
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	/* ASP1.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */
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	{ CS8409_PIN_VENDOR_WIDGET, ASP1_A_TX_CTRL1, 0x0800 },
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	/* ASP1.A: TX.RAP=0, TX.RSZ=24 bits, TX.RCS=32 */
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	{ CS8409_PIN_VENDOR_WIDGET, ASP1_A_TX_CTRL2, 0x0820 },
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	/* ASP2.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */
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	{ CS8409_PIN_VENDOR_WIDGET, ASP2_A_TX_CTRL1, 0x0800 },
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	/* ASP2.A: TX.RAP=1, TX.RSZ=24 bits, TX.RCS=0 */
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	{ CS8409_PIN_VENDOR_WIDGET, ASP2_A_TX_CTRL2, 0x2800 },
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	/* ASP1.A: RX.LAP=0, RX.LSZ=24 bits, RX.LCS=0 */
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	{ CS8409_PIN_VENDOR_WIDGET, ASP1_A_RX_CTRL1, 0x0800 },
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	/* ASP1.A: RX.RAP=0, RX.RSZ=24 bits, RX.RCS=0 */
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	{ CS8409_PIN_VENDOR_WIDGET, ASP1_A_RX_CTRL2, 0x0800 },
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	/* ASP1: LCHI = 00h */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL1, 0x8000 },
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	/* ASP1: MC/SC_SRCSEL=PLL1, LCPR=FFh */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL2, 0x28ff },
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	/* ASP1: MCEN=0, FSD=011, SCPOL_IN/OUT=0, SCDIV=1:4 */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL3, 0x0062 },
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	/* ASP2: LCHI=1Fh */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_ASP2_CLK_CTRL1, 0x801f },
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	/* ASP2: MC/SC_SRCSEL=PLL1, LCPR=3Fh */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_ASP2_CLK_CTRL2, 0x283f },
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	/* ASP2: 5050=1, MCEN=0, FSD=010, SCPOL_IN/OUT=1, SCDIV=1:16 */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_ASP2_CLK_CTRL3, 0x805c },
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	/* DMIC1_MO=10b, DMIC1/2_SR=1 */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_DMIC_CFG, 0x0023 },
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	/* ASP1/2_BEEP=0 */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_BEEP_CFG, 0x0000 },
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	/* ASP1/2_EN=1, ASP1_STP=1 */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0062 },
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	/* -PLL2_EN */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0x9008 },
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	/* TX2.A: pre-scale att.=0 dB */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PRE_SCALE_ATTN2, 0x0000 },
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	/* ASP1/2_xxx_EN=1, ASP1/2_MCLK_EN=0, DMIC1_SCL_EN=1 */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PAD_CFG_SLW_RATE_CTRL, 0xfc03 },
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	/* test mode on */
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	{ CS8409_PIN_VENDOR_WIDGET, 0xc0, 0x9999 },
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	/* GPIO hysteresis = 30 us */
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	{ CS8409_PIN_VENDOR_WIDGET, 0xc5, 0x0000 },
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	/* test mode off */
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	{ CS8409_PIN_VENDOR_WIDGET, 0xc0, 0x0000 },
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	{} /* Terminator */
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};
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const struct cs8409_cir_param cs8409_cs42l42_bullseye_atn[] = {
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	/* EQ_SEL=1, EQ1/2_EN=0 */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_CTRL1, 0x4000 },
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	/* +EQ_ACC */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0x4000 },
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	/* +EQ2_EN */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_CTRL1, 0x4010 },
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	/* EQ_DATA_HI=0x0647 */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x0647 },
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	/* +EQ_WRT, +EQ_ACC, EQ_ADR=0, EQ_DATA_LO=0x67 */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc0c7 },
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	/* EQ_DATA_HI=0x0647 */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x0647 },
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	/* +EQ_WRT, +EQ_ACC, EQ_ADR=1, EQ_DATA_LO=0x67 */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc1c7 },
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	/* EQ_DATA_HI=0xf370 */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xf370 },
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	/* +EQ_WRT, +EQ_ACC, EQ_ADR=2, EQ_DATA_LO=0x71 */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc271 },
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	/* EQ_DATA_HI=0x1ef8 */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1ef8 },
223
	/* +EQ_WRT, +EQ_ACC, EQ_ADR=3, EQ_DATA_LO=0x48 */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc348 },
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	/* EQ_DATA_HI=0xc110 */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xc110 },
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	/* +EQ_WRT, +EQ_ACC, EQ_ADR=4, EQ_DATA_LO=0x5a */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc45a },
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	/* EQ_DATA_HI=0x1f29 */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1f29 },
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	/* +EQ_WRT, +EQ_ACC, EQ_ADR=5, EQ_DATA_LO=0x74 */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc574 },
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	/* EQ_DATA_HI=0x1d7a */
234
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1d7a },
235
	/* +EQ_WRT, +EQ_ACC, EQ_ADR=6, EQ_DATA_LO=0x53 */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc653 },
237
	/* EQ_DATA_HI=0xc38c */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xc38c },
239
	/* +EQ_WRT, +EQ_ACC, EQ_ADR=7, EQ_DATA_LO=0x14 */
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	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc714 },
241
	/* EQ_DATA_HI=0x1ca3 */
242
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1ca3 },
243
	/* +EQ_WRT, +EQ_ACC, EQ_ADR=8, EQ_DATA_LO=0xc7 */
244
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc8c7 },
245
	/* EQ_DATA_HI=0xc38c */
246
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xc38c },
247
	/* +EQ_WRT, +EQ_ACC, EQ_ADR=9, EQ_DATA_LO=0x14 */
248
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc914 },
249
	/* -EQ_ACC, -EQ_WRT */
250
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0x0000 },
251
	{} /* Terminator */
252
};
253

254
struct sub_codec cs8409_cs42l42_codec = {
255
	.addr = CS42L42_I2C_ADDR,
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	.reset_gpio = CS8409_CS42L42_RESET,
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	.irq_mask = CS8409_CS42L42_INT,
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	.init_seq = cs42l42_init_reg_seq,
259
	.init_seq_num = ARRAY_SIZE(cs42l42_init_reg_seq),
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	.hp_jack_in = 0,
261
	.mic_jack_in = 0,
262
	.paged = 1,
263
	.suspended = 1,
264
	.no_type_dect = 0,
265
};
266

267
/******************************************************************************
268
 *                          Dolphin Specific Arrays
269
 *                            CS8409/ 2 X CS42L42
270
 ******************************************************************************/
271

272
const struct hda_verb dolphin_init_verbs[] = {
273
	{ 0x01, AC_VERB_SET_GPIO_WAKE_MASK, DOLPHIN_WAKE }, /* WAKE from GPIO 0,4 */
274
	{ CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_STATE, 0x0001 }, /* Enable VPW processing  */
275
	{ CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x0002 }, /* Configure GPIO 6,7 */
276
	{ CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF,  0x0080 }, /* I2C mode */
277
	{ CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x005b }, /* Set I2C bus speed */
278
	{ CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF,  0x0200 }, /* 100kHz I2C_STO = 2 */
279
	{} /* terminator */
280
};
281

282
static const struct hda_pintbl dolphin_pincfgs[] = {
283
	{ 0x24, 0x022210f0 }, /* ASP-1-TX-A */
284
	{ 0x25, 0x010240f0 }, /* ASP-1-TX-B */
285
	{ 0x34, 0x02a21050 }, /* ASP-1-RX */
286
	{} /* terminator */
287
};
288

289
/* Vendor specific HW configuration for CS42L42 */
290
static const struct cs8409_i2c_param dolphin_c0_init_reg_seq[] = {
291
	{ CS42L42_I2C_TIMEOUT, 0xB0 },
292
	{ CS42L42_ADC_CTL, 0x00 },
293
	{ 0x1D02, 0x06 },
294
	{ CS42L42_ADC_VOLUME, 0x9F },
295
	{ CS42L42_OSC_SWITCH, 0x01 },
296
	{ CS42L42_MCLK_CTL, 0x02 },
297
	{ CS42L42_SRC_CTL, 0x03 },
298
	{ CS42L42_MCLK_SRC_SEL, 0x00 },
299
	{ CS42L42_ASP_FRM_CFG, 0x13 },
300
	{ CS42L42_FSYNC_P_LOWER, 0xFF },
301
	{ CS42L42_FSYNC_P_UPPER, 0x00 },
302
	{ CS42L42_ASP_CLK_CFG, 0x20 },
303
	{ CS42L42_SPDIF_CLK_CFG, 0x0D },
304
	{ CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x02 },
305
	{ CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
306
	{ CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 },
307
	{ CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x02 },
308
	{ CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
309
	{ CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x20 },
310
	{ CS42L42_ASP_RX_DAI0_EN, 0x0C },
311
	{ CS42L42_ASP_TX_CH_EN, 0x01 },
312
	{ CS42L42_ASP_TX_CH_AP_RES, 0x02 },
313
	{ CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
314
	{ CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
315
	{ CS42L42_ASP_TX_SZ_EN, 0x01 },
316
	{ CS42L42_PWR_CTL1, 0x0A },
317
	{ CS42L42_PWR_CTL2, 0x84 },
318
	{ CS42L42_HP_CTL, 0x0D },
319
	{ CS42L42_MIXER_CHA_VOL, 0x3F },
320
	{ CS42L42_MIXER_CHB_VOL, 0x3F },
321
	{ CS42L42_MIXER_ADC_VOL, 0x3f },
322
	{ CS42L42_MIC_DET_CTL1, 0xB6 },
323
	{ CS42L42_TIPSENSE_CTL, 0xC2 },
324
	{ CS42L42_HS_CLAMP_DISABLE, 0x01 },
325
	{ CS42L42_HS_SWITCH_CTL, 0xF3 },
326
	{ CS42L42_PWR_CTL3, 0x20 },
327
	{ CS42L42_RSENSE_CTL2, 0x00 },
328
	{ CS42L42_RSENSE_CTL3, 0x00 },
329
	{ CS42L42_TSENSE_CTL, 0x80 },
330
	{ CS42L42_HS_BIAS_CTL, 0xC0 },
331
	{ CS42L42_PWR_CTL1, 0x02, 10000 },
332
	{ CS42L42_ADC_OVFL_INT_MASK, 0xff },
333
	{ CS42L42_MIXER_INT_MASK, 0xff },
334
	{ CS42L42_SRC_INT_MASK, 0xff },
335
	{ CS42L42_ASP_RX_INT_MASK, 0xff },
336
	{ CS42L42_ASP_TX_INT_MASK, 0xff },
337
	{ CS42L42_CODEC_INT_MASK, 0xff },
338
	{ CS42L42_SRCPL_INT_MASK, 0xff },
339
	{ CS42L42_VPMON_INT_MASK, 0xff },
340
	{ CS42L42_PLL_LOCK_INT_MASK, 0xff },
341
	{ CS42L42_TSRS_PLUG_INT_MASK, 0xff },
342
	{ CS42L42_DET_INT1_MASK, 0xff },
343
	{ CS42L42_DET_INT2_MASK, 0xff }
344
};
345

346
static const struct cs8409_i2c_param dolphin_c1_init_reg_seq[] = {
347
	{ CS42L42_I2C_TIMEOUT, 0xB0 },
348
	{ CS42L42_ADC_CTL, 0x00 },
349
	{ 0x1D02, 0x06 },
350
	{ CS42L42_ADC_VOLUME, 0x9F },
351
	{ CS42L42_OSC_SWITCH, 0x01 },
352
	{ CS42L42_MCLK_CTL, 0x02 },
353
	{ CS42L42_SRC_CTL, 0x03 },
354
	{ CS42L42_MCLK_SRC_SEL, 0x00 },
355
	{ CS42L42_ASP_FRM_CFG, 0x13 },
356
	{ CS42L42_FSYNC_P_LOWER, 0xFF },
357
	{ CS42L42_FSYNC_P_UPPER, 0x00 },
358
	{ CS42L42_ASP_CLK_CFG, 0x20 },
359
	{ CS42L42_SPDIF_CLK_CFG, 0x0D },
360
	{ CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x02 },
361
	{ CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
362
	{ CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x80 },
363
	{ CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x02 },
364
	{ CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
365
	{ CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0xA0 },
366
	{ CS42L42_ASP_RX_DAI0_EN, 0x0C },
367
	{ CS42L42_ASP_TX_CH_EN, 0x00 },
368
	{ CS42L42_ASP_TX_CH_AP_RES, 0x02 },
369
	{ CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
370
	{ CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
371
	{ CS42L42_ASP_TX_SZ_EN, 0x00 },
372
	{ CS42L42_PWR_CTL1, 0x0E },
373
	{ CS42L42_PWR_CTL2, 0x84 },
374
	{ CS42L42_HP_CTL, 0x0D },
375
	{ CS42L42_MIXER_CHA_VOL, 0x3F },
376
	{ CS42L42_MIXER_CHB_VOL, 0x3F },
377
	{ CS42L42_MIXER_ADC_VOL, 0x3f },
378
	{ CS42L42_MIC_DET_CTL1, 0xB6 },
379
	{ CS42L42_TIPSENSE_CTL, 0xC2 },
380
	{ CS42L42_HS_CLAMP_DISABLE, 0x01 },
381
	{ CS42L42_HS_SWITCH_CTL, 0xF3 },
382
	{ CS42L42_PWR_CTL3, 0x20 },
383
	{ CS42L42_RSENSE_CTL2, 0x00 },
384
	{ CS42L42_RSENSE_CTL3, 0x00 },
385
	{ CS42L42_TSENSE_CTL, 0x80 },
386
	{ CS42L42_HS_BIAS_CTL, 0xC0 },
387
	{ CS42L42_PWR_CTL1, 0x06, 10000 },
388
	{ CS42L42_ADC_OVFL_INT_MASK, 0xff },
389
	{ CS42L42_MIXER_INT_MASK, 0xff },
390
	{ CS42L42_SRC_INT_MASK, 0xff },
391
	{ CS42L42_ASP_RX_INT_MASK, 0xff },
392
	{ CS42L42_ASP_TX_INT_MASK, 0xff },
393
	{ CS42L42_CODEC_INT_MASK, 0xff },
394
	{ CS42L42_SRCPL_INT_MASK, 0xff },
395
	{ CS42L42_VPMON_INT_MASK, 0xff },
396
	{ CS42L42_PLL_LOCK_INT_MASK, 0xff },
397
	{ CS42L42_TSRS_PLUG_INT_MASK, 0xff },
398
	{ CS42L42_DET_INT1_MASK, 0xff },
399
	{ CS42L42_DET_INT2_MASK, 0xff }
400
};
401

402
/* Vendor specific hw configuration for CS8409 */
403
const struct cs8409_cir_param dolphin_hw_cfg[] = {
404
	/* +PLL1/2_EN, +I2C_EN */
405
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0xb008 },
406
	/* ASP1_EN=0, ASP1_STP=1 */
407
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0002 },
408
	/* ASP1/2_BUS_IDLE=10, +GPIO_I2C */
409
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG3, 0x0a80 },
410
	/* ASP1.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */
411
	{ CS8409_PIN_VENDOR_WIDGET, ASP1_A_TX_CTRL1, 0x0800 },
412
	/* ASP1.A: TX.RAP=0, TX.RSZ=24 bits, TX.RCS=32 */
413
	{ CS8409_PIN_VENDOR_WIDGET, ASP1_A_TX_CTRL2, 0x0820 },
414
	/* ASP1.B: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=128 */
415
	{ CS8409_PIN_VENDOR_WIDGET, ASP1_B_TX_CTRL1, 0x0880 },
416
	/* ASP1.B: TX.RAP=0, TX.RSZ=24 bits, TX.RCS=160 */
417
	{ CS8409_PIN_VENDOR_WIDGET, ASP1_B_TX_CTRL2, 0x08a0 },
418
	/* ASP1.A: RX.LAP=0, RX.LSZ=24 bits, RX.LCS=0 */
419
	{ CS8409_PIN_VENDOR_WIDGET, ASP1_A_RX_CTRL1, 0x0800 },
420
	/* ASP1.A: RX.RAP=0, RX.RSZ=24 bits, RX.RCS=0 */
421
	{ CS8409_PIN_VENDOR_WIDGET, ASP1_A_RX_CTRL2, 0x0800 },
422
	/* ASP1: LCHI = 00h */
423
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL1, 0x8000 },
424
	/* ASP1: MC/SC_SRCSEL=PLL1, LCPR=FFh */
425
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL2, 0x28ff },
426
	/* ASP1: MCEN=0, FSD=011, SCPOL_IN/OUT=0, SCDIV=1:4 */
427
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL3, 0x0062 },
428
	/* ASP1/2_BEEP=0 */
429
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_BEEP_CFG, 0x0000 },
430
	/* ASP1_EN=1, ASP1_STP=1 */
431
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0022 },
432
	/* -PLL2_EN */
433
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0x9008 },
434
	/* ASP1_xxx_EN=1, ASP1_MCLK_EN=0 */
435
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PAD_CFG_SLW_RATE_CTRL, 0x5400 },
436
	/* test mode on */
437
	{ CS8409_PIN_VENDOR_WIDGET, 0xc0, 0x9999 },
438
	/* GPIO hysteresis = 30 us */
439
	{ CS8409_PIN_VENDOR_WIDGET, 0xc5, 0x0000 },
440
	/* test mode off */
441
	{ CS8409_PIN_VENDOR_WIDGET, 0xc0, 0x0000 },
442
	{} /* Terminator */
443
};
444

445
struct sub_codec dolphin_cs42l42_0 = {
446
	.addr = DOLPHIN_C0_I2C_ADDR,
447
	.reset_gpio = DOLPHIN_C0_RESET,
448
	.irq_mask = DOLPHIN_C0_INT,
449
	.init_seq = dolphin_c0_init_reg_seq,
450
	.init_seq_num = ARRAY_SIZE(dolphin_c0_init_reg_seq),
451
	.hp_jack_in = 0,
452
	.mic_jack_in = 0,
453
	.paged = 1,
454
	.suspended = 1,
455
	.no_type_dect = 0,
456
};
457

458
struct sub_codec dolphin_cs42l42_1 = {
459
	.addr = DOLPHIN_C1_I2C_ADDR,
460
	.reset_gpio = DOLPHIN_C1_RESET,
461
	.irq_mask = DOLPHIN_C1_INT,
462
	.init_seq = dolphin_c1_init_reg_seq,
463
	.init_seq_num = ARRAY_SIZE(dolphin_c1_init_reg_seq),
464
	.hp_jack_in = 0,
465
	.mic_jack_in = 0,
466
	.paged = 1,
467
	.suspended = 1,
468
	.no_type_dect = 1,
469
};
470

471
/******************************************************************************
472
 *                          CDB35L56-FOUR-HD Specific Arrays
473
 ******************************************************************************/
474
const struct hda_verb cs8409_cdb35l56_four_init_verbs[] = {
475
	{ CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_STATE, 0x0001 },	/* Enable VPW processing */
476
	{} /* terminator */
477
};
478

479
static const struct hda_pintbl cs8409_cdb35l56_four_pincfgs[] = {
480
	/* 0xPPLLLLLLDDDDTTTTCCCCMMMMAAAASSSS
481
	 * P = PCON:	AC_JACK_PORT_*
482
	 * L = LOC:	AC_JACK_LOC_*
483
	 * D = DD:	device type AC_JACK_*
484
	 * T = CTYP:	AC_JACK_CONN_*
485
	 * C = COL:	AC_JACK_COLOR_*
486
	 * M = MISC:	?
487
	 * A = DA:	AC_DEFCFG_DEF_ASSOC
488
	 * S = SEQ:	Sequence number in DA group
489
	 */
490
	{ CS8409_PIN_ASP2_TRANSMITTER_A, 0x901000f0 },	/* ASP-2-TX */
491
	/* "Mic" */
492
	{ CS8409_PIN_ASP2_RECEIVER_A, 0x04a12050 },	/* ASP-2-RX */
493
	{} /* terminator */
494
};
495

496
const struct cs8409_cir_param cs8409_cdb35l56_four_hw_cfg[] = {
497
	/* +PLL1/2_EN, +I2C_EN */
498
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0xb008 },
499
	/* ASP1/2_EN=0, ASP1_STP=1 */
500
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0002 },
501
	/* ASP1/2_BUS_IDLE=10, +GPIO_I2C */
502
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG3, 0x0a80 },
503
	/* ASP2.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */
504
	{ CS8409_PIN_VENDOR_WIDGET, ASP2_A_TX_CTRL1, 0x0800 },
505
	/* ASP2.A: TX.RAP=1, TX.RSZ=24 bits, TX.RCS=0 */
506
	{ CS8409_PIN_VENDOR_WIDGET, ASP2_A_TX_CTRL2, 0x2800 },
507
	/* ASP2.A: RX.LAP=0, RX.LSZ=24 bits, RX.LCS=0 */
508
	{ CS8409_PIN_VENDOR_WIDGET, ASP2_A_RX_CTRL1, 0x0800 },
509
	/* ASP2.A: RX.RAP=1, RX.RSZ=24 bits, RX.RCS=0 */
510
	{ CS8409_PIN_VENDOR_WIDGET, ASP2_A_RX_CTRL2, 0x2800 },
511
	/* ASP1: LCHI = 00h */
512
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL1, 0x8000 },
513
	/* ASP1: MC/SC_SRCSEL=PLL1, LCPR=FFh */
514
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL2, 0x28ff },
515
	/* ASP1: MCEN=0, FSD=011, SCPOL_IN/OUT=0, SCDIV=1:4 */
516
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL3, 0x0062 },
517
	/* ASP2: LCHI=1Fh */
518
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_ASP2_CLK_CTRL1, 0x801f },
519
	/* ASP2: MC/SC_SRCSEL=PLL1, LCPR=3Fh */
520
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_ASP2_CLK_CTRL2, 0x283f },
521
	/* ASP2: 5050=1, MCEN=0, FSD=010, SCPOL_IN/OUT=1, SCDIV=1:16 */
522
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_ASP2_CLK_CTRL3, 0x805c },
523
	/* ASP1/2_BEEP=0 */
524
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_BEEP_CFG, 0x0000 },
525
	/* ASP1/2_EN=1, ASP1_STP=1 */
526
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0062 },
527
	/* -PLL2_EN */
528
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0x9008 },	/* TX2.A: pre-scale att.=0 dB */
529
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PRE_SCALE_ATTN2, 0x0000 },
530
	/* ASP1/2_xxx_EN=1, ASP1/2_MCLK_EN=0, DMIC1_SCL_EN=1 */
531
	{ CS8409_PIN_VENDOR_WIDGET, CS8409_PAD_CFG_SLW_RATE_CTRL, 0xfc03 },
532
	{} /* Terminator */
533
};
534

535
/******************************************************************************
536
 *                         CS8409 Patch Driver Structs
537
 *                    Arrays Used for all projects using CS8409
538
 ******************************************************************************/
539

540
const struct hda_quirk cs8409_fixup_tbl[] = {
541
	SND_PCI_QUIRK(0x1028, 0x0A11, "Bullseye", CS8409_BULLSEYE),
542
	SND_PCI_QUIRK(0x1028, 0x0A12, "Bullseye", CS8409_BULLSEYE),
543
	SND_PCI_QUIRK(0x1028, 0x0A23, "Bullseye", CS8409_BULLSEYE),
544
	SND_PCI_QUIRK(0x1028, 0x0A24, "Bullseye", CS8409_BULLSEYE),
545
	SND_PCI_QUIRK(0x1028, 0x0A25, "Bullseye", CS8409_BULLSEYE),
546
	SND_PCI_QUIRK(0x1028, 0x0A29, "Bullseye", CS8409_BULLSEYE),
547
	SND_PCI_QUIRK(0x1028, 0x0A2A, "Bullseye", CS8409_BULLSEYE),
548
	SND_PCI_QUIRK(0x1028, 0x0A2B, "Bullseye", CS8409_BULLSEYE),
549
	SND_PCI_QUIRK(0x1028, 0x0A77, "Cyborg", CS8409_CYBORG),
550
	SND_PCI_QUIRK(0x1028, 0x0A78, "Cyborg", CS8409_CYBORG),
551
	SND_PCI_QUIRK(0x1028, 0x0A79, "Cyborg", CS8409_CYBORG),
552
	SND_PCI_QUIRK(0x1028, 0x0A7A, "Cyborg", CS8409_CYBORG),
553
	SND_PCI_QUIRK(0x1028, 0x0A7D, "Cyborg", CS8409_CYBORG),
554
	SND_PCI_QUIRK(0x1028, 0x0A7E, "Cyborg", CS8409_CYBORG),
555
	SND_PCI_QUIRK(0x1028, 0x0A7F, "Cyborg", CS8409_CYBORG),
556
	SND_PCI_QUIRK(0x1028, 0x0A80, "Cyborg", CS8409_CYBORG),
557
	SND_PCI_QUIRK(0x1028, 0x0AB0, "Warlock", CS8409_WARLOCK),
558
	SND_PCI_QUIRK(0x1028, 0x0AB2, "Warlock", CS8409_WARLOCK),
559
	SND_PCI_QUIRK(0x1028, 0x0AB1, "Warlock", CS8409_WARLOCK),
560
	SND_PCI_QUIRK(0x1028, 0x0AB3, "Warlock", CS8409_WARLOCK),
561
	SND_PCI_QUIRK(0x1028, 0x0AB4, "Warlock", CS8409_WARLOCK),
562
	SND_PCI_QUIRK(0x1028, 0x0AB5, "Warlock", CS8409_WARLOCK),
563
	SND_PCI_QUIRK(0x1028, 0x0ACF, "Dolphin", CS8409_DOLPHIN),
564
	SND_PCI_QUIRK(0x1028, 0x0AD0, "Dolphin", CS8409_DOLPHIN),
565
	SND_PCI_QUIRK(0x1028, 0x0AD1, "Dolphin", CS8409_DOLPHIN),
566
	SND_PCI_QUIRK(0x1028, 0x0AD2, "Dolphin", CS8409_DOLPHIN),
567
	SND_PCI_QUIRK(0x1028, 0x0AD3, "Dolphin", CS8409_DOLPHIN),
568
	SND_PCI_QUIRK(0x1028, 0x0AD9, "Warlock", CS8409_WARLOCK),
569
	SND_PCI_QUIRK(0x1028, 0x0ADA, "Warlock", CS8409_WARLOCK),
570
	SND_PCI_QUIRK(0x1028, 0x0ADB, "Warlock", CS8409_WARLOCK),
571
	SND_PCI_QUIRK(0x1028, 0x0ADC, "Warlock", CS8409_WARLOCK),
572
	SND_PCI_QUIRK(0x1028, 0x0ADF, "Cyborg", CS8409_CYBORG),
573
	SND_PCI_QUIRK(0x1028, 0x0AE0, "Cyborg", CS8409_CYBORG),
574
	SND_PCI_QUIRK(0x1028, 0x0AE1, "Cyborg", CS8409_CYBORG),
575
	SND_PCI_QUIRK(0x1028, 0x0AE2, "Cyborg", CS8409_CYBORG),
576
	SND_PCI_QUIRK(0x1028, 0x0AE9, "Cyborg", CS8409_CYBORG),
577
	SND_PCI_QUIRK(0x1028, 0x0AEA, "Cyborg", CS8409_CYBORG),
578
	SND_PCI_QUIRK(0x1028, 0x0AEB, "Cyborg", CS8409_CYBORG),
579
	SND_PCI_QUIRK(0x1028, 0x0AEC, "Cyborg", CS8409_CYBORG),
580
	SND_PCI_QUIRK(0x1028, 0x0AED, "Cyborg", CS8409_CYBORG),
581
	SND_PCI_QUIRK(0x1028, 0x0AEE, "Cyborg", CS8409_CYBORG),
582
	SND_PCI_QUIRK(0x1028, 0x0AEF, "Cyborg", CS8409_CYBORG),
583
	SND_PCI_QUIRK(0x1028, 0x0AF0, "Cyborg", CS8409_CYBORG),
584
	SND_PCI_QUIRK(0x1028, 0x0AF4, "Warlock", CS8409_WARLOCK),
585
	SND_PCI_QUIRK(0x1028, 0x0AF5, "Warlock", CS8409_WARLOCK),
586
	SND_PCI_QUIRK(0x1028, 0x0B92, "Warlock MLK", CS8409_WARLOCK_MLK),
587
	SND_PCI_QUIRK(0x1028, 0x0B93, "Warlock MLK Dual Mic", CS8409_WARLOCK_MLK_DUAL_MIC),
588
	SND_PCI_QUIRK(0x1028, 0x0B94, "Warlock MLK", CS8409_WARLOCK_MLK),
589
	SND_PCI_QUIRK(0x1028, 0x0B95, "Warlock MLK Dual Mic", CS8409_WARLOCK_MLK_DUAL_MIC),
590
	SND_PCI_QUIRK(0x1028, 0x0B96, "Warlock MLK", CS8409_WARLOCK_MLK),
591
	SND_PCI_QUIRK(0x1028, 0x0B97, "Warlock MLK Dual Mic", CS8409_WARLOCK_MLK_DUAL_MIC),
592
	SND_PCI_QUIRK(0x1028, 0x0BA5, "Odin", CS8409_ODIN),
593
	SND_PCI_QUIRK(0x1028, 0x0BA6, "Odin", CS8409_ODIN),
594
	SND_PCI_QUIRK(0x1028, 0x0BA8, "Odin", CS8409_ODIN),
595
	SND_PCI_QUIRK(0x1028, 0x0BAA, "Odin", CS8409_ODIN),
596
	SND_PCI_QUIRK(0x1028, 0x0BAE, "Odin", CS8409_ODIN),
597
	SND_PCI_QUIRK(0x1028, 0x0BB2, "Warlock MLK", CS8409_WARLOCK_MLK),
598
	SND_PCI_QUIRK(0x1028, 0x0BB3, "Warlock MLK", CS8409_WARLOCK_MLK),
599
	SND_PCI_QUIRK(0x1028, 0x0BB4, "Warlock MLK", CS8409_WARLOCK_MLK),
600
	SND_PCI_QUIRK(0x1028, 0x0BB5, "Warlock N3 15 TGL-U Nuvoton EC", CS8409_WARLOCK),
601
	SND_PCI_QUIRK(0x1028, 0x0BB6, "Warlock V3 15 TGL-U Nuvoton EC", CS8409_WARLOCK),
602
	SND_PCI_QUIRK(0x1028, 0x0BB8, "Warlock MLK", CS8409_WARLOCK_MLK),
603
	SND_PCI_QUIRK(0x1028, 0x0BB9, "Warlock MLK Dual Mic", CS8409_WARLOCK_MLK_DUAL_MIC),
604
	SND_PCI_QUIRK(0x1028, 0x0BBA, "Warlock MLK", CS8409_WARLOCK_MLK),
605
	SND_PCI_QUIRK(0x1028, 0x0BBB, "Warlock MLK Dual Mic", CS8409_WARLOCK_MLK_DUAL_MIC),
606
	SND_PCI_QUIRK(0x1028, 0x0BBC, "Warlock MLK", CS8409_WARLOCK_MLK),
607
	SND_PCI_QUIRK(0x1028, 0x0BBD, "Warlock MLK Dual Mic", CS8409_WARLOCK_MLK_DUAL_MIC),
608
	SND_PCI_QUIRK(0x1028, 0x0BD4, "Dolphin", CS8409_DOLPHIN),
609
	SND_PCI_QUIRK(0x1028, 0x0BD5, "Dolphin", CS8409_DOLPHIN),
610
	SND_PCI_QUIRK(0x1028, 0x0BD6, "Dolphin", CS8409_DOLPHIN),
611
	SND_PCI_QUIRK(0x1028, 0x0BD7, "Dolphin", CS8409_DOLPHIN),
612
	SND_PCI_QUIRK(0x1028, 0x0BD8, "Dolphin", CS8409_DOLPHIN),
613
	SND_PCI_QUIRK(0x1028, 0x0C43, "Dolphin", CS8409_DOLPHIN),
614
	SND_PCI_QUIRK(0x1028, 0x0C50, "Dolphin", CS8409_DOLPHIN),
615
	SND_PCI_QUIRK(0x1028, 0x0C51, "Dolphin", CS8409_DOLPHIN),
616
	SND_PCI_QUIRK(0x1028, 0x0C52, "Dolphin", CS8409_DOLPHIN),
617
	SND_PCI_QUIRK(0x1028, 0x0C73, "Dolphin", CS8409_DOLPHIN),
618
	SND_PCI_QUIRK(0x1028, 0x0C75, "Dolphin", CS8409_DOLPHIN),
619
	SND_PCI_QUIRK(0x1028, 0x0C7D, "Dolphin", CS8409_DOLPHIN),
620
	SND_PCI_QUIRK(0x1028, 0x0C7F, "Dolphin", CS8409_DOLPHIN),
621
	{} /* terminator */
622
};
623

624
const struct hda_model_fixup cs8409_models[] = {
625
	{ .id = CS8409_BULLSEYE, .name = "bullseye" },
626
	{ .id = CS8409_WARLOCK, .name = "warlock" },
627
	{ .id = CS8409_WARLOCK_MLK, .name = "warlock mlk" },
628
	{ .id = CS8409_WARLOCK_MLK_DUAL_MIC, .name = "warlock mlk dual mic" },
629
	{ .id = CS8409_CYBORG, .name = "cyborg" },
630
	{ .id = CS8409_DOLPHIN, .name = "dolphin" },
631
	{ .id = CS8409_ODIN, .name = "odin" },
632
	{ .id = CS8409_CDB35L56_FOUR_HD, .name = "CDB35L56-FOUR-HD" },
633
	{}
634
};
635

636
const struct hda_fixup cs8409_fixups[] = {
637
	[CS8409_BULLSEYE] = {
638
		.type = HDA_FIXUP_PINS,
639
		.v.pins = cs8409_cs42l42_pincfgs,
640
		.chained = true,
641
		.chain_id = CS8409_FIXUPS,
642
	},
643
	[CS8409_WARLOCK] = {
644
		.type = HDA_FIXUP_PINS,
645
		.v.pins = cs8409_cs42l42_pincfgs,
646
		.chained = true,
647
		.chain_id = CS8409_FIXUPS,
648
	},
649
	[CS8409_WARLOCK_MLK] = {
650
		.type = HDA_FIXUP_PINS,
651
		.v.pins = cs8409_cs42l42_pincfgs,
652
		.chained = true,
653
		.chain_id = CS8409_FIXUPS,
654
	},
655
	[CS8409_WARLOCK_MLK_DUAL_MIC] = {
656
		.type = HDA_FIXUP_PINS,
657
		.v.pins = cs8409_cs42l42_pincfgs,
658
		.chained = true,
659
		.chain_id = CS8409_FIXUPS,
660
	},
661
	[CS8409_CYBORG] = {
662
		.type = HDA_FIXUP_PINS,
663
		.v.pins = cs8409_cs42l42_pincfgs,
664
		.chained = true,
665
		.chain_id = CS8409_FIXUPS,
666
	},
667
	[CS8409_FIXUPS] = {
668
		.type = HDA_FIXUP_FUNC,
669
		.v.func = cs8409_cs42l42_fixups,
670
	},
671
	[CS8409_DOLPHIN] = {
672
		.type = HDA_FIXUP_PINS,
673
		.v.pins = dolphin_pincfgs,
674
		.chained = true,
675
		.chain_id = CS8409_DOLPHIN_FIXUPS,
676
	},
677
	[CS8409_DOLPHIN_FIXUPS] = {
678
		.type = HDA_FIXUP_FUNC,
679
		.v.func = dolphin_fixups,
680
	},
681
	[CS8409_ODIN] = {
682
		.type = HDA_FIXUP_PINS,
683
		.v.pins = cs8409_cs42l42_pincfgs_no_dmic,
684
		.chained = true,
685
		.chain_id = CS8409_FIXUPS,
686
	},
687
	[CS8409_CDB35L56_FOUR_HD] = {
688
		.type = HDA_FIXUP_PINS,
689
		.v.pins = cs8409_cdb35l56_four_pincfgs,
690
		.chained = true,
691
		.chain_id = CS8409_CDB35L56_FOUR_HD_FIXUP,
692
	},
693
	[CS8409_CDB35L56_FOUR_HD_FIXUP] = {
694
		.type = HDA_FIXUP_FUNC,
695
		.v.func = cs8409_cdb35l56_four_autodet_fixup,
696
	},
697
};
698

699
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