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GitHub Repository: torvalds/linux
 Path: blob/master/sound/hda/codecs/cirrus/cs8409.h
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1
/* SPDX-License-Identifier: GPL-2.0-or-later */

2
/*

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 * HD audio codec driver for Cirrus Logic CS8409 HDA bridge chip

4
 *

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 * Copyright (C) 2021 Cirrus Logic, Inc. and

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 *                    Cirrus Logic International Semiconductor Ltd.

7
 */

8


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#ifndef __CS8409_PATCH_H

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#define __CS8409_PATCH_H

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#include <linux/pci.h>

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#include <sound/tlv.h>

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#include <linux/workqueue.h>

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#include <sound/cs42l42.h>

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#include <sound/hda_codec.h>

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#include "hda_local.h"

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#include "hda_auto_parser.h"

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#include "hda_jack.h"

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#include "../generic.h"

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/* CS8409 Specific Definitions */

23


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enum cs8409_pins {

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	CS8409_PIN_ROOT,

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	CS8409_PIN_AFG,

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	CS8409_PIN_ASP1_OUT_A,

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	CS8409_PIN_ASP1_OUT_B,

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	CS8409_PIN_ASP1_OUT_C,

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	CS8409_PIN_ASP1_OUT_D,

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	CS8409_PIN_ASP1_OUT_E,

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	CS8409_PIN_ASP1_OUT_F,

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	CS8409_PIN_ASP1_OUT_G,

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	CS8409_PIN_ASP1_OUT_H,

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	CS8409_PIN_ASP2_OUT_A,

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	CS8409_PIN_ASP2_OUT_B,

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	CS8409_PIN_ASP2_OUT_C,

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	CS8409_PIN_ASP2_OUT_D,

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	CS8409_PIN_ASP2_OUT_E,

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	CS8409_PIN_ASP2_OUT_F,

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	CS8409_PIN_ASP2_OUT_G,

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	CS8409_PIN_ASP2_OUT_H,

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	CS8409_PIN_ASP1_IN_A,

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	CS8409_PIN_ASP1_IN_B,

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	CS8409_PIN_ASP1_IN_C,

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	CS8409_PIN_ASP1_IN_D,

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	CS8409_PIN_ASP1_IN_E,

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	CS8409_PIN_ASP1_IN_F,

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	CS8409_PIN_ASP1_IN_G,

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	CS8409_PIN_ASP1_IN_H,

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	CS8409_PIN_ASP2_IN_A,

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	CS8409_PIN_ASP2_IN_B,

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	CS8409_PIN_ASP2_IN_C,

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	CS8409_PIN_ASP2_IN_D,

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	CS8409_PIN_ASP2_IN_E,

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	CS8409_PIN_ASP2_IN_F,

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	CS8409_PIN_ASP2_IN_G,

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	CS8409_PIN_ASP2_IN_H,

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	CS8409_PIN_DMIC1,

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	CS8409_PIN_DMIC2,

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	CS8409_PIN_ASP1_TRANSMITTER_A,

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	CS8409_PIN_ASP1_TRANSMITTER_B,

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	CS8409_PIN_ASP1_TRANSMITTER_C,

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	CS8409_PIN_ASP1_TRANSMITTER_D,

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	CS8409_PIN_ASP1_TRANSMITTER_E,

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	CS8409_PIN_ASP1_TRANSMITTER_F,

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	CS8409_PIN_ASP1_TRANSMITTER_G,

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	CS8409_PIN_ASP1_TRANSMITTER_H,

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	CS8409_PIN_ASP2_TRANSMITTER_A,

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	CS8409_PIN_ASP2_TRANSMITTER_B,

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	CS8409_PIN_ASP2_TRANSMITTER_C,

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	CS8409_PIN_ASP2_TRANSMITTER_D,

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	CS8409_PIN_ASP2_TRANSMITTER_E,

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	CS8409_PIN_ASP2_TRANSMITTER_F,

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	CS8409_PIN_ASP2_TRANSMITTER_G,

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	CS8409_PIN_ASP2_TRANSMITTER_H,

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	CS8409_PIN_ASP1_RECEIVER_A,

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	CS8409_PIN_ASP1_RECEIVER_B,

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	CS8409_PIN_ASP1_RECEIVER_C,

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	CS8409_PIN_ASP1_RECEIVER_D,

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	CS8409_PIN_ASP1_RECEIVER_E,

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	CS8409_PIN_ASP1_RECEIVER_F,

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	CS8409_PIN_ASP1_RECEIVER_G,

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	CS8409_PIN_ASP1_RECEIVER_H,

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	CS8409_PIN_ASP2_RECEIVER_A,

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	CS8409_PIN_ASP2_RECEIVER_B,

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	CS8409_PIN_ASP2_RECEIVER_C,

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	CS8409_PIN_ASP2_RECEIVER_D,

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	CS8409_PIN_ASP2_RECEIVER_E,

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	CS8409_PIN_ASP2_RECEIVER_F,

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	CS8409_PIN_ASP2_RECEIVER_G,

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	CS8409_PIN_ASP2_RECEIVER_H,

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	CS8409_PIN_DMIC1_IN,

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	CS8409_PIN_DMIC2_IN,

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	CS8409_PIN_BEEP_GEN,

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	CS8409_PIN_VENDOR_WIDGET

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};

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enum cs8409_coefficient_index_registers {

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	CS8409_DEV_CFG1,

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	CS8409_DEV_CFG2,

102
	CS8409_DEV_CFG3,

103
	CS8409_ASP1_CLK_CTRL1,

104
	CS8409_ASP1_CLK_CTRL2,

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	CS8409_ASP1_CLK_CTRL3,

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	CS8409_ASP2_CLK_CTRL1,

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	CS8409_ASP2_CLK_CTRL2,

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	CS8409_ASP2_CLK_CTRL3,

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	CS8409_DMIC_CFG,

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	CS8409_BEEP_CFG,

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	ASP1_RX_NULL_INS_RMV,

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	ASP1_Rx_RATE1,

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	ASP1_Rx_RATE2,

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	ASP1_Tx_NULL_INS_RMV,

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	ASP1_Tx_RATE1,

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	ASP1_Tx_RATE2,

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	ASP2_Rx_NULL_INS_RMV,

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	ASP2_Rx_RATE1,

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	ASP2_Rx_RATE2,

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	ASP2_Tx_NULL_INS_RMV,

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	ASP2_Tx_RATE1,

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	ASP2_Tx_RATE2,

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	ASP1_SYNC_CTRL,

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	ASP2_SYNC_CTRL,

125
	ASP1_A_TX_CTRL1,

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	ASP1_A_TX_CTRL2,

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	ASP1_B_TX_CTRL1,

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	ASP1_B_TX_CTRL2,

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	ASP1_C_TX_CTRL1,

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	ASP1_C_TX_CTRL2,

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	ASP1_D_TX_CTRL1,

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	ASP1_D_TX_CTRL2,

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	ASP1_E_TX_CTRL1,

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	ASP1_E_TX_CTRL2,

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	ASP1_F_TX_CTRL1,

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	ASP1_F_TX_CTRL2,

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	ASP1_G_TX_CTRL1,

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	ASP1_G_TX_CTRL2,

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	ASP1_H_TX_CTRL1,

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	ASP1_H_TX_CTRL2,

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	ASP2_A_TX_CTRL1,

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	ASP2_A_TX_CTRL2,

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	ASP2_B_TX_CTRL1,

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	ASP2_B_TX_CTRL2,

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	ASP2_C_TX_CTRL1,

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	ASP2_C_TX_CTRL2,

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	ASP2_D_TX_CTRL1,

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	ASP2_D_TX_CTRL2,

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	ASP2_E_TX_CTRL1,

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	ASP2_E_TX_CTRL2,

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	ASP2_F_TX_CTRL1,

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	ASP2_F_TX_CTRL2,

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	ASP2_G_TX_CTRL1,

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	ASP2_G_TX_CTRL2,

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	ASP2_H_TX_CTRL1,

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	ASP2_H_TX_CTRL2,

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	ASP1_A_RX_CTRL1,

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	ASP1_A_RX_CTRL2,

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	ASP1_B_RX_CTRL1,

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	ASP1_B_RX_CTRL2,

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	ASP1_C_RX_CTRL1,

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	ASP1_C_RX_CTRL2,

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	ASP1_D_RX_CTRL1,

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	ASP1_D_RX_CTRL2,

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	ASP1_E_RX_CTRL1,

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	ASP1_E_RX_CTRL2,

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	ASP1_F_RX_CTRL1,

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	ASP1_F_RX_CTRL2,

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	ASP1_G_RX_CTRL1,

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	ASP1_G_RX_CTRL2,

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	ASP1_H_RX_CTRL1,

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	ASP1_H_RX_CTRL2,

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	ASP2_A_RX_CTRL1,

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	ASP2_A_RX_CTRL2,

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	ASP2_B_RX_CTRL1,

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	ASP2_B_RX_CTRL2,

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	ASP2_C_RX_CTRL1,

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	ASP2_C_RX_CTRL2,

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	ASP2_D_RX_CTRL1,

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	ASP2_D_RX_CTRL2,

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	ASP2_E_RX_CTRL1,

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	ASP2_E_RX_CTRL2,

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	ASP2_F_RX_CTRL1,

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	ASP2_F_RX_CTRL2,

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	ASP2_G_RX_CTRL1,

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	ASP2_G_RX_CTRL2,

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	ASP2_H_RX_CTRL1,

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	ASP2_H_RX_CTRL2,

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	CS8409_I2C_ADDR,

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	CS8409_I2C_DATA,

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	CS8409_I2C_CTRL,

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	CS8409_I2C_STS,

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	CS8409_I2C_QWRITE,

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	CS8409_I2C_QREAD,

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	CS8409_SPI_CTRL,

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	CS8409_SPI_TX_DATA,

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	CS8409_SPI_RX_DATA,

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	CS8409_SPI_STS,

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	CS8409_PFE_COEF_W1, /* Parametric filter engine coefficient write 1*/

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	CS8409_PFE_COEF_W2,

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	CS8409_PFE_CTRL1,

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	CS8409_PFE_CTRL2,

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	CS8409_PRE_SCALE_ATTN1,

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	CS8409_PRE_SCALE_ATTN2,

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	CS8409_PFE_COEF_MON1, /* Parametric filter engine coefficient monitor 1*/

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	CS8409_PFE_COEF_MON2,

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	CS8409_ASP1_INTRN_STS,

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	CS8409_ASP2_INTRN_STS,

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	CS8409_ASP1_RX_SCLK_COUNT,

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	CS8409_ASP1_TX_SCLK_COUNT,

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	CS8409_ASP2_RX_SCLK_COUNT,

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	CS8409_ASP2_TX_SCLK_COUNT,

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	CS8409_ASP_UNS_RESP_MASK,

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	CS8409_LOOPBACK_CTRL = 0x80,

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	CS8409_PAD_CFG_SLW_RATE_CTRL = 0x82, /* Pad Config and Slew Rate Control (CIR = 0x0082) */

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};

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/* CS42L42 Specific Definitions */

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#define CS8409_MAX_CODECS			8

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#define CS42L42_VOLUMES				(4U)

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#define CS42L42_HP_VOL_REAL_MIN			(-63)

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#define CS42L42_HP_VOL_REAL_MAX			(0)

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#define CS42L42_AMIC_VOL_REAL_MIN		(-97)

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#define CS42L42_AMIC_VOL_REAL_MAX		(12)

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#define CS42L42_REG_AMIC_VOL_MASK		(0x00FF)

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#define CS42L42_HSTYPE_MASK			(0x03)

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#define CS42L42_I2C_TIMEOUT_US			(20000)

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#define CS42L42_I2C_SLEEP_US			(2000)

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#define CS42L42_PDN_TIMEOUT_US			(250000)

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#define CS42L42_PDN_SLEEP_US			(2000)

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#define CS42L42_ANA_MUTE_AB			(0x0C)

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#define CS42L42_FULL_SCALE_VOL_MASK		(2)

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#define CS42L42_FULL_SCALE_VOL_0DB		(0)

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#define CS42L42_FULL_SCALE_VOL_MINUS6DB		(1)

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/* Dell BULLSEYE / WARLOCK / CYBORG Specific Definitions */

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#define CS42L42_I2C_ADDR			(0x48 << 1)

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#define CS8409_CS42L42_RESET			GENMASK(5, 5) /* CS8409_GPIO5 */

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#define CS8409_CS42L42_INT			GENMASK(4, 4) /* CS8409_GPIO4 */

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#define CS8409_CYBORG_SPEAKER_PDN		GENMASK(2, 2) /* CS8409_GPIO2 */

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#define CS8409_WARLOCK_SPEAKER_PDN		GENMASK(1, 1) /* CS8409_GPIO1 */

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#define CS8409_CS42L42_HP_PIN_NID		CS8409_PIN_ASP1_TRANSMITTER_A

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#define CS8409_CS42L42_SPK_PIN_NID		CS8409_PIN_ASP2_TRANSMITTER_A

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#define CS8409_CS42L42_AMIC_PIN_NID		CS8409_PIN_ASP1_RECEIVER_A

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#define CS8409_CS42L42_DMIC_PIN_NID		CS8409_PIN_DMIC1_IN

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#define CS8409_CS42L42_DMIC_ADC_PIN_NID		CS8409_PIN_DMIC1

249


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/* Dolphin */

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#define DOLPHIN_C0_I2C_ADDR			(0x48 << 1)

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#define DOLPHIN_C1_I2C_ADDR			(0x49 << 1)

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#define DOLPHIN_HP_PIN_NID			CS8409_PIN_ASP1_TRANSMITTER_A

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#define DOLPHIN_LO_PIN_NID			CS8409_PIN_ASP1_TRANSMITTER_B

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#define DOLPHIN_AMIC_PIN_NID			CS8409_PIN_ASP1_RECEIVER_A

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#define DOLPHIN_C0_INT				GENMASK(4, 4)

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#define DOLPHIN_C1_INT				GENMASK(0, 0)

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#define DOLPHIN_C0_RESET			GENMASK(5, 5)

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#define DOLPHIN_C1_RESET			GENMASK(1, 1)

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#define DOLPHIN_WAKE				(DOLPHIN_C0_INT | DOLPHIN_C1_INT)

263


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enum {

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	CS8409_BULLSEYE,

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	CS8409_WARLOCK,

267
	CS8409_WARLOCK_MLK,

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	CS8409_WARLOCK_MLK_DUAL_MIC,

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	CS8409_CYBORG,

270
	CS8409_FIXUPS,

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	CS8409_DOLPHIN,

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	CS8409_DOLPHIN_FIXUPS,

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	CS8409_ODIN,

274
};

275


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enum {

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	CS8409_CODEC0,

278
	CS8409_CODEC1

279
};

280


281
enum {

282
	CS42L42_VOL_ADC,

283
	CS42L42_VOL_DAC,

284
};

285


286
#define CS42L42_ADC_VOL_OFFSET			(CS42L42_VOL_ADC)

287
#define CS42L42_DAC_CH0_VOL_OFFSET		(CS42L42_VOL_DAC)

288
#define CS42L42_DAC_CH1_VOL_OFFSET		(CS42L42_VOL_DAC + 1)

289


290
struct cs8409_i2c_param {

291
	unsigned int addr;

292
	unsigned int value;

293
	unsigned int delay;

294
};

295


296
struct cs8409_cir_param {

297
	unsigned int nid;

298
	unsigned int cir;

299
	unsigned int coeff;

300
};

301


302
struct sub_codec {

303
	struct hda_codec *codec;

304
	unsigned int addr;

305
	unsigned int reset_gpio;

306
	unsigned int irq_mask;

307
	const struct cs8409_i2c_param *init_seq;

308
	unsigned int init_seq_num;

309


310
	unsigned int hp_jack_in:1;

311
	unsigned int mic_jack_in:1;

312
	unsigned int suspended:1;

313
	unsigned int paged:1;

314
	unsigned int last_page;

315
	unsigned int hsbias_hiz;

316
	unsigned int full_scale_vol:1;

317
	unsigned int no_type_dect:1;

318


319
	s8 vol[CS42L42_VOLUMES];

320
};

321


322
struct cs8409_spec {

323
	struct hda_gen_spec gen;

324
	struct hda_codec *codec;

325


326
	struct sub_codec *scodecs[CS8409_MAX_CODECS];

327
	unsigned int num_scodecs;

328


329
	unsigned int gpio_mask;

330
	unsigned int gpio_dir;

331
	unsigned int gpio_data;

332


333
	int speaker_pdn_gpio;

334


335
	struct mutex i2c_mux;

336
	unsigned int i2c_clck_enabled;

337
	unsigned int dev_addr;

338
	struct delayed_work i2c_clk_work;

339


340
	unsigned int playback_started:1;

341
	unsigned int capture_started:1;

342
	unsigned int init_done:1;

343
	unsigned int build_ctrl_done:1;

344


345
	/* verb exec op override */

346
	int (*exec_verb)(struct hdac_device *dev, unsigned int cmd, unsigned int flags,

347
			 unsigned int *res);

348
	/* unsol_event op override */

349
	void (*unsol_event)(struct hda_codec *codec, unsigned int res);

350
};

351


352
extern const struct snd_kcontrol_new cs42l42_dac_volume_mixer;

353
extern const struct snd_kcontrol_new cs42l42_adc_volume_mixer;

354


355
int cs42l42_volume_info(struct snd_kcontrol *kctrl, struct snd_ctl_elem_info *uinfo);

356
int cs42l42_volume_get(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl);

357
int cs42l42_volume_put(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl);

358


359
extern const struct hda_pcm_stream cs42l42_48k_pcm_analog_playback;

360
extern const struct hda_pcm_stream cs42l42_48k_pcm_analog_capture;

361
extern const struct hda_quirk cs8409_fixup_tbl[];

362
extern const struct hda_model_fixup cs8409_models[];

363
extern const struct hda_fixup cs8409_fixups[];

364
extern const struct hda_verb cs8409_cs42l42_init_verbs[];

365
extern const struct cs8409_cir_param cs8409_cs42l42_hw_cfg[];

366
extern const struct cs8409_cir_param cs8409_cs42l42_bullseye_atn[];

367
extern struct sub_codec cs8409_cs42l42_codec;

368


369
extern const struct hda_verb dolphin_init_verbs[];

370
extern const struct cs8409_cir_param dolphin_hw_cfg[];

371
extern struct sub_codec dolphin_cs42l42_0;

372
extern struct sub_codec dolphin_cs42l42_1;

373


374
void cs8409_cs42l42_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action);

375
void dolphin_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action);

376


377
#endif

378


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