CoCalc -- emufx.c

GitHub Repository: torvalds/linux
Path: blob/master/sound/pci/emu10k1/emufx.c
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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 *  Copyright (c) by Jaroslav Kysela <[email protected]>
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 *                   James Courtier-Dutton <[email protected]>
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 *                   Oswald Buddenhagen <[email protected]>
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 *                   Creative Labs, Inc.
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 *
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 *  Routines for effect processor FX8010
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 */
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#include <linux/pci.h>
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#include <linux/capability.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/vmalloc.h>
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#include <linux/init.h>
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#include <linux/mutex.h>
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#include <linux/moduleparam.h>
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#include <linux/nospec.h>
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#include <sound/core.h>
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#include <sound/tlv.h>
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#include <sound/emu10k1.h>
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#if 0		/* for testing purposes - digital out -> capture */
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#define EMU10K1_CAPTURE_DIGITAL_OUT
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#endif
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#if 0		/* for testing purposes - set S/PDIF to AC3 output */
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#define EMU10K1_SET_AC3_IEC958
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#endif
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#if 0		/* for testing purposes - feed the front signal to Center/LFE outputs */
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#define EMU10K1_CENTER_LFE_FROM_FRONT
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#endif
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static bool high_res_gpr_volume;
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module_param(high_res_gpr_volume, bool, 0444);
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MODULE_PARM_DESC(high_res_gpr_volume, "GPR mixer controls use 31-bit range.");
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/*
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 *  Tables
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 */ 
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// Playback channel labels; corresponds with the public FXBUS_* defines.
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// Unlike the tables below, this is not determined by the hardware.
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const char * const snd_emu10k1_fxbus[32] = {
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	/* 0x00 */ "PCM Left",
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	/* 0x01 */ "PCM Right",
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	/* 0x02 */ "PCM Rear Left",
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	/* 0x03 */ "PCM Rear Right",
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	/* 0x04 */ "MIDI Left",
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	/* 0x05 */ "MIDI Right",
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	/* 0x06 */ "PCM Center",
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	/* 0x07 */ "PCM LFE",
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	/* 0x08 */ "PCM Front Left",
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	/* 0x09 */ "PCM Front Right",
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	/* 0x0a */ NULL,
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	/* 0x0b */ NULL,
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	/* 0x0c */ "MIDI Reverb",
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	/* 0x0d */ "MIDI Chorus",
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	/* 0x0e */ "PCM Side Left",
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	/* 0x0f */ "PCM Side Right",
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	/* 0x10 */ NULL,
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	/* 0x11 */ NULL,
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	/* 0x12 */ NULL,
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	/* 0x13 */ NULL,
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	/* 0x14 */ "Passthrough Left",
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	/* 0x15 */ "Passthrough Right",
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	/* 0x16 */ NULL,
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	/* 0x17 */ NULL,
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	/* 0x18 */ NULL,
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	/* 0x19 */ NULL,
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	/* 0x1a */ NULL,
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	/* 0x1b */ NULL,
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	/* 0x1c */ NULL,
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	/* 0x1d */ NULL,
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	/* 0x1e */ NULL,
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	/* 0x1f */ NULL
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};
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// Physical inputs; corresponds with the public EXTIN_* defines.
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const char * const snd_emu10k1_sblive_ins[16] = {
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	/* 0x00 */ "AC97 Left",
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	/* 0x01 */ "AC97 Right",
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	/* 0x02 */ "TTL IEC958 Left",
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	/* 0x03 */ "TTL IEC958 Right",
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	/* 0x04 */ "Zoom Video Left",
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	/* 0x05 */ "Zoom Video Right",
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	/* 0x06 */ "Optical IEC958 Left",
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	/* 0x07 */ "Optical IEC958 Right",
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	/* 0x08 */ "Line/Mic 1 Left",
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	/* 0x09 */ "Line/Mic 1 Right",
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	/* 0x0a */ "Coaxial IEC958 Left",
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	/* 0x0b */ "Coaxial IEC958 Right",
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	/* 0x0c */ "Line/Mic 2 Left",
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	/* 0x0d */ "Line/Mic 2 Right",
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	/* 0x0e */ NULL,
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	/* 0x0f */ NULL
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};
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// Physical inputs; corresponds with the public A_EXTIN_* defines.
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const char * const snd_emu10k1_audigy_ins[16] = {
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	/* 0x00 */ "AC97 Left",
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	/* 0x01 */ "AC97 Right",
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	/* 0x02 */ "Audigy CD Left",
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	/* 0x03 */ "Audigy CD Right",
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	/* 0x04 */ "Optical IEC958 Left",
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	/* 0x05 */ "Optical IEC958 Right",
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	/* 0x06 */ NULL,
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	/* 0x07 */ NULL,
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	/* 0x08 */ "Line/Mic 2 Left",
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	/* 0x09 */ "Line/Mic 2 Right",
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	/* 0x0a */ "SPDIF Left",
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	/* 0x0b */ "SPDIF Right",
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	/* 0x0c */ "Aux2 Left",
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	/* 0x0d */ "Aux2 Right",
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	/* 0x0e */ NULL,
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	/* 0x0f */ NULL
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};
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// Physical outputs; corresponds with the public EXTOUT_* defines.
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const char * const snd_emu10k1_sblive_outs[32] = {
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	/* 0x00 */ "AC97 Left",
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	/* 0x01 */ "AC97 Right",
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	/* 0x02 */ "Optical IEC958 Left",
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	/* 0x03 */ "Optical IEC958 Right",
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	/* 0x04 */ "Center",
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	/* 0x05 */ "LFE",
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	/* 0x06 */ "Headphone Left",
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	/* 0x07 */ "Headphone Right",
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	/* 0x08 */ "Surround Left",
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	/* 0x09 */ "Surround Right",
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	/* 0x0a */ "PCM Capture Left",
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	/* 0x0b */ "PCM Capture Right",
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	/* 0x0c */ "MIC Capture",
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	/* 0x0d */ "AC97 Surround Left",
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	/* 0x0e */ "AC97 Surround Right",
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	/* 0x0f */ NULL,
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	// This is actually the FXBUS2 range; SB Live! 5.1 only.
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	/* 0x10 */ NULL,
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	/* 0x11 */ "Analog Center",
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	/* 0x12 */ "Analog LFE",
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	/* 0x13 */ NULL,
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	/* 0x14 */ NULL,
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	/* 0x15 */ NULL,
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	/* 0x16 */ NULL,
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	/* 0x17 */ NULL,
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	/* 0x18 */ NULL,
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	/* 0x19 */ NULL,
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	/* 0x1a */ NULL,
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	/* 0x1b */ NULL,
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	/* 0x1c */ NULL,
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	/* 0x1d */ NULL,
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	/* 0x1e */ NULL,
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	/* 0x1f */ NULL,
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};
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// Physical outputs; corresponds with the public A_EXTOUT_* defines.
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const char * const snd_emu10k1_audigy_outs[32] = {
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	/* 0x00 */ "Digital Front Left",
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	/* 0x01 */ "Digital Front Right",
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	/* 0x02 */ "Digital Center",
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	/* 0x03 */ "Digital LEF",
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	/* 0x04 */ "Headphone Left",
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	/* 0x05 */ "Headphone Right",
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	/* 0x06 */ "Digital Rear Left",
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	/* 0x07 */ "Digital Rear Right",
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	/* 0x08 */ "Front Left",
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	/* 0x09 */ "Front Right",
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	/* 0x0a */ "Center",
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	/* 0x0b */ "LFE",
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	/* 0x0c */ NULL,
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	/* 0x0d */ NULL,
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	/* 0x0e */ "Rear Left",
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	/* 0x0f */ "Rear Right",
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	/* 0x10 */ "AC97 Front Left",
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	/* 0x11 */ "AC97 Front Right",
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	/* 0x12 */ "ADC Capture Left",
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	/* 0x13 */ "ADC Capture Right",
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	/* 0x14 */ NULL,
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	/* 0x15 */ NULL,
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	/* 0x16 */ NULL,
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	/* 0x17 */ NULL,
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	/* 0x18 */ NULL,
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	/* 0x19 */ NULL,
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	/* 0x1a */ NULL,
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	/* 0x1b */ NULL,
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	/* 0x1c */ NULL,
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	/* 0x1d */ NULL,
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	/* 0x1e */ NULL,
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	/* 0x1f */ NULL,
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};
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// On the SB Live! 5.1, FXBUS2[1] and FXBUS2[2] are occupied by EXTOUT_ACENTER
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// and EXTOUT_ALFE, so we can't connect inputs to them for multitrack recording.
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//
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// Since only 14 of the 16 EXTINs are used, this is not a big problem.
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// We route AC97 to FX capture 14 and 15, SPDIF_CD to FX capture 0 and 3,
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// and the rest of the EXTINs to the corresponding FX capture channel.
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// Multitrack recorders will still see the center/LFE output signal
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// on the second and third "input" channel.
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const s8 snd_emu10k1_sblive51_fxbus2_map[16] = {
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	2, -1, -1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 0, 1
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};
205

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static const u32 bass_table[41][5] = {
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	{ 0x3e4f844f, 0x84ed4cc3, 0x3cc69927, 0x7b03553a, 0xc4da8486 },
208
	{ 0x3e69a17a, 0x84c280fb, 0x3cd77cd4, 0x7b2f2a6f, 0xc4b08d1d },
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	{ 0x3e82ff42, 0x849991d5, 0x3ce7466b, 0x7b5917c6, 0xc48863ee },
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	{ 0x3e9bab3c, 0x847267f0, 0x3cf5ffe8, 0x7b813560, 0xc461f22c },
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	{ 0x3eb3b275, 0x844ced29, 0x3d03b295, 0x7ba79a1c, 0xc43d223b },
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	{ 0x3ecb2174, 0x84290c8b, 0x3d106714, 0x7bcc5ba3, 0xc419dfa5 },
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	{ 0x3ee2044b, 0x8406b244, 0x3d1c2561, 0x7bef8e77, 0xc3f8170f },
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	{ 0x3ef86698, 0x83e5cb96, 0x3d26f4d8, 0x7c114600, 0xc3d7b625 },
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	{ 0x3f0e5390, 0x83c646c9, 0x3d30dc39, 0x7c319498, 0xc3b8ab97 },
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	{ 0x3f23d60b, 0x83a81321, 0x3d39e1af, 0x7c508b9c, 0xc39ae704 },
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	{ 0x3f38f884, 0x838b20d2, 0x3d420ad2, 0x7c6e3b75, 0xc37e58f1 },
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	{ 0x3f4dc52c, 0x836f60ef, 0x3d495cab, 0x7c8ab3a6, 0xc362f2be },
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	{ 0x3f6245e8, 0x8354c565, 0x3d4fdbb8, 0x7ca602d6, 0xc348a69b },
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	{ 0x3f76845f, 0x833b40ec, 0x3d558bf0, 0x7cc036df, 0xc32f677c },
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	{ 0x3f8a8a03, 0x8322c6fb, 0x3d5a70c4, 0x7cd95cd7, 0xc317290b },
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	{ 0x3f9e6014, 0x830b4bc3, 0x3d5e8d25, 0x7cf1811a, 0xc2ffdfa5 },
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	{ 0x3fb20fae, 0x82f4c420, 0x3d61e37f, 0x7d08af56, 0xc2e9804a },
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	{ 0x3fc5a1cc, 0x82df2592, 0x3d6475c3, 0x7d1ef294, 0xc2d40096 },
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	{ 0x3fd91f55, 0x82ca6632, 0x3d664564, 0x7d345541, 0xc2bf56b9 },
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	{ 0x3fec9120, 0x82b67cac, 0x3d675356, 0x7d48e138, 0xc2ab796e },
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	{ 0x40000000, 0x82a36037, 0x3d67a012, 0x7d5c9fc9, 0xc2985fee },
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	{ 0x401374c7, 0x8291088a, 0x3d672b93, 0x7d6f99c3, 0xc28601f2 },
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	{ 0x4026f857, 0x827f6dd7, 0x3d65f559, 0x7d81d77c, 0xc27457a3 },
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	{ 0x403a939f, 0x826e88c5, 0x3d63fc63, 0x7d9360d4, 0xc2635996 },
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	{ 0x404e4faf, 0x825e5266, 0x3d613f32, 0x7da43d42, 0xc25300c6 },
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	{ 0x406235ba, 0x824ec434, 0x3d5dbbc3, 0x7db473d7, 0xc243468e },
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	{ 0x40764f1f, 0x823fd80c, 0x3d596f8f, 0x7dc40b44, 0xc23424a2 },
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	{ 0x408aa576, 0x82318824, 0x3d545787, 0x7dd309e2, 0xc2259509 },
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	{ 0x409f4296, 0x8223cf0b, 0x3d4e7012, 0x7de175b5, 0xc2179218 },
236
	{ 0x40b430a0, 0x8216a7a1, 0x3d47b505, 0x7def5475, 0xc20a1670 },
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	{ 0x40c97a0a, 0x820a0d12, 0x3d4021a1, 0x7dfcab8d, 0xc1fd1cf5 },
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	{ 0x40df29a6, 0x81fdfad6, 0x3d37b08d, 0x7e098028, 0xc1f0a0ca },
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	{ 0x40f54ab1, 0x81f26ca9, 0x3d2e5bd1, 0x7e15d72b, 0xc1e49d52 },
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	{ 0x410be8da, 0x81e75e89, 0x3d241cce, 0x7e21b544, 0xc1d90e24 },
241
	{ 0x41231051, 0x81dcccb3, 0x3d18ec37, 0x7e2d1ee6, 0xc1cdef10 },
242
	{ 0x413acdd0, 0x81d2b39e, 0x3d0cc20a, 0x7e38184e, 0xc1c33c13 },
243
	{ 0x41532ea7, 0x81c90ffb, 0x3cff9585, 0x7e42a58b, 0xc1b8f15a },
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	{ 0x416c40cd, 0x81bfdeb2, 0x3cf15d21, 0x7e4cca7c, 0xc1af0b3f },
245
	{ 0x418612ea, 0x81b71cdc, 0x3ce20e85, 0x7e568ad3, 0xc1a58640 },
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	{ 0x41a0b465, 0x81aec7c5, 0x3cd19e7c, 0x7e5fea1e, 0xc19c5f03 },
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	{ 0x41bc3573, 0x81a6dcea, 0x3cc000e9, 0x7e68ebc2, 0xc1939250 }
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};
249

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static const u32 treble_table[41][5] = {
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	{ 0x0125cba9, 0xfed5debd, 0x00599b6c, 0x0d2506da, 0xfa85b354 },
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	{ 0x0142f67e, 0xfeb03163, 0x0066cd0f, 0x0d14c69d, 0xfa914473 },
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	{ 0x016328bd, 0xfe860158, 0x0075b7f2, 0x0d03eb27, 0xfa9d32d2 },
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	{ 0x0186b438, 0xfe56c982, 0x00869234, 0x0cf27048, 0xfaa97fca },
255
	{ 0x01adf358, 0xfe21f5fe, 0x00999842, 0x0ce051c2, 0xfab62ca5 },
256
	{ 0x01d949fa, 0xfde6e287, 0x00af0d8d, 0x0ccd8b4a, 0xfac33aa7 },
257
	{ 0x02092669, 0xfda4d8bf, 0x00c73d4c, 0x0cba1884, 0xfad0ab07 },
258
	{ 0x023e0268, 0xfd5b0e4a, 0x00e27b54, 0x0ca5f509, 0xfade7ef2 },
259
	{ 0x0278645c, 0xfd08a2b0, 0x01012509, 0x0c911c63, 0xfaecb788 },
260
	{ 0x02b8e091, 0xfcac9d1a, 0x0123a262, 0x0c7b8a14, 0xfafb55df },
261
	{ 0x03001a9a, 0xfc45e9ce, 0x014a6709, 0x0c65398f, 0xfb0a5aff },
262
	{ 0x034ec6d7, 0xfbd3576b, 0x0175f397, 0x0c4e2643, 0xfb19c7e4 },
263
	{ 0x03a5ac15, 0xfb5393ee, 0x01a6d6ed, 0x0c364b94, 0xfb299d7c },
264
	{ 0x0405a562, 0xfac52968, 0x01ddafae, 0x0c1da4e2, 0xfb39dca5 },
265
	{ 0x046fa3fe, 0xfa267a66, 0x021b2ddd, 0x0c042d8d, 0xfb4a8631 },
266
	{ 0x04e4b17f, 0xf975be0f, 0x0260149f, 0x0be9e0f2, 0xfb5b9ae0 },
267
	{ 0x0565f220, 0xf8b0fbe5, 0x02ad3c29, 0x0bceba73, 0xfb6d1b60 },
268
	{ 0x05f4a745, 0xf7d60722, 0x030393d4, 0x0bb2b578, 0xfb7f084d },
269
	{ 0x06923236, 0xf6e279bd, 0x03642465, 0x0b95cd75, 0xfb916233 },
270
	{ 0x07401713, 0xf5d3aef9, 0x03d01283, 0x0b77fded, 0xfba42984 },
271
	{ 0x08000000, 0xf4a6bd88, 0x0448a161, 0x0b594278, 0xfbb75e9f },
272
	{ 0x08d3c097, 0xf3587131, 0x04cf35a4, 0x0b3996c9, 0xfbcb01cb },
273
	{ 0x09bd59a2, 0xf1e543f9, 0x05655880, 0x0b18f6b2, 0xfbdf1333 },
274
	{ 0x0abefd0f, 0xf04956ca, 0x060cbb12, 0x0af75e2c, 0xfbf392e8 },
275
	{ 0x0bdb123e, 0xee806984, 0x06c739fe, 0x0ad4c962, 0xfc0880dd },
276
	{ 0x0d143a94, 0xec85d287, 0x0796e150, 0x0ab134b0, 0xfc1ddce5 },
277
	{ 0x0e6d5664, 0xea547598, 0x087df0a0, 0x0a8c9cb6, 0xfc33a6ad },
278
	{ 0x0fe98a2a, 0xe7e6ba35, 0x097edf83, 0x0a66fe5b, 0xfc49ddc2 },
279
	{ 0x118c4421, 0xe536813a, 0x0a9c6248, 0x0a4056d7, 0xfc608185 },
280
	{ 0x1359422e, 0xe23d19eb, 0x0bd96efb, 0x0a18a3bf, 0xfc77912c },
281
	{ 0x1554982b, 0xdef33645, 0x0d3942bd, 0x09efe312, 0xfc8f0bc1 },
282
	{ 0x1782b68a, 0xdb50deb1, 0x0ebf676d, 0x09c6133f, 0xfca6f019 },
283
	{ 0x19e8715d, 0xd74d64fd, 0x106fb999, 0x099b3337, 0xfcbf3cd6 },
284
	{ 0x1c8b07b8, 0xd2df56ab, 0x124e6ec8, 0x096f4274, 0xfcd7f060 },
285
	{ 0x1f702b6d, 0xcdfc6e92, 0x14601c10, 0x0942410b, 0xfcf108e5 },
286
	{ 0x229e0933, 0xc89985cd, 0x16a9bcfa, 0x09142fb5, 0xfd0a8451 },
287
	{ 0x261b5118, 0xc2aa8409, 0x1930bab6, 0x08e50fdc, 0xfd24604d },
288
	{ 0x29ef3f5d, 0xbc224f28, 0x1bfaf396, 0x08b4e3aa, 0xfd3e9a3b },
289
	{ 0x2e21a59b, 0xb4f2ba46, 0x1f0ec2d6, 0x0883ae15, 0xfd592f33 },
290
	{ 0x32baf44b, 0xad0c7429, 0x227308a3, 0x085172eb, 0xfd741bfd },
291
	{ 0x37c4448b, 0xa45ef51d, 0x262f3267, 0x081e36dc, 0xfd8f5d14 }
292
};
293

294
/* dB gain = (float) 20 * log10( float(db_table_value) / 0x8000000 ) */
295
static const u32 db_table[101] = {
296
	0x00000000, 0x01571f82, 0x01674b41, 0x01783a1b, 0x0189f540,
297
	0x019c8651, 0x01aff763, 0x01c45306, 0x01d9a446, 0x01eff6b8,
298
	0x0207567a, 0x021fd03d, 0x0239714c, 0x02544792, 0x027061a1,
299
	0x028dcebb, 0x02ac9edc, 0x02cce2bf, 0x02eeabe8, 0x03120cb0,
300
	0x0337184e, 0x035de2df, 0x03868173, 0x03b10a18, 0x03dd93e9,
301
	0x040c3713, 0x043d0cea, 0x04702ff3, 0x04a5bbf2, 0x04ddcdfb,
302
	0x0518847f, 0x0555ff62, 0x05966005, 0x05d9c95d, 0x06206005,
303
	0x066a4a52, 0x06b7b067, 0x0708bc4c, 0x075d9a01, 0x07b6779d,
304
	0x08138561, 0x0874f5d5, 0x08dafde1, 0x0945d4ed, 0x09b5b4fd,
305
	0x0a2adad1, 0x0aa58605, 0x0b25f936, 0x0bac7a24, 0x0c3951d8,
306
	0x0ccccccc, 0x0d673b17, 0x0e08f093, 0x0eb24510, 0x0f639481,
307
	0x101d3f2d, 0x10dfa9e6, 0x11ab3e3f, 0x12806ac3, 0x135fa333,
308
	0x144960c5, 0x153e2266, 0x163e6cfe, 0x174acbb7, 0x1863d04d,
309
	0x198a1357, 0x1abe349f, 0x1c00db77, 0x1d52b712, 0x1eb47ee6,
310
	0x2026f30f, 0x21aadcb6, 0x23410e7e, 0x24ea64f9, 0x26a7c71d,
311
	0x287a26c4, 0x2a62812c, 0x2c61df84, 0x2e795779, 0x30aa0bcf,
312
	0x32f52cfe, 0x355bf9d8, 0x37dfc033, 0x3a81dda4, 0x3d43c038,
313
	0x4026e73c, 0x432ce40f, 0x46575af8, 0x49a8040f, 0x4d20ac2a,
314
	0x50c335d3, 0x54919a57, 0x588dead1, 0x5cba514a, 0x611911ea,
315
	0x65ac8c2f, 0x6a773c39, 0x6f7bbc23, 0x74bcc56c, 0x7a3d3272,
316
	0x7fffffff,
317
};
318

319
/* EMU10k1/EMU10k2 DSP control db gain */
320
static const DECLARE_TLV_DB_SCALE(snd_emu10k1_db_scale1, -4000, 40, 1);
321
static const DECLARE_TLV_DB_LINEAR(snd_emu10k1_db_linear, TLV_DB_GAIN_MUTE, 0);
322

323
/* EMU10K1 bass/treble db gain */
324
static const DECLARE_TLV_DB_SCALE(snd_emu10k1_bass_treble_db_scale, -1200, 60, 0);
325

326
static const u32 onoff_table[2] = {
327
	0x00000000, 0x00000001
328
};
329

330
/*
331
 *   controls
332
 */
333

334
static int snd_emu10k1_gpr_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
335
{
336
	struct snd_emu10k1_fx8010_ctl *ctl =
337
		(struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
338

339
	if (ctl->min == 0 && ctl->max == 1)
340
		uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
341
	else
342
		uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
343
	uinfo->count = ctl->vcount;
344
	uinfo->value.integer.min = ctl->min;
345
	uinfo->value.integer.max = ctl->max;
346
	return 0;
347
}
348

349
static int snd_emu10k1_gpr_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
350
{
351
	struct snd_emu10k1_fx8010_ctl *ctl =
352
		(struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
353
	unsigned int i;
354
	
355
	for (i = 0; i < ctl->vcount; i++)
356
		ucontrol->value.integer.value[i] = ctl->value[i];
357
	return 0;
358
}
359

360
static int snd_emu10k1_gpr_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
361
{
362
	struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
363
	struct snd_emu10k1_fx8010_ctl *ctl =
364
		(struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
365
	int nval, val;
366
	unsigned int i, j;
367
	int change = 0;
368
	
369
	for (i = 0; i < ctl->vcount; i++) {
370
		nval = ucontrol->value.integer.value[i];
371
		if (nval < ctl->min)
372
			nval = ctl->min;
373
		if (nval > ctl->max)
374
			nval = ctl->max;
375
		if (nval != ctl->value[i])
376
			change = 1;
377
		val = ctl->value[i] = nval;
378
		switch (ctl->translation) {
379
		case EMU10K1_GPR_TRANSLATION_NONE:
380
			snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, val);
381
			break;
382
		case EMU10K1_GPR_TRANSLATION_NEGATE:
383
			snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, ~val);
384
			break;
385
		case EMU10K1_GPR_TRANSLATION_TABLE100:
386
			snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, db_table[val]);
387
			break;
388
		case EMU10K1_GPR_TRANSLATION_NEG_TABLE100:
389
			snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0,
390
					      val == 100 ? 0x80000000 : -(int)db_table[val]);
391
			break;
392
		case EMU10K1_GPR_TRANSLATION_BASS:
393
			if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
394
				change = -EIO;
395
				goto __error;
396
			}
397
			for (j = 0; j < 5; j++)
398
				snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, bass_table[val][j]);
399
			break;
400
		case EMU10K1_GPR_TRANSLATION_TREBLE:
401
			if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
402
				change = -EIO;
403
				goto __error;
404
			}
405
			for (j = 0; j < 5; j++)
406
				snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, treble_table[val][j]);
407
			break;
408
		case EMU10K1_GPR_TRANSLATION_ONOFF:
409
			snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, onoff_table[val]);
410
			break;
411
		}
412
	}
413
      __error:
414
	return change;
415
}
416

417
/*
418
 *   Interrupt handler
419
 */
420

421
static void snd_emu10k1_fx8010_interrupt(struct snd_emu10k1 *emu)
422
{
423
	struct snd_emu10k1_fx8010_irq *irq, *nirq;
424

425
	irq = emu->fx8010.irq_handlers;
426
	while (irq) {
427
		nirq = irq->next;	/* irq ptr can be removed from list */
428
		if (snd_emu10k1_ptr_read(emu, emu->gpr_base + irq->gpr_running, 0) & 0xffff0000) {
429
			if (irq->handler)
430
				irq->handler(emu, irq->private_data);
431
			snd_emu10k1_ptr_write(emu, emu->gpr_base + irq->gpr_running, 0, 1);
432
		}
433
		irq = nirq;
434
	}
435
}
436

437
int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
438
					    snd_fx8010_irq_handler_t *handler,
439
					    unsigned char gpr_running,
440
					    void *private_data,
441
					    struct snd_emu10k1_fx8010_irq *irq)
442
{
443
	unsigned long flags;
444
	
445
	irq->handler = handler;
446
	irq->gpr_running = gpr_running;
447
	irq->private_data = private_data;
448
	irq->next = NULL;
449
	spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
450
	if (emu->fx8010.irq_handlers == NULL) {
451
		emu->fx8010.irq_handlers = irq;
452
		emu->dsp_interrupt = snd_emu10k1_fx8010_interrupt;
453
		snd_emu10k1_intr_enable(emu, INTE_FXDSPENABLE);
454
	} else {
455
		irq->next = emu->fx8010.irq_handlers;
456
		emu->fx8010.irq_handlers = irq;
457
	}
458
	spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
459
	return 0;
460
}
461

462
int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
463
					      struct snd_emu10k1_fx8010_irq *irq)
464
{
465
	struct snd_emu10k1_fx8010_irq *tmp;
466
	unsigned long flags;
467
	
468
	spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
469
	tmp = emu->fx8010.irq_handlers;
470
	if (tmp == irq) {
471
		emu->fx8010.irq_handlers = tmp->next;
472
		if (emu->fx8010.irq_handlers == NULL) {
473
			snd_emu10k1_intr_disable(emu, INTE_FXDSPENABLE);
474
			emu->dsp_interrupt = NULL;
475
		}
476
	} else {
477
		while (tmp && tmp->next != irq)
478
			tmp = tmp->next;
479
		if (tmp)
480
			tmp->next = tmp->next->next;
481
	}
482
	spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
483
	return 0;
484
}
485

486
/*************************************************************************
487
 * EMU10K1 effect manager
488
 *************************************************************************/
489

490
static void snd_emu10k1_write_op(struct snd_emu10k1_fx8010_code *icode,
491
				 unsigned int *ptr,
492
				 u32 op, u32 r, u32 a, u32 x, u32 y)
493
{
494
	u_int32_t *code;
495
	if (snd_BUG_ON(*ptr >= 512))
496
		return;
497
	code = icode->code + (*ptr) * 2;
498
	set_bit(*ptr, icode->code_valid);
499
	code[0] = ((x & 0x3ff) << 10) | (y & 0x3ff);
500
	code[1] = ((op & 0x0f) << 20) | ((r & 0x3ff) << 10) | (a & 0x3ff);
501
	(*ptr)++;
502
}
503

504
#define OP(icode, ptr, op, r, a, x, y) \
505
	snd_emu10k1_write_op(icode, ptr, op, r, a, x, y)
506

507
static void snd_emu10k1_audigy_write_op(struct snd_emu10k1_fx8010_code *icode,
508
					unsigned int *ptr,
509
					u32 op, u32 r, u32 a, u32 x, u32 y)
510
{
511
	u_int32_t *code;
512
	if (snd_BUG_ON(*ptr >= 1024))
513
		return;
514
	code = icode->code + (*ptr) * 2;
515
	set_bit(*ptr, icode->code_valid);
516
	code[0] = ((x & 0x7ff) << 12) | (y & 0x7ff);
517
	code[1] = ((op & 0x0f) << 24) | ((r & 0x7ff) << 12) | (a & 0x7ff);
518
	(*ptr)++;
519
}
520

521
#define A_OP(icode, ptr, op, r, a, x, y) \
522
	snd_emu10k1_audigy_write_op(icode, ptr, op, r, a, x, y)
523

524
static void snd_emu10k1_efx_write(struct snd_emu10k1 *emu, unsigned int pc, unsigned int data)
525
{
526
	pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
527
	snd_emu10k1_ptr_write(emu, pc, 0, data);
528
}
529

530
unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc)
531
{
532
	pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
533
	return snd_emu10k1_ptr_read(emu, pc, 0);
534
}
535

536
static int snd_emu10k1_gpr_poke(struct snd_emu10k1 *emu,
537
				struct snd_emu10k1_fx8010_code *icode,
538
				bool in_kernel)
539
{
540
	int gpr;
541
	u32 val;
542

543
	for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
544
		if (!test_bit(gpr, icode->gpr_valid))
545
			continue;
546
		if (in_kernel)
547
			val = icode->gpr_map[gpr];
548
		else if (get_user(val, (__user u32 *)&icode->gpr_map[gpr]))
549
			return -EFAULT;
550
		snd_emu10k1_ptr_write(emu, emu->gpr_base + gpr, 0, val);
551
	}
552
	return 0;
553
}
554

555
static int snd_emu10k1_gpr_peek(struct snd_emu10k1 *emu,
556
				struct snd_emu10k1_fx8010_code *icode)
557
{
558
	int gpr;
559
	u32 val;
560

561
	for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
562
		set_bit(gpr, icode->gpr_valid);
563
		val = snd_emu10k1_ptr_read(emu, emu->gpr_base + gpr, 0);
564
		if (put_user(val, (__user u32 *)&icode->gpr_map[gpr]))
565
			return -EFAULT;
566
	}
567
	return 0;
568
}
569

570
static int snd_emu10k1_tram_poke(struct snd_emu10k1 *emu,
571
				 struct snd_emu10k1_fx8010_code *icode,
572
				 bool in_kernel)
573
{
574
	int tram;
575
	u32 addr, val;
576

577
	for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
578
		if (!test_bit(tram, icode->tram_valid))
579
			continue;
580
		if (in_kernel) {
581
			val = icode->tram_data_map[tram];
582
			addr = icode->tram_addr_map[tram];
583
		} else {
584
			if (get_user(val, (__user __u32 *)&icode->tram_data_map[tram]) ||
585
			    get_user(addr, (__user __u32 *)&icode->tram_addr_map[tram]))
586
				return -EFAULT;
587
		}
588
		snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + tram, 0, val);
589
		if (!emu->audigy) {
590
			snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr);
591
		} else {
592
			snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr << 12);
593
			snd_emu10k1_ptr_write(emu, A_TANKMEMCTLREGBASE + tram, 0, addr >> 20);
594
		}
595
	}
596
	return 0;
597
}
598

599
static int snd_emu10k1_tram_peek(struct snd_emu10k1 *emu,
600
				 struct snd_emu10k1_fx8010_code *icode)
601
{
602
	int tram;
603
	u32 val, addr;
604

605
	memset(icode->tram_valid, 0, sizeof(icode->tram_valid));
606
	for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
607
		set_bit(tram, icode->tram_valid);
608
		val = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + tram, 0);
609
		if (!emu->audigy) {
610
			addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0);
611
		} else {
612
			addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0) >> 12;
613
			addr |= snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + tram, 0) << 20;
614
		}
615
		if (put_user(val, (__user u32 *)&icode->tram_data_map[tram]) ||
616
		    put_user(addr, (__user u32 *)&icode->tram_addr_map[tram]))
617
			return -EFAULT;
618
	}
619
	return 0;
620
}
621

622
static int snd_emu10k1_code_poke(struct snd_emu10k1 *emu,
623
				 struct snd_emu10k1_fx8010_code *icode,
624
				 bool in_kernel)
625
{
626
	u32 pc, lo, hi;
627

628
	for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
629
		if (!test_bit(pc / 2, icode->code_valid))
630
			continue;
631
		if (in_kernel) {
632
			lo = icode->code[pc + 0];
633
			hi = icode->code[pc + 1];
634
		} else {
635
			if (get_user(lo, (__user u32 *)&icode->code[pc + 0]) ||
636
			    get_user(hi, (__user u32 *)&icode->code[pc + 1]))
637
				return -EFAULT;
638
		}
639
		snd_emu10k1_efx_write(emu, pc + 0, lo);
640
		snd_emu10k1_efx_write(emu, pc + 1, hi);
641
	}
642
	return 0;
643
}
644

645
static int snd_emu10k1_code_peek(struct snd_emu10k1 *emu,
646
				 struct snd_emu10k1_fx8010_code *icode)
647
{
648
	u32 pc;
649

650
	memset(icode->code_valid, 0, sizeof(icode->code_valid));
651
	for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
652
		set_bit(pc / 2, icode->code_valid);
653
		if (put_user(snd_emu10k1_efx_read(emu, pc + 0),
654
			     (__user u32 *)&icode->code[pc + 0]))
655
			return -EFAULT;
656
		if (put_user(snd_emu10k1_efx_read(emu, pc + 1),
657
			     (__user u32 *)&icode->code[pc + 1]))
658
			return -EFAULT;
659
	}
660
	return 0;
661
}
662

663
static struct snd_emu10k1_fx8010_ctl *
664
snd_emu10k1_look_for_ctl(struct snd_emu10k1 *emu,
665
			 struct emu10k1_ctl_elem_id *_id)
666
{
667
	struct snd_ctl_elem_id *id = (struct snd_ctl_elem_id *)_id;
668
	struct snd_emu10k1_fx8010_ctl *ctl;
669
	struct snd_kcontrol *kcontrol;
670

671
	list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
672
		kcontrol = ctl->kcontrol;
673
		if (kcontrol->id.iface == id->iface &&
674
		    kcontrol->id.index == id->index &&
675
		    !strcmp(kcontrol->id.name, id->name))
676
			return ctl;
677
	}
678
	return NULL;
679
}
680

681
#define MAX_TLV_SIZE	256
682

683
static unsigned int *copy_tlv(const unsigned int __user *_tlv, bool in_kernel)
684
{
685
	unsigned int data[2];
686
	unsigned int *tlv;
687

688
	if (!_tlv)
689
		return NULL;
690
	if (in_kernel)
691
		memcpy(data, (__force void *)_tlv, sizeof(data));
692
	else if (copy_from_user(data, _tlv, sizeof(data)))
693
		return NULL;
694
	if (data[1] >= MAX_TLV_SIZE)
695
		return NULL;
696
	tlv = kmalloc(data[1] + sizeof(data), GFP_KERNEL);
697
	if (!tlv)
698
		return NULL;
699
	memcpy(tlv, data, sizeof(data));
700
	if (in_kernel) {
701
		memcpy(tlv + 2, (__force void *)(_tlv + 2),  data[1]);
702
	} else if (copy_from_user(tlv + 2, _tlv + 2, data[1])) {
703
		kfree(tlv);
704
		return NULL;
705
	}
706
	return tlv;
707
}
708

709
static int copy_gctl(struct snd_emu10k1 *emu,
710
		     struct snd_emu10k1_fx8010_control_gpr *dst,
711
		     struct snd_emu10k1_fx8010_control_gpr *src,
712
		     int idx, bool in_kernel)
713
{
714
	struct snd_emu10k1_fx8010_control_gpr __user *_src;
715
	struct snd_emu10k1_fx8010_control_old_gpr *octl;
716
	struct snd_emu10k1_fx8010_control_old_gpr __user *_octl;
717

718
	_src = (struct snd_emu10k1_fx8010_control_gpr __user *)src;
719
	if (emu->support_tlv) {
720
		if (in_kernel)
721
			*dst = src[idx];
722
		else if (copy_from_user(dst, &_src[idx], sizeof(*src)))
723
			return -EFAULT;
724
		return 0;
725
	}
726

727
	octl = (struct snd_emu10k1_fx8010_control_old_gpr *)src;
728
	_octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)octl;
729
	if (in_kernel)
730
		memcpy(dst, &octl[idx], sizeof(*octl));
731
	else if (copy_from_user(dst, &_octl[idx], sizeof(*octl)))
732
		return -EFAULT;
733
	dst->tlv = NULL;
734
	return 0;
735
}
736

737
static int copy_gctl_to_user(struct snd_emu10k1 *emu,
738
		     struct snd_emu10k1_fx8010_control_gpr *dst,
739
		     struct snd_emu10k1_fx8010_control_gpr *src,
740
		     int idx)
741
{
742
	struct snd_emu10k1_fx8010_control_gpr __user *_dst;
743
	struct snd_emu10k1_fx8010_control_old_gpr __user *octl;
744

745
	_dst = (struct snd_emu10k1_fx8010_control_gpr __user *)dst;
746
	if (emu->support_tlv)
747
		return copy_to_user(&_dst[idx], src, sizeof(*src));
748
	
749
	octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)dst;
750
	return copy_to_user(&octl[idx], src, sizeof(*octl));
751
}
752

753
static int copy_ctl_elem_id(const struct emu10k1_ctl_elem_id *list, int i,
754
			    struct emu10k1_ctl_elem_id *ret, bool in_kernel)
755
{
756
	struct emu10k1_ctl_elem_id __user *_id =
757
		(struct emu10k1_ctl_elem_id __user *)&list[i];
758

759
	if (in_kernel)
760
		*ret = list[i];
761
	else if (copy_from_user(ret, _id, sizeof(*ret)))
762
		return -EFAULT;
763
	return 0;
764
}
765

766
static int snd_emu10k1_verify_controls(struct snd_emu10k1 *emu,
767
				       struct snd_emu10k1_fx8010_code *icode,
768
				       bool in_kernel)
769
{
770
	unsigned int i;
771
	struct emu10k1_ctl_elem_id id;
772
	struct snd_emu10k1_fx8010_control_gpr *gctl;
773
	struct snd_ctl_elem_id *gctl_id;
774
	int err;
775
	
776
	for (i = 0; i < icode->gpr_del_control_count; i++) {
777
		err = copy_ctl_elem_id(icode->gpr_del_controls, i, &id,
778
				       in_kernel);
779
		if (err < 0)
780
			return err;
781
		if (snd_emu10k1_look_for_ctl(emu, &id) == NULL)
782
			return -ENOENT;
783
	}
784
	gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
785
	if (! gctl)
786
		return -ENOMEM;
787
	err = 0;
788
	for (i = 0; i < icode->gpr_add_control_count; i++) {
789
		if (copy_gctl(emu, gctl, icode->gpr_add_controls, i,
790
			      in_kernel)) {
791
			err = -EFAULT;
792
			goto __error;
793
		}
794
		if (snd_emu10k1_look_for_ctl(emu, &gctl->id))
795
			continue;
796
		gctl_id = (struct snd_ctl_elem_id *)&gctl->id;
797
		if (snd_ctl_find_id(emu->card, gctl_id)) {
798
			err = -EEXIST;
799
			goto __error;
800
		}
801
		if (gctl_id->iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
802
		    gctl_id->iface != SNDRV_CTL_ELEM_IFACE_PCM) {
803
			err = -EINVAL;
804
			goto __error;
805
		}
806
		switch (gctl->translation) {
807
		case EMU10K1_GPR_TRANSLATION_NONE:
808
		case EMU10K1_GPR_TRANSLATION_NEGATE:
809
			break;
810
		case EMU10K1_GPR_TRANSLATION_TABLE100:
811
		case EMU10K1_GPR_TRANSLATION_NEG_TABLE100:
812
			if (gctl->min != 0 || gctl->max != 100) {
813
				err = -EINVAL;
814
				goto __error;
815
			}
816
			break;
817
		case EMU10K1_GPR_TRANSLATION_BASS:
818
		case EMU10K1_GPR_TRANSLATION_TREBLE:
819
			if (gctl->min != 0 || gctl->max != 40) {
820
				err = -EINVAL;
821
				goto __error;
822
			}
823
			break;
824
		case EMU10K1_GPR_TRANSLATION_ONOFF:
825
			if (gctl->min != 0 || gctl->max != 1) {
826
				err = -EINVAL;
827
				goto __error;
828
			}
829
			break;
830
		default:
831
			err = -EINVAL;
832
			goto __error;
833
		}
834
	}
835
	for (i = 0; i < icode->gpr_list_control_count; i++) {
836
	     	/* FIXME: we need to check the WRITE access */
837
		if (copy_gctl(emu, gctl, icode->gpr_list_controls, i,
838
			      in_kernel)) {
839
			err = -EFAULT;
840
			goto __error;
841
		}
842
	}
843
 __error:
844
	kfree(gctl);
845
	return err;
846
}
847

848
static void snd_emu10k1_ctl_private_free(struct snd_kcontrol *kctl)
849
{
850
	struct snd_emu10k1_fx8010_ctl *ctl;
851
	
852
	ctl = (struct snd_emu10k1_fx8010_ctl *) kctl->private_value;
853
	kctl->private_value = 0;
854
	list_del(&ctl->list);
855
	kfree(ctl);
856
	kfree(kctl->tlv.p);
857
}
858

859
static int snd_emu10k1_add_controls(struct snd_emu10k1 *emu,
860
				    struct snd_emu10k1_fx8010_code *icode,
861
				    bool in_kernel)
862
{
863
	unsigned int i, j;
864
	struct snd_emu10k1_fx8010_control_gpr *gctl;
865
	struct snd_ctl_elem_id *gctl_id;
866
	struct snd_emu10k1_fx8010_ctl *ctl, *nctl;
867
	struct snd_kcontrol_new knew;
868
	struct snd_kcontrol *kctl;
869
	struct snd_ctl_elem_value *val;
870
	int err = 0;
871

872
	val = kmalloc(sizeof(*val), GFP_KERNEL);
873
	gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
874
	nctl = kmalloc(sizeof(*nctl), GFP_KERNEL);
875
	if (!val || !gctl || !nctl) {
876
		err = -ENOMEM;
877
		goto __error;
878
	}
879

880
	for (i = 0; i < icode->gpr_add_control_count; i++) {
881
		if (copy_gctl(emu, gctl, icode->gpr_add_controls, i,
882
			      in_kernel)) {
883
			err = -EFAULT;
884
			goto __error;
885
		}
886
		gctl_id = (struct snd_ctl_elem_id *)&gctl->id;
887
		if (gctl_id->iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
888
		    gctl_id->iface != SNDRV_CTL_ELEM_IFACE_PCM) {
889
			err = -EINVAL;
890
			goto __error;
891
		}
892
		if (!*gctl_id->name) {
893
			err = -EINVAL;
894
			goto __error;
895
		}
896
		ctl = snd_emu10k1_look_for_ctl(emu, &gctl->id);
897
		memset(&knew, 0, sizeof(knew));
898
		knew.iface = gctl_id->iface;
899
		knew.name = gctl_id->name;
900
		knew.index = gctl_id->index;
901
		knew.device = gctl_id->device;
902
		knew.subdevice = gctl_id->subdevice;
903
		knew.info = snd_emu10k1_gpr_ctl_info;
904
		knew.tlv.p = copy_tlv((const unsigned int __user *)gctl->tlv, in_kernel);
905
		if (knew.tlv.p)
906
			knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
907
				SNDRV_CTL_ELEM_ACCESS_TLV_READ;
908
		knew.get = snd_emu10k1_gpr_ctl_get;
909
		knew.put = snd_emu10k1_gpr_ctl_put;
910
		memset(nctl, 0, sizeof(*nctl));
911
		nctl->vcount = gctl->vcount;
912
		nctl->count = gctl->count;
913
		for (j = 0; j < 32; j++) {
914
			nctl->gpr[j] = gctl->gpr[j];
915
			nctl->value[j] = ~gctl->value[j];	/* inverted, we want to write new value in gpr_ctl_put() */
916
			val->value.integer.value[j] = gctl->value[j];
917
		}
918
		nctl->min = gctl->min;
919
		nctl->max = gctl->max;
920
		nctl->translation = gctl->translation;
921
		if (ctl == NULL) {
922
			ctl = kmalloc(sizeof(*ctl), GFP_KERNEL);
923
			if (ctl == NULL) {
924
				err = -ENOMEM;
925
				kfree(knew.tlv.p);
926
				goto __error;
927
			}
928
			knew.private_value = (unsigned long)ctl;
929
			*ctl = *nctl;
930
			kctl = snd_ctl_new1(&knew, emu);
931
			err = snd_ctl_add(emu->card, kctl);
932
			if (err < 0) {
933
				kfree(ctl);
934
				kfree(knew.tlv.p);
935
				goto __error;
936
			}
937
			kctl->private_free = snd_emu10k1_ctl_private_free;
938
			ctl->kcontrol = kctl;
939
			list_add_tail(&ctl->list, &emu->fx8010.gpr_ctl);
940
		} else {
941
			/* overwrite */
942
			nctl->list = ctl->list;
943
			nctl->kcontrol = ctl->kcontrol;
944
			*ctl = *nctl;
945
			snd_ctl_notify(emu->card, SNDRV_CTL_EVENT_MASK_VALUE |
946
			                          SNDRV_CTL_EVENT_MASK_INFO, &ctl->kcontrol->id);
947
		}
948
		snd_emu10k1_gpr_ctl_put(ctl->kcontrol, val);
949
	}
950
      __error:
951
	kfree(nctl);
952
	kfree(gctl);
953
	kfree(val);
954
	return err;
955
}
956

957
static int snd_emu10k1_del_controls(struct snd_emu10k1 *emu,
958
				    struct snd_emu10k1_fx8010_code *icode,
959
				    bool in_kernel)
960
{
961
	unsigned int i;
962
	struct emu10k1_ctl_elem_id id;
963
	struct snd_emu10k1_fx8010_ctl *ctl;
964
	struct snd_card *card = emu->card;
965
	int err;
966
	
967
	for (i = 0; i < icode->gpr_del_control_count; i++) {
968
		err = copy_ctl_elem_id(icode->gpr_del_controls, i, &id,
969
				       in_kernel);
970
		if (err < 0)
971
			return err;
972
		ctl = snd_emu10k1_look_for_ctl(emu, &id);
973
		if (ctl)
974
			snd_ctl_remove(card, ctl->kcontrol);
975
	}
976
	return 0;
977
}
978

979
static int snd_emu10k1_list_controls(struct snd_emu10k1 *emu,
980
				     struct snd_emu10k1_fx8010_code *icode)
981
{
982
	unsigned int i = 0, j;
983
	unsigned int total = 0;
984
	struct snd_emu10k1_fx8010_control_gpr *gctl;
985
	struct snd_emu10k1_fx8010_ctl *ctl;
986
	struct snd_ctl_elem_id *id;
987

988
	gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
989
	if (! gctl)
990
		return -ENOMEM;
991

992
	list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
993
		total++;
994
		if (icode->gpr_list_controls &&
995
		    i < icode->gpr_list_control_count) {
996
			memset(gctl, 0, sizeof(*gctl));
997
			id = &ctl->kcontrol->id;
998
			gctl->id.iface = (__force int)id->iface;
999
			strscpy(gctl->id.name, id->name, sizeof(gctl->id.name));
1000
			gctl->id.index = id->index;
1001
			gctl->id.device = id->device;
1002
			gctl->id.subdevice = id->subdevice;
1003
			gctl->vcount = ctl->vcount;
1004
			gctl->count = ctl->count;
1005
			for (j = 0; j < 32; j++) {
1006
				gctl->gpr[j] = ctl->gpr[j];
1007
				gctl->value[j] = ctl->value[j];
1008
			}
1009
			gctl->min = ctl->min;
1010
			gctl->max = ctl->max;
1011
			gctl->translation = ctl->translation;
1012
			if (copy_gctl_to_user(emu, icode->gpr_list_controls,
1013
					      gctl, i)) {
1014
				kfree(gctl);
1015
				return -EFAULT;
1016
			}
1017
			i++;
1018
		}
1019
	}
1020
	icode->gpr_list_control_total = total;
1021
	kfree(gctl);
1022
	return 0;
1023
}
1024

1025
static int snd_emu10k1_icode_poke(struct snd_emu10k1 *emu,
1026
				  struct snd_emu10k1_fx8010_code *icode,
1027
				  bool in_kernel)
1028
{
1029
	int err = 0;
1030

1031
	mutex_lock(&emu->fx8010.lock);
1032
	err = snd_emu10k1_verify_controls(emu, icode, in_kernel);
1033
	if (err < 0)
1034
		goto __error;
1035
	strscpy(emu->fx8010.name, icode->name, sizeof(emu->fx8010.name));
1036
	/* stop FX processor - this may be dangerous, but it's better to miss
1037
	   some samples than generate wrong ones - [jk] */
1038
	if (emu->audigy)
1039
		snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
1040
	else
1041
		snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
1042
	/* ok, do the main job */
1043
	err = snd_emu10k1_del_controls(emu, icode, in_kernel);
1044
	if (err < 0)
1045
		goto __error;
1046
	err = snd_emu10k1_gpr_poke(emu, icode, in_kernel);
1047
	if (err < 0)
1048
		goto __error;
1049
	err = snd_emu10k1_tram_poke(emu, icode, in_kernel);
1050
	if (err < 0)
1051
		goto __error;
1052
	err = snd_emu10k1_code_poke(emu, icode, in_kernel);
1053
	if (err < 0)
1054
		goto __error;
1055
	err = snd_emu10k1_add_controls(emu, icode, in_kernel);
1056
	if (err < 0)
1057
		goto __error;
1058
	/* start FX processor when the DSP code is updated */
1059
	if (emu->audigy)
1060
		snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
1061
	else
1062
		snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
1063
      __error:
1064
	mutex_unlock(&emu->fx8010.lock);
1065
	return err;
1066
}
1067

1068
static int snd_emu10k1_icode_peek(struct snd_emu10k1 *emu,
1069
				  struct snd_emu10k1_fx8010_code *icode)
1070
{
1071
	int err;
1072

1073
	mutex_lock(&emu->fx8010.lock);
1074
	strscpy(icode->name, emu->fx8010.name, sizeof(icode->name));
1075
	/* ok, do the main job */
1076
	err = snd_emu10k1_gpr_peek(emu, icode);
1077
	if (err >= 0)
1078
		err = snd_emu10k1_tram_peek(emu, icode);
1079
	if (err >= 0)
1080
		err = snd_emu10k1_code_peek(emu, icode);
1081
	if (err >= 0)
1082
		err = snd_emu10k1_list_controls(emu, icode);
1083
	mutex_unlock(&emu->fx8010.lock);
1084
	return err;
1085
}
1086

1087
static int snd_emu10k1_ipcm_poke(struct snd_emu10k1 *emu,
1088
				 struct snd_emu10k1_fx8010_pcm_rec *ipcm)
1089
{
1090
	unsigned int i;
1091
	int err = 0;
1092
	struct snd_emu10k1_fx8010_pcm *pcm;
1093

1094
	if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
1095
		return -EINVAL;
1096
	ipcm->substream = array_index_nospec(ipcm->substream,
1097
					     EMU10K1_FX8010_PCM_COUNT);
1098
	if (ipcm->channels > 32)
1099
		return -EINVAL;
1100
	pcm = &emu->fx8010.pcm[ipcm->substream];
1101
	mutex_lock(&emu->fx8010.lock);
1102
	spin_lock_irq(&emu->reg_lock);
1103
	if (pcm->opened) {
1104
		err = -EBUSY;
1105
		goto __error;
1106
	}
1107
	if (ipcm->channels == 0) {	/* remove */
1108
		pcm->valid = 0;
1109
	} else {
1110
		/* FIXME: we need to add universal code to the PCM transfer routine */
1111
		if (ipcm->channels != 2) {
1112
			err = -EINVAL;
1113
			goto __error;
1114
		}
1115
		pcm->valid = 1;
1116
		pcm->opened = 0;
1117
		pcm->channels = ipcm->channels;
1118
		pcm->tram_start = ipcm->tram_start;
1119
		pcm->buffer_size = ipcm->buffer_size;
1120
		pcm->gpr_size = ipcm->gpr_size;
1121
		pcm->gpr_count = ipcm->gpr_count;
1122
		pcm->gpr_tmpcount = ipcm->gpr_tmpcount;
1123
		pcm->gpr_ptr = ipcm->gpr_ptr;
1124
		pcm->gpr_trigger = ipcm->gpr_trigger;
1125
		pcm->gpr_running = ipcm->gpr_running;
1126
		for (i = 0; i < pcm->channels; i++)
1127
			pcm->etram[i] = ipcm->etram[i];
1128
	}
1129
      __error:
1130
	spin_unlock_irq(&emu->reg_lock);
1131
	mutex_unlock(&emu->fx8010.lock);
1132
	return err;
1133
}
1134

1135
static int snd_emu10k1_ipcm_peek(struct snd_emu10k1 *emu,
1136
				 struct snd_emu10k1_fx8010_pcm_rec *ipcm)
1137
{
1138
	unsigned int i;
1139
	int err = 0;
1140
	struct snd_emu10k1_fx8010_pcm *pcm;
1141

1142
	if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
1143
		return -EINVAL;
1144
	ipcm->substream = array_index_nospec(ipcm->substream,
1145
					     EMU10K1_FX8010_PCM_COUNT);
1146
	pcm = &emu->fx8010.pcm[ipcm->substream];
1147
	mutex_lock(&emu->fx8010.lock);
1148
	spin_lock_irq(&emu->reg_lock);
1149
	ipcm->channels = pcm->channels;
1150
	ipcm->tram_start = pcm->tram_start;
1151
	ipcm->buffer_size = pcm->buffer_size;
1152
	ipcm->gpr_size = pcm->gpr_size;
1153
	ipcm->gpr_ptr = pcm->gpr_ptr;
1154
	ipcm->gpr_count = pcm->gpr_count;
1155
	ipcm->gpr_tmpcount = pcm->gpr_tmpcount;
1156
	ipcm->gpr_trigger = pcm->gpr_trigger;
1157
	ipcm->gpr_running = pcm->gpr_running;
1158
	for (i = 0; i < pcm->channels; i++)
1159
		ipcm->etram[i] = pcm->etram[i];
1160
	ipcm->res1 = ipcm->res2 = 0;
1161
	ipcm->pad = 0;
1162
	spin_unlock_irq(&emu->reg_lock);
1163
	mutex_unlock(&emu->fx8010.lock);
1164
	return err;
1165
}
1166

1167
#define SND_EMU10K1_GPR_CONTROLS	44
1168
#define SND_EMU10K1_INPUTS		12
1169
#define SND_EMU10K1_PLAYBACK_CHANNELS	8
1170
#define SND_EMU10K1_CAPTURE_CHANNELS	4
1171

1172
#define HR_VAL(v) ((v) * 0x80000000LL / 100 - 1)
1173

1174
static void
1175
snd_emu10k1_init_mono_control2(struct snd_emu10k1_fx8010_control_gpr *ctl,
1176
			       const char *name, int gpr, int defval, int defval_hr)
1177
{
1178
	ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
1179
	strscpy(ctl->id.name, name);
1180
	ctl->vcount = ctl->count = 1;
1181
	if (high_res_gpr_volume) {
1182
		ctl->min = -1;
1183
		ctl->max = 0x7fffffff;
1184
		ctl->tlv = snd_emu10k1_db_linear;
1185
		ctl->translation = EMU10K1_GPR_TRANSLATION_NEGATE;
1186
		defval = defval_hr;
1187
	} else {
1188
		ctl->min = 0;
1189
		ctl->max = 100;
1190
		ctl->tlv = snd_emu10k1_db_scale1;
1191
		ctl->translation = EMU10K1_GPR_TRANSLATION_NEG_TABLE100;
1192
	}
1193
	ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1194
}
1195
#define snd_emu10k1_init_mono_control(ctl, name, gpr, defval) \
1196
	snd_emu10k1_init_mono_control2(ctl, name, gpr, defval, HR_VAL(defval))
1197

1198
static void
1199
snd_emu10k1_init_stereo_control2(struct snd_emu10k1_fx8010_control_gpr *ctl,
1200
				 const char *name, int gpr, int defval, int defval_hr)
1201
{
1202
	ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
1203
	strscpy(ctl->id.name, name);
1204
	ctl->vcount = ctl->count = 2;
1205
	if (high_res_gpr_volume) {
1206
		ctl->min = -1;
1207
		ctl->max = 0x7fffffff;
1208
		ctl->tlv = snd_emu10k1_db_linear;
1209
		ctl->translation = EMU10K1_GPR_TRANSLATION_NEGATE;
1210
		defval = defval_hr;
1211
	} else {
1212
		ctl->min = 0;
1213
		ctl->max = 100;
1214
		ctl->tlv = snd_emu10k1_db_scale1;
1215
		ctl->translation = EMU10K1_GPR_TRANSLATION_NEG_TABLE100;
1216
	}
1217
	ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1218
	ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
1219
}
1220
#define snd_emu10k1_init_stereo_control(ctl, name, gpr, defval) \
1221
	snd_emu10k1_init_stereo_control2(ctl, name, gpr, defval, HR_VAL(defval))
1222

1223
static void
1224
snd_emu10k1_init_mono_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
1225
				    const char *name, int gpr, int defval)
1226
{
1227
	ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
1228
	strscpy(ctl->id.name, name);
1229
	ctl->vcount = ctl->count = 1;
1230
	ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1231
	ctl->min = 0;
1232
	ctl->max = 1;
1233
	ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
1234
}
1235

1236
static void
1237
snd_emu10k1_init_stereo_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
1238
				      const char *name, int gpr, int defval)
1239
{
1240
	ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
1241
	strscpy(ctl->id.name, name);
1242
	ctl->vcount = ctl->count = 2;
1243
	ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
1244
	ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
1245
	ctl->min = 0;
1246
	ctl->max = 1;
1247
	ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
1248
}
1249

1250
/*
1251
 * Used for emu1010 - conversion from 32-bit capture inputs from the FPGA
1252
 * to 2 x 16-bit registers in Audigy - their values are read via DMA.
1253
 * Conversion is performed by Audigy DSP instructions of FX8010.
1254
 */
1255
static void snd_emu10k1_audigy_dsp_convert_32_to_2x16(
1256
				struct snd_emu10k1_fx8010_code *icode,
1257
				u32 *ptr, int tmp, int bit_shifter16,
1258
				int reg_in, int reg_out)
1259
{
1260
	// This leaves the low word in place, which is fine,
1261
	// as the low bits are completely ignored subsequently.
1262
	// reg_out[1] = reg_in
1263
	A_OP(icode, ptr, iACC3, reg_out + 1, reg_in, A_C_00000000, A_C_00000000);
1264
	// It is fine to read reg_in multiple times.
1265
	// tmp = reg_in << 15
1266
	A_OP(icode, ptr, iMACINT1, A_GPR(tmp), A_C_00000000, reg_in, A_GPR(bit_shifter16));
1267
	// Left-shift once more. This is a separate step, as the
1268
	// signed multiplication would clobber the MSB.
1269
	// reg_out[0] = tmp + ((tmp << 31) >> 31)
1270
	A_OP(icode, ptr, iMAC3, reg_out, A_GPR(tmp), A_GPR(tmp), A_C_80000000);
1271
}
1272

1273
#define ENUM_GPR(name, size) name, name ## _dummy = name + (size) - 1
1274

1275
/*
1276
 * initial DSP configuration for Audigy
1277
 */
1278

1279
static int _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu)
1280
{
1281
	int err, z, nctl;
1282
	enum {
1283
		ENUM_GPR(playback, SND_EMU10K1_PLAYBACK_CHANNELS),
1284
		ENUM_GPR(stereo_mix, 2),
1285
		ENUM_GPR(capture, 2),
1286
		ENUM_GPR(bit_shifter16, 1),
1287
		// The fixed allocation of these breaks the pattern, but why not.
1288
		// Splitting these into left/right is questionable, as it will break
1289
		// down for center/lfe. But it works for stereo/quadro, so whatever.
1290
		ENUM_GPR(bass_gpr, 2 * 5),  // two sides, five coefficients
1291
		ENUM_GPR(treble_gpr, 2 * 5),
1292
		ENUM_GPR(bass_tmp, SND_EMU10K1_PLAYBACK_CHANNELS * 4),  // four delay stages
1293
		ENUM_GPR(treble_tmp, SND_EMU10K1_PLAYBACK_CHANNELS * 4),
1294
		ENUM_GPR(tmp, 3),
1295
		num_static_gprs
1296
	};
1297
	int gpr = num_static_gprs;
1298
	u32 ptr, ptr_skip;
1299
	struct snd_emu10k1_fx8010_code *icode = NULL;
1300
	struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
1301
	u32 *gpr_map;
1302

1303
	err = -ENOMEM;
1304
	icode = kzalloc(sizeof(*icode), GFP_KERNEL);
1305
	if (!icode)
1306
		return err;
1307

1308
	icode->gpr_map = kcalloc(512 + 256 + 256 + 2 * 1024,
1309
				 sizeof(u_int32_t), GFP_KERNEL);
1310
	if (!icode->gpr_map)
1311
		goto __err_gpr;
1312
	controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
1313
			   sizeof(*controls), GFP_KERNEL);
1314
	if (!controls)
1315
		goto __err_ctrls;
1316

1317
	gpr_map = icode->gpr_map;
1318

1319
	icode->tram_data_map = icode->gpr_map + 512;
1320
	icode->tram_addr_map = icode->tram_data_map + 256;
1321
	icode->code = icode->tram_addr_map + 256;
1322

1323
	/* clear free GPRs */
1324
	memset(icode->gpr_valid, 0xff, 512 / 8);
1325
		
1326
	/* clear TRAM data & address lines */
1327
	memset(icode->tram_valid, 0xff, 256 / 8);
1328

1329
	strscpy(icode->name, "Audigy DSP code for ALSA");
1330
	ptr = 0;
1331
	nctl = 0;
1332
	gpr_map[bit_shifter16] = 0x00008000;
1333

1334
#if 1
1335
	/* PCM front Playback Volume (independent from stereo mix)
1336
	 * playback = -gpr * FXBUS_PCM_LEFT_FRONT >> 31
1337
	 * where gpr contains negated attenuation from corresponding mixer control
1338
	 * (snd_emu10k1_init_stereo_control)
1339
	 */
1340
	A_OP(icode, &ptr, iMAC1, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT));
1341
	A_OP(icode, &ptr, iMAC1, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT));
1342
	snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Front Playback Volume", gpr, 100);
1343
	gpr += 2;
1344

1345
	/* PCM Surround Playback (independent from stereo mix) */
1346
	A_OP(icode, &ptr, iMAC1, A_GPR(playback+2), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_REAR));
1347
	A_OP(icode, &ptr, iMAC1, A_GPR(playback+3), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_REAR));
1348
	snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Surround Playback Volume", gpr, 100);
1349
	gpr += 2;
1350
	
1351
	/* PCM Side Playback (independent from stereo mix) */
1352
	if (emu->card_capabilities->spk71) {
1353
		A_OP(icode, &ptr, iMAC1, A_GPR(playback+6), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_SIDE));
1354
		A_OP(icode, &ptr, iMAC1, A_GPR(playback+7), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_SIDE));
1355
		snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Side Playback Volume", gpr, 100);
1356
		gpr += 2;
1357
	}
1358

1359
	/* PCM Center Playback (independent from stereo mix) */
1360
	A_OP(icode, &ptr, iMAC1, A_GPR(playback+4), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_CENTER));
1361
	snd_emu10k1_init_mono_control(&controls[nctl++], "PCM Center Playback Volume", gpr, 100);
1362
	gpr++;
1363

1364
	/* PCM LFE Playback (independent from stereo mix) */
1365
	A_OP(icode, &ptr, iMAC1, A_GPR(playback+5), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LFE));
1366
	snd_emu10k1_init_mono_control(&controls[nctl++], "PCM LFE Playback Volume", gpr, 100);
1367
	gpr++;
1368
	
1369
	/*
1370
	 * Stereo Mix
1371
	 */
1372
	/* Wave (PCM) Playback Volume (will be renamed later) */
1373
	A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
1374
	A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
1375
	snd_emu10k1_init_stereo_control(&controls[nctl++], "Wave Playback Volume", gpr, 100);
1376
	gpr += 2;
1377

1378
	/* Synth Playback */
1379
	A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+0), A_GPR(stereo_mix+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
1380
	A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+1), A_GPR(stereo_mix+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
1381
	snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Playback Volume", gpr, 100);
1382
	gpr += 2;
1383

1384
	/* Wave (PCM) Capture */
1385
	A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
1386
	A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
1387
	snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Capture Volume", gpr, 0);
1388
	gpr += 2;
1389

1390
	/* Synth Capture */
1391
	A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
1392
	A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
1393
	snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Capture Volume", gpr, 0);
1394
	gpr += 2;
1395

1396
	// We need to double the volume, as we configure the voices for half volume,
1397
	// which is necessary for bit-identical reproduction.
1398
	{ static_assert(stereo_mix == playback + SND_EMU10K1_PLAYBACK_CHANNELS); }
1399
	for (z = 0; z < SND_EMU10K1_PLAYBACK_CHANNELS + 2; z++)
1400
		A_OP(icode, &ptr, iACC3, A_GPR(playback + z), A_GPR(playback + z), A_GPR(playback + z), A_C_00000000);
1401

1402
	/*
1403
	 * inputs
1404
	 */
1405
#define A_ADD_VOLUME_IN(var,vol,input) \
1406
	A_OP(icode, &ptr, iMAC1, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
1407

1408
	if (emu->card_capabilities->emu_model) {
1409
		/* EMU1010 DSP 0 and DSP 1 Capture */
1410
		// The 24 MSB hold the actual value. We implicitly discard the 16 LSB.
1411
		if (emu->card_capabilities->ca0108_chip) {
1412
			// For unclear reasons, the EMU32IN cannot be the Y operand!
1413
			A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A3_EMU32IN(0x0), A_GPR(gpr));
1414
			// A3_EMU32IN(0) is delayed by one sample, so all other A3_EMU32IN channels
1415
			// need to be delayed as well; we use an auxiliary register for that.
1416
			A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+2), A_GPR(gpr+1));
1417
			A_OP(icode, &ptr, iACC3, A_GPR(gpr+2), A3_EMU32IN(0x1), A_C_00000000, A_C_00000000);
1418
		} else {
1419
			A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A_P16VIN(0x0), A_GPR(gpr));
1420
			// A_P16VIN(0) is delayed by one sample, so all other A_P16VIN channels
1421
			// need to be delayed as well; we use an auxiliary register for that.
1422
			A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+2), A_GPR(gpr+1));
1423
			A_OP(icode, &ptr, iACC3, A_GPR(gpr+2), A_P16VIN(0x1), A_C_00000000, A_C_00000000);
1424
		}
1425
		snd_emu10k1_init_stereo_control(&controls[nctl++], "EMU Capture Volume", gpr, 0);
1426
		gpr_map[gpr + 2] = 0x00000000;
1427
		gpr += 3;
1428
	} else {
1429
		if (emu->card_capabilities->ac97_chip) {
1430
			/* AC'97 Playback Volume - used only for mic (renamed later) */
1431
			A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AC97_L);
1432
			A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AC97_R);
1433
			snd_emu10k1_init_stereo_control(&controls[nctl++], "AMic Playback Volume", gpr, 0);
1434
			gpr += 2;
1435
			/* AC'97 Capture Volume - used only for mic */
1436
			A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AC97_L);
1437
			A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AC97_R);
1438
			snd_emu10k1_init_stereo_control(&controls[nctl++], "Mic Capture Volume", gpr, 0);
1439
			gpr += 2;
1440

1441
			/* mic capture buffer */
1442
			A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), A_C_40000000, A_EXTIN(A_EXTIN_AC97_R));
1443
		}
1444

1445
		/* Audigy CD Playback Volume */
1446
		A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L);
1447
		A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_SPDIF_CD_R);
1448
		snd_emu10k1_init_stereo_control(&controls[nctl++],
1449
						emu->card_capabilities->ac97_chip ? "Audigy CD Playback Volume" : "CD Playback Volume",
1450
						gpr, 0);
1451
		gpr += 2;
1452
		/* Audigy CD Capture Volume */
1453
		A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_SPDIF_CD_L);
1454
		A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_SPDIF_CD_R);
1455
		snd_emu10k1_init_stereo_control(&controls[nctl++],
1456
						emu->card_capabilities->ac97_chip ? "Audigy CD Capture Volume" : "CD Capture Volume",
1457
						gpr, 0);
1458
		gpr += 2;
1459

1460
		/* Optical SPDIF Playback Volume */
1461
		A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_OPT_SPDIF_L);
1462
		A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
1463
		snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",PLAYBACK,VOLUME), gpr, 0);
1464
		gpr += 2;
1465
		/* Optical SPDIF Capture Volume */
1466
		A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_OPT_SPDIF_L);
1467
		A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
1468
		snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",CAPTURE,VOLUME), gpr, 0);
1469
		gpr += 2;
1470

1471
		/* Line2 Playback Volume */
1472
		A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_LINE2_L);
1473
		A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_LINE2_R);
1474
		snd_emu10k1_init_stereo_control(&controls[nctl++],
1475
						emu->card_capabilities->ac97_chip ? "Line2 Playback Volume" : "Line Playback Volume",
1476
						gpr, 0);
1477
		gpr += 2;
1478
		/* Line2 Capture Volume */
1479
		A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_LINE2_L);
1480
		A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_LINE2_R);
1481
		snd_emu10k1_init_stereo_control(&controls[nctl++],
1482
						emu->card_capabilities->ac97_chip ? "Line2 Capture Volume" : "Line Capture Volume",
1483
						gpr, 0);
1484
		gpr += 2;
1485

1486
		/* Philips ADC Playback Volume */
1487
		A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_ADC_L);
1488
		A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_ADC_R);
1489
		snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Playback Volume", gpr, 0);
1490
		gpr += 2;
1491
		/* Philips ADC Capture Volume */
1492
		A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_ADC_L);
1493
		A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_ADC_R);
1494
		snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Capture Volume", gpr, 0);
1495
		gpr += 2;
1496

1497
		/* Aux2 Playback Volume */
1498
		A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AUX2_L);
1499
		A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AUX2_R);
1500
		snd_emu10k1_init_stereo_control(&controls[nctl++],
1501
						emu->card_capabilities->ac97_chip ? "Aux2 Playback Volume" : "Aux Playback Volume",
1502
						gpr, 0);
1503
		gpr += 2;
1504
		/* Aux2 Capture Volume */
1505
		A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AUX2_L);
1506
		A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AUX2_R);
1507
		snd_emu10k1_init_stereo_control(&controls[nctl++],
1508
						emu->card_capabilities->ac97_chip ? "Aux2 Capture Volume" : "Aux Capture Volume",
1509
						gpr, 0);
1510
		gpr += 2;
1511
	}
1512
	
1513
	/* Stereo Mix Front Playback Volume */
1514
	A_OP(icode, &ptr, iMAC1, A_GPR(playback), A_GPR(playback), A_GPR(gpr), A_GPR(stereo_mix));
1515
	A_OP(icode, &ptr, iMAC1, A_GPR(playback+1), A_GPR(playback+1), A_GPR(gpr+1), A_GPR(stereo_mix+1));
1516
	snd_emu10k1_init_stereo_control(&controls[nctl++], "Front Playback Volume", gpr, 100);
1517
	gpr += 2;
1518
	
1519
	/* Stereo Mix Surround Playback */
1520
	A_OP(icode, &ptr, iMAC1, A_GPR(playback+2), A_GPR(playback+2), A_GPR(gpr), A_GPR(stereo_mix));
1521
	A_OP(icode, &ptr, iMAC1, A_GPR(playback+3), A_GPR(playback+3), A_GPR(gpr+1), A_GPR(stereo_mix+1));
1522
	snd_emu10k1_init_stereo_control(&controls[nctl++], "Surround Playback Volume", gpr, 0);
1523
	gpr += 2;
1524

1525
	/* Stereo Mix Center Playback */
1526
	/* Center = sub = Left/2 + Right/2 */
1527
	A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), A_C_40000000, A_GPR(stereo_mix+1));
1528
	A_OP(icode, &ptr, iMAC1, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp));
1529
	snd_emu10k1_init_mono_control(&controls[nctl++], "Center Playback Volume", gpr, 0);
1530
	gpr++;
1531

1532
	/* Stereo Mix LFE Playback */
1533
	A_OP(icode, &ptr, iMAC1, A_GPR(playback+5), A_GPR(playback+5), A_GPR(gpr), A_GPR(tmp));
1534
	snd_emu10k1_init_mono_control(&controls[nctl++], "LFE Playback Volume", gpr, 0);
1535
	gpr++;
1536
	
1537
	if (emu->card_capabilities->spk71) {
1538
		/* Stereo Mix Side Playback */
1539
		A_OP(icode, &ptr, iMAC1, A_GPR(playback+6), A_GPR(playback+6), A_GPR(gpr), A_GPR(stereo_mix));
1540
		A_OP(icode, &ptr, iMAC1, A_GPR(playback+7), A_GPR(playback+7), A_GPR(gpr+1), A_GPR(stereo_mix+1));
1541
		snd_emu10k1_init_stereo_control(&controls[nctl++], "Side Playback Volume", gpr, 0);
1542
		gpr += 2;
1543
	}
1544

1545
	/*
1546
	 * outputs
1547
	 */
1548
#define A_PUT_OUTPUT(out,src) A_OP(icode, &ptr, iACC3, A_EXTOUT(out), A_C_00000000, A_C_00000000, A_GPR(src))
1549
#define A_PUT_STEREO_OUTPUT(out1,out2,src) \
1550
	{A_PUT_OUTPUT(out1,src); A_PUT_OUTPUT(out2,src+1);}
1551

1552
#define _A_SWITCH(icode, ptr, dst, src, sw) \
1553
	A_OP((icode), ptr, iMACINT0, dst, A_C_00000000, src, sw);
1554
#define A_SWITCH(icode, ptr, dst, src, sw) \
1555
		_A_SWITCH(icode, ptr, A_GPR(dst), A_GPR(src), A_GPR(sw))
1556
#define _A_SWITCH_NEG(icode, ptr, dst, src) \
1557
	A_OP((icode), ptr, iANDXOR, dst, src, A_C_00000001, A_C_00000001);
1558
#define A_SWITCH_NEG(icode, ptr, dst, src) \
1559
		_A_SWITCH_NEG(icode, ptr, A_GPR(dst), A_GPR(src))
1560

1561

1562
	/*
1563
	 *  Process tone control
1564
	 */
1565
	ctl = &controls[nctl + 0];
1566
	ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
1567
	strscpy(ctl->id.name, "Tone Control - Bass");
1568
	ctl->vcount = 2;
1569
	ctl->count = 10;
1570
	ctl->min = 0;
1571
	ctl->max = 40;
1572
	ctl->value[0] = ctl->value[1] = 20;
1573
	ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
1574
	ctl = &controls[nctl + 1];
1575
	ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
1576
	strscpy(ctl->id.name, "Tone Control - Treble");
1577
	ctl->vcount = 2;
1578
	ctl->count = 10;
1579
	ctl->min = 0;
1580
	ctl->max = 40;
1581
	ctl->value[0] = ctl->value[1] = 20;
1582
	ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
1583
	for (z = 0; z < 5; z++) {
1584
		int j;
1585
		for (j = 0; j < 2; j++) {
1586
			controls[nctl + 0].gpr[z * 2 + j] = bass_gpr + z * 2 + j;
1587
			controls[nctl + 1].gpr[z * 2 + j] = treble_gpr + z * 2 + j;
1588
		}
1589
	}
1590
	nctl += 2;
1591

1592
	A_OP(icode, &ptr, iACC3, A_C_00000000, A_GPR(gpr), A_C_00000000, A_C_00000000);
1593
	snd_emu10k1_init_mono_onoff_control(controls + nctl++, "Tone Control - Switch", gpr, 0);
1594
	gpr++;
1595
	A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_CC_REG_ZERO, A_GPR(gpr));
1596
	ptr_skip = ptr;
1597
	for (z = 0; z < 4; z++) {		/* front/rear/center-lfe/side */
1598
		int j, k, l, d;
1599
		for (j = 0; j < 2; j++) {	/* left/right */
1600
			k = bass_tmp + (z * 8) + (j * 4);
1601
			l = treble_tmp + (z * 8) + (j * 4);
1602
			d = playback + z * 2 + j;
1603

1604
			A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(d), A_GPR(bass_gpr + 0 + j));
1605
			A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(bass_gpr + 4 + j));
1606
			A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(bass_gpr + 2 + j));
1607
			A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(bass_gpr + 8 + j));
1608
			A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(bass_gpr + 6 + j));
1609
			A_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000);
1610

1611
			A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(treble_gpr + 0 + j));
1612
			A_OP(icode, &ptr, iMACMV, A_GPR(l+1), A_GPR(l), A_GPR(l+1), A_GPR(treble_gpr + 4 + j));
1613
			A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(treble_gpr + 2 + j));
1614
			A_OP(icode, &ptr, iMACMV, A_GPR(l+3), A_GPR(l+2), A_GPR(l+3), A_GPR(treble_gpr + 8 + j));
1615
			A_OP(icode, &ptr, iMAC0, A_GPR(l+2), A_GPR_ACCU, A_GPR(l+2), A_GPR(treble_gpr + 6 + j));
1616
			A_OP(icode, &ptr, iMACINT0, A_GPR(l+2), A_C_00000000, A_GPR(l+2), A_C_00000010);
1617

1618
			A_OP(icode, &ptr, iACC3, A_GPR(d), A_GPR(l+2), A_C_00000000, A_C_00000000);
1619

1620
			if (z == 2)	/* center */
1621
				break;
1622
		}
1623
	}
1624
	gpr_map[gpr++] = ptr - ptr_skip;
1625

1626
	/* Master volume (will be renamed later) */
1627
	for (z = 0; z < 8; z++)
1628
		A_OP(icode, &ptr, iMAC1, A_GPR(playback+z), A_C_00000000, A_GPR(gpr), A_GPR(playback+z));
1629
	snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0);
1630
	gpr++;
1631

1632
	if (emu->card_capabilities->emu_model) {
1633
		/* EMU1010 Outputs from PCM Front, Rear, Center, LFE, Side */
1634
		dev_info(emu->card->dev, "EMU outputs on\n");
1635
		for (z = 0; z < 8; z++) {
1636
			if (emu->card_capabilities->ca0108_chip) {
1637
				A_OP(icode, &ptr, iACC3, A3_EMU32OUT(z), A_GPR(playback + z), A_C_00000000, A_C_00000000);
1638
			} else {
1639
				A_OP(icode, &ptr, iACC3, A_EMU32OUTL(z), A_GPR(playback + z), A_C_00000000, A_C_00000000);
1640
			}
1641
		}
1642
	} else {
1643
		/* analog speakers */
1644
		A_PUT_STEREO_OUTPUT(A_EXTOUT_AFRONT_L, A_EXTOUT_AFRONT_R, playback);
1645
		A_PUT_STEREO_OUTPUT(A_EXTOUT_AREAR_L, A_EXTOUT_AREAR_R, playback+2);
1646
		A_PUT_OUTPUT(A_EXTOUT_ACENTER, playback+4);
1647
		A_PUT_OUTPUT(A_EXTOUT_ALFE, playback+5);
1648
		if (emu->card_capabilities->spk71)
1649
			A_PUT_STEREO_OUTPUT(A_EXTOUT_ASIDE_L, A_EXTOUT_ASIDE_R, playback+6);
1650

1651
		/* headphone */
1652
		A_PUT_STEREO_OUTPUT(A_EXTOUT_HEADPHONE_L, A_EXTOUT_HEADPHONE_R, playback);
1653

1654
		/* IEC958 Optical Raw Playback Switch */
1655
		gpr_map[gpr++] = 0;
1656
		gpr_map[gpr++] = 0x1008;
1657
		gpr_map[gpr++] = 0xffff0000;
1658
		for (z = 0; z < 2; z++) {
1659
			A_OP(icode, &ptr, iMAC0, A_GPR(tmp + 2), A_FXBUS(FXBUS_PT_LEFT + z), A_C_00000000, A_C_00000000);
1660
			A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_GPR(gpr - 2), A_C_00000001);
1661
			A_OP(icode, &ptr, iACC3, A_GPR(tmp + 2), A_C_00000000, A_C_00010000, A_GPR(tmp + 2));
1662
			A_OP(icode, &ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_GPR(gpr - 1), A_C_00000000);
1663
			A_SWITCH(icode, &ptr, tmp + 0, tmp + 2, gpr + z);
1664
			A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
1665
			A_SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
1666
			if ((z==1) && (emu->card_capabilities->spdif_bug)) {
1667
				/* Due to a SPDIF output bug on some Audigy cards, this code delays the Right channel by 1 sample */
1668
				dev_info(emu->card->dev,
1669
					 "Installing spdif_bug patch: %s\n",
1670
					 emu->card_capabilities->name);
1671
				A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(gpr - 3), A_C_00000000, A_C_00000000);
1672
				A_OP(icode, &ptr, iACC3, A_GPR(gpr - 3), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
1673
			} else {
1674
				A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
1675
			}
1676
		}
1677
		snd_emu10k1_init_stereo_onoff_control(controls + nctl++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
1678
		gpr += 2;
1679

1680
		A_PUT_STEREO_OUTPUT(A_EXTOUT_REAR_L, A_EXTOUT_REAR_R, playback+2);
1681
		A_PUT_OUTPUT(A_EXTOUT_CENTER, playback+4);
1682
		A_PUT_OUTPUT(A_EXTOUT_LFE, playback+5);
1683
	}
1684

1685
	/* ADC buffer */
1686
#ifdef EMU10K1_CAPTURE_DIGITAL_OUT
1687
	A_PUT_STEREO_OUTPUT(A_EXTOUT_ADC_CAP_L, A_EXTOUT_ADC_CAP_R, playback);
1688
#else
1689
	A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_L, capture);
1690
	A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_R, capture+1);
1691
#endif
1692

1693
	if (emu->card_capabilities->emu_model) {
1694
		/* Capture 16 channels of S32_LE sound. */
1695
		if (emu->card_capabilities->ca0108_chip) {
1696
			dev_info(emu->card->dev, "EMU2 inputs on\n");
1697
			/* Note that the Tina[2] DSPs have 16 more EMU32 inputs which we don't use. */
1698

1699
			snd_emu10k1_audigy_dsp_convert_32_to_2x16(
1700
				icode, &ptr, tmp, bit_shifter16, A3_EMU32IN(0), A_FXBUS2(0));
1701
			// A3_EMU32IN(0) is delayed by one sample, so all other A3_EMU32IN channels
1702
			// need to be delayed as well; we use an auxiliary register for that.
1703
			for (z = 1; z < 0x10; z++) {
1704
				snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, 
1705
									bit_shifter16,
1706
									A_GPR(gpr),
1707
									A_FXBUS2(z*2) );
1708
				A_OP(icode, &ptr, iACC3, A_GPR(gpr), A3_EMU32IN(z), A_C_00000000, A_C_00000000);
1709
				gpr_map[gpr++] = 0x00000000;
1710
			}
1711
		} else {
1712
			dev_info(emu->card->dev, "EMU inputs on\n");
1713
			/* Note that the Alice2 DSPs have 6 I2S inputs which we don't use. */
1714

1715
			/*
1716
			dev_dbg(emu->card->dev, "emufx.c: gpr=0x%x, tmp=0x%x\n",
1717
			       gpr, tmp);
1718
			*/
1719
			snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) );
1720
			/* A_P16VIN(0) is delayed by one sample, so all other A_P16VIN channels
1721
			 * will need to also be delayed; we use an auxiliary register for that. */
1722
			for (z = 1; z < 0x10; z++) {
1723
				snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr), A_FXBUS2(z * 2) );
1724
				A_OP(icode, &ptr, iACC3, A_GPR(gpr), A_P16VIN(z), A_C_00000000, A_C_00000000);
1725
				gpr_map[gpr++] = 0x00000000;
1726
			}
1727
		}
1728

1729
#if 0
1730
		for (z = 4; z < 8; z++) {
1731
			A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
1732
		}
1733
		for (z = 0xc; z < 0x10; z++) {
1734
			A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
1735
		}
1736
#endif
1737
	} else {
1738
		/* EFX capture - capture the 16 EXTINs */
1739
		/* Capture 16 channels of S16_LE sound */
1740
		for (z = 0; z < 16; z++) {
1741
			A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_EXTIN(z));
1742
		}
1743
	}
1744
	
1745
#endif /* JCD test */
1746
	/*
1747
	 * ok, set up done..
1748
	 */
1749

1750
	if (gpr > 512) {
1751
		snd_BUG();
1752
		err = -EIO;
1753
		goto __err;
1754
	}
1755

1756
	/* clear remaining instruction memory */
1757
	while (ptr < 0x400)
1758
		A_OP(icode, &ptr, 0x0f, 0xc0, 0xc0, 0xcf, 0xc0);
1759

1760
	icode->gpr_add_control_count = nctl;
1761
	icode->gpr_add_controls = controls;
1762
	emu->support_tlv = 1; /* support TLV */
1763
	err = snd_emu10k1_icode_poke(emu, icode, true);
1764
	emu->support_tlv = 0; /* clear again */
1765

1766
__err:
1767
	kfree(controls);
1768
__err_ctrls:
1769
	kfree(icode->gpr_map);
1770
__err_gpr:
1771
	kfree(icode);
1772
	return err;
1773
}
1774

1775

1776
/*
1777
 * initial DSP configuration for Emu10k1
1778
 */
1779

1780
/* Volumes are in the [-2^31, 0] range, zero being mute. */
1781
static void _volume(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
1782
{
1783
	OP(icode, ptr, iMAC1, dst, C_00000000, src, vol);
1784
}
1785
static void _volume_add(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
1786
{
1787
	OP(icode, ptr, iMAC1, dst, dst, src, vol);
1788
}
1789

1790
#define VOLUME(icode, ptr, dst, src, vol) \
1791
		_volume(icode, ptr, GPR(dst), GPR(src), GPR(vol))
1792
#define VOLUME_IN(icode, ptr, dst, src, vol) \
1793
		_volume(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
1794
#define VOLUME_ADD(icode, ptr, dst, src, vol) \
1795
		_volume_add(icode, ptr, GPR(dst), GPR(src), GPR(vol))
1796
#define VOLUME_ADDIN(icode, ptr, dst, src, vol) \
1797
		_volume_add(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
1798
#define VOLUME_OUT(icode, ptr, dst, src, vol) \
1799
		_volume(icode, ptr, EXTOUT(dst), GPR(src), GPR(vol))
1800
#define _SWITCH(icode, ptr, dst, src, sw) \
1801
	OP((icode), ptr, iMACINT0, dst, C_00000000, src, sw);
1802
#define SWITCH(icode, ptr, dst, src, sw) \
1803
		_SWITCH(icode, ptr, GPR(dst), GPR(src), GPR(sw))
1804
#define SWITCH_IN(icode, ptr, dst, src, sw) \
1805
		_SWITCH(icode, ptr, GPR(dst), EXTIN(src), GPR(sw))
1806
#define _SWITCH_NEG(icode, ptr, dst, src) \
1807
	OP((icode), ptr, iANDXOR, dst, src, C_00000001, C_00000001);
1808
#define SWITCH_NEG(icode, ptr, dst, src) \
1809
		_SWITCH_NEG(icode, ptr, GPR(dst), GPR(src))
1810

1811

1812
static int _snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
1813
{
1814
	int err, i, z, gpr, tmp, playback, capture;
1815
	u32 ptr, ptr_skip;
1816
	struct snd_emu10k1_fx8010_code *icode;
1817
	struct snd_emu10k1_fx8010_pcm_rec *ipcm = NULL;
1818
	struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
1819
	u32 *gpr_map;
1820

1821
	err = -ENOMEM;
1822
	icode = kzalloc(sizeof(*icode), GFP_KERNEL);
1823
	if (!icode)
1824
		return err;
1825

1826
	icode->gpr_map = kcalloc(256 + 160 + 160 + 2 * 512,
1827
				 sizeof(u_int32_t), GFP_KERNEL);
1828
	if (!icode->gpr_map)
1829
		goto __err_gpr;
1830

1831
	controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
1832
			   sizeof(struct snd_emu10k1_fx8010_control_gpr),
1833
			   GFP_KERNEL);
1834
	if (!controls)
1835
		goto __err_ctrls;
1836

1837
	ipcm = kzalloc(sizeof(*ipcm), GFP_KERNEL);
1838
	if (!ipcm)
1839
		goto __err_ipcm;
1840

1841
	gpr_map = icode->gpr_map;
1842

1843
	icode->tram_data_map = icode->gpr_map + 256;
1844
	icode->tram_addr_map = icode->tram_data_map + 160;
1845
	icode->code = icode->tram_addr_map + 160;
1846
	
1847
	/* clear free GPRs */
1848
	memset(icode->gpr_valid, 0xff, 256 / 8);
1849

1850
	/* clear TRAM data & address lines */
1851
	memset(icode->tram_valid, 0xff, 160 / 8);
1852

1853
	strscpy(icode->name, "SB Live! FX8010 code for ALSA v1.2 by Jaroslav Kysela");
1854
	ptr = 0; i = 0;
1855
	/* we have 12 inputs */
1856
	playback = SND_EMU10K1_INPUTS;
1857
	/* we have 6 playback channels and tone control doubles */
1858
	capture = playback + SND_EMU10K1_PLAYBACK_CHANNELS;
1859
	gpr = capture + SND_EMU10K1_CAPTURE_CHANNELS;
1860
	tmp = 0x88;	/* we need 4 temporary GPR */
1861
	/* from 0x8c to 0xff is the area for tone control */
1862

1863
	/*
1864
	 *  Process FX Buses
1865
	 */
1866
	OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000008);
1867
	OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000008);
1868
	OP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_00000008);
1869
	OP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_00000008);
1870
	OP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_00000008);
1871
	OP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_00000008);
1872
	OP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_00000008);
1873
	OP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_00000008);
1874
	OP(icode, &ptr, iMACINT0, GPR(8), C_00000000, C_00000000, C_00000000);	/* S/PDIF left */
1875
	OP(icode, &ptr, iMACINT0, GPR(9), C_00000000, C_00000000, C_00000000);	/* S/PDIF right */
1876
	OP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_00000008);
1877
	OP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_00000008);
1878

1879
	/* Raw S/PDIF PCM */
1880
	ipcm->substream = 0;
1881
	ipcm->channels = 2;
1882
	ipcm->tram_start = 0;
1883
	ipcm->buffer_size = (64 * 1024) / 2;
1884
	ipcm->gpr_size = gpr++;
1885
	ipcm->gpr_ptr = gpr++;
1886
	ipcm->gpr_count = gpr++;
1887
	ipcm->gpr_tmpcount = gpr++;
1888
	ipcm->gpr_trigger = gpr++;
1889
	ipcm->gpr_running = gpr++;
1890
	ipcm->etram[0] = 0;
1891
	ipcm->etram[1] = 1;
1892

1893
	gpr_map[gpr + 0] = 0xfffff000;
1894
	gpr_map[gpr + 1] = 0xffff0000;
1895
	gpr_map[gpr + 2] = 0x70000000;
1896
	gpr_map[gpr + 3] = 0x00000007;
1897
	gpr_map[gpr + 4] = 0x001f << 11;
1898
	gpr_map[gpr + 5] = 0x001c << 11;
1899
	gpr_map[gpr + 6] = (0x22  - 0x01) - 1;	/* skip at 01 to 22 */
1900
	gpr_map[gpr + 7] = (0x22  - 0x06) - 1;	/* skip at 06 to 22 */
1901
	gpr_map[gpr + 8] = 0x2000000 + (2<<11);
1902
	gpr_map[gpr + 9] = 0x4000000 + (2<<11);
1903
	gpr_map[gpr + 10] = 1<<11;
1904
	gpr_map[gpr + 11] = (0x24 - 0x0a) - 1;	/* skip at 0a to 24 */
1905
	gpr_map[gpr + 12] = 0;
1906

1907
	/* if the trigger flag is not set, skip */
1908
	/* 00: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_trigger), C_00000000, C_00000000);
1909
	/* 01: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr + 6));
1910
	/* if the running flag is set, we're running */
1911
	/* 02: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_running), C_00000000, C_00000000);
1912
	/* 03: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000004);
1913
	/* wait until ((GPR_DBAC>>11) & 0x1f) == 0x1c) */
1914
	/* 04: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), GPR_DBAC, GPR(gpr + 4), C_00000000);
1915
	/* 05: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(gpr + 5));
1916
	/* 06: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 7));
1917
	/* 07: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000010, C_00000001, C_00000000);
1918

1919
	/* 08: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000000, C_00000001);
1920
	/* 09: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), GPR(gpr + 12), C_ffffffff, C_00000000);
1921
	/* 0a: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 11));
1922
	/* 0b: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000001, C_00000000, C_00000000);
1923

1924
	/* 0c: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[0]), GPR(gpr + 0), C_00000000);
1925
	/* 0d: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
1926
	/* 0e: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
1927
	/* 0f: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
1928
	/* 10: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(8), GPR(gpr + 1), GPR(gpr + 2));
1929

1930
	/* 11: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[1]), GPR(gpr + 0), C_00000000);
1931
	/* 12: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
1932
	/* 13: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
1933
	/* 14: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
1934
	/* 15: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(9), GPR(gpr + 1), GPR(gpr + 2));
1935

1936
	/* 16: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(ipcm->gpr_ptr), C_00000001, C_00000000);
1937
	/* 17: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(ipcm->gpr_size));
1938
	/* 18: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_MINUS, C_00000001);
1939
	/* 19: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), C_00000000, C_00000000, C_00000000);
1940
	/* 1a: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_ptr), GPR(tmp + 0), C_00000000, C_00000000);
1941
	
1942
	/* 1b: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_tmpcount), C_ffffffff, C_00000000);
1943
	/* 1c: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
1944
	/* 1d: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_count), C_00000000, C_00000000);
1945
	/* 1e: */ OP(icode, &ptr, iACC3, GPR_IRQ, C_80000000, C_00000000, C_00000000);
1946
	/* 1f: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000001, C_00010000);
1947

1948
	/* 20: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00010000, C_00000001);
1949
	/* 21: */ OP(icode, &ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000002);
1950

1951
	/* 22: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[0]), GPR(gpr + 8), GPR_DBAC, C_ffffffff);
1952
	/* 23: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[1]), GPR(gpr + 9), GPR_DBAC, C_ffffffff);
1953

1954
	/* 24: */
1955
	gpr += 13;
1956

1957
	/* Wave Playback Volume */
1958
	for (z = 0; z < 2; z++)
1959
		VOLUME(icode, &ptr, playback + z, z, gpr + z);
1960
	snd_emu10k1_init_stereo_control(controls + i++, "Wave Playback Volume", gpr, 100);
1961
	gpr += 2;
1962

1963
	/* Wave Surround Playback Volume */
1964
	for (z = 0; z < 2; z++)
1965
		VOLUME(icode, &ptr, playback + 2 + z, z, gpr + z);
1966
	snd_emu10k1_init_stereo_control(controls + i++, "Wave Surround Playback Volume", gpr, 0);
1967
	gpr += 2;
1968
	
1969
	/* Wave Center/LFE Playback Volume */
1970
	OP(icode, &ptr, iACC3, GPR(tmp + 0), FXBUS(FXBUS_PCM_LEFT), FXBUS(FXBUS_PCM_RIGHT), C_00000000);
1971
	OP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_00000004);
1972
	VOLUME(icode, &ptr, playback + 4, tmp + 0, gpr);
1973
	snd_emu10k1_init_mono_control(controls + i++, "Wave Center Playback Volume", gpr++, 0);
1974
	VOLUME(icode, &ptr, playback + 5, tmp + 0, gpr);
1975
	snd_emu10k1_init_mono_control(controls + i++, "Wave LFE Playback Volume", gpr++, 0);
1976

1977
	/* Wave Capture Volume + Switch */
1978
	for (z = 0; z < 2; z++) {
1979
		SWITCH(icode, &ptr, tmp + 0, z, gpr + 2 + z);
1980
		VOLUME(icode, &ptr, capture + z, tmp + 0, gpr + z);
1981
	}
1982
	snd_emu10k1_init_stereo_control(controls + i++, "Wave Capture Volume", gpr, 0);
1983
	snd_emu10k1_init_stereo_onoff_control(controls + i++, "Wave Capture Switch", gpr + 2, 0);
1984
	gpr += 4;
1985

1986
	/* Synth Playback Volume */
1987
	for (z = 0; z < 2; z++)
1988
		VOLUME_ADD(icode, &ptr, playback + z, 2 + z, gpr + z);
1989
	snd_emu10k1_init_stereo_control(controls + i++, "Synth Playback Volume", gpr, 100);
1990
	gpr += 2;
1991

1992
	/* Synth Capture Volume + Switch */
1993
	for (z = 0; z < 2; z++) {
1994
		SWITCH(icode, &ptr, tmp + 0, 2 + z, gpr + 2 + z);
1995
		VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
1996
	}
1997
	snd_emu10k1_init_stereo_control(controls + i++, "Synth Capture Volume", gpr, 0);
1998
	snd_emu10k1_init_stereo_onoff_control(controls + i++, "Synth Capture Switch", gpr + 2, 0);
1999
	gpr += 4;
2000

2001
	/* Surround Digital Playback Volume (renamed later without Digital) */
2002
	for (z = 0; z < 2; z++)
2003
		VOLUME_ADD(icode, &ptr, playback + 2 + z, 4 + z, gpr + z);
2004
	snd_emu10k1_init_stereo_control(controls + i++, "Surround Digital Playback Volume", gpr, 100);
2005
	gpr += 2;
2006

2007
	/* Surround Capture Volume + Switch */
2008
	for (z = 0; z < 2; z++) {
2009
		SWITCH(icode, &ptr, tmp + 0, 4 + z, gpr + 2 + z);
2010
		VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2011
	}
2012
	snd_emu10k1_init_stereo_control(controls + i++, "Surround Capture Volume", gpr, 0);
2013
	snd_emu10k1_init_stereo_onoff_control(controls + i++, "Surround Capture Switch", gpr + 2, 0);
2014
	gpr += 4;
2015

2016
	/* Center Playback Volume (renamed later without Digital) */
2017
	VOLUME_ADD(icode, &ptr, playback + 4, 6, gpr);
2018
	snd_emu10k1_init_mono_control(controls + i++, "Center Digital Playback Volume", gpr++, 100);
2019

2020
	/* LFE Playback Volume + Switch (renamed later without Digital) */
2021
	VOLUME_ADD(icode, &ptr, playback + 5, 7, gpr);
2022
	snd_emu10k1_init_mono_control(controls + i++, "LFE Digital Playback Volume", gpr++, 100);
2023

2024
	/* Front Playback Volume */
2025
	for (z = 0; z < 2; z++)
2026
		VOLUME_ADD(icode, &ptr, playback + z, 10 + z, gpr + z);
2027
	snd_emu10k1_init_stereo_control(controls + i++, "Front Playback Volume", gpr, 100);
2028
	gpr += 2;
2029

2030
	/* Front Capture Volume + Switch */
2031
	for (z = 0; z < 2; z++) {
2032
		SWITCH(icode, &ptr, tmp + 0, 10 + z, gpr + 2);
2033
		VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2034
	}
2035
	snd_emu10k1_init_stereo_control(controls + i++, "Front Capture Volume", gpr, 0);
2036
	snd_emu10k1_init_mono_onoff_control(controls + i++, "Front Capture Switch", gpr + 2, 0);
2037
	gpr += 3;
2038

2039
	/*
2040
	 *  Process inputs
2041
	 */
2042

2043
	if (emu->fx8010.extin_mask & ((1<<EXTIN_AC97_L)|(1<<EXTIN_AC97_R))) {
2044
		/* AC'97 Playback Volume */
2045
		VOLUME_ADDIN(icode, &ptr, playback + 0, EXTIN_AC97_L, gpr); gpr++;
2046
		VOLUME_ADDIN(icode, &ptr, playback + 1, EXTIN_AC97_R, gpr); gpr++;
2047
		snd_emu10k1_init_stereo_control(controls + i++, "AC97 Playback Volume", gpr-2, 0);
2048
		/* AC'97 Capture Volume */
2049
		VOLUME_ADDIN(icode, &ptr, capture + 0, EXTIN_AC97_L, gpr); gpr++;
2050
		VOLUME_ADDIN(icode, &ptr, capture + 1, EXTIN_AC97_R, gpr); gpr++;
2051
		snd_emu10k1_init_stereo_control(controls + i++, "AC97 Capture Volume", gpr-2, 100);
2052
	}
2053
	
2054
	if (emu->fx8010.extin_mask & ((1<<EXTIN_SPDIF_CD_L)|(1<<EXTIN_SPDIF_CD_R))) {
2055
		/* IEC958 TTL Playback Volume */
2056
		for (z = 0; z < 2; z++)
2057
			VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_SPDIF_CD_L + z, gpr + z);
2058
		snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",PLAYBACK,VOLUME), gpr, 0);
2059
		gpr += 2;
2060
	
2061
		/* IEC958 TTL Capture Volume + Switch */
2062
		for (z = 0; z < 2; z++) {
2063
			SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_SPDIF_CD_L + z, gpr + 2 + z);
2064
			VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2065
		}
2066
		snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,VOLUME), gpr, 0);
2067
		snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,SWITCH), gpr + 2, 0);
2068
		gpr += 4;
2069
	}
2070
	
2071
	if (emu->fx8010.extin_mask & ((1<<EXTIN_ZOOM_L)|(1<<EXTIN_ZOOM_R))) {
2072
		/* Zoom Video Playback Volume */
2073
		for (z = 0; z < 2; z++)
2074
			VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_ZOOM_L + z, gpr + z);
2075
		snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Playback Volume", gpr, 0);
2076
		gpr += 2;
2077
	
2078
		/* Zoom Video Capture Volume + Switch */
2079
		for (z = 0; z < 2; z++) {
2080
			SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_ZOOM_L + z, gpr + 2 + z);
2081
			VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2082
		}
2083
		snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Capture Volume", gpr, 0);
2084
		snd_emu10k1_init_stereo_onoff_control(controls + i++, "Zoom Video Capture Switch", gpr + 2, 0);
2085
		gpr += 4;
2086
	}
2087
	
2088
	if (emu->fx8010.extin_mask & ((1<<EXTIN_TOSLINK_L)|(1<<EXTIN_TOSLINK_R))) {
2089
		/* IEC958 Optical Playback Volume */
2090
		for (z = 0; z < 2; z++)
2091
			VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_TOSLINK_L + z, gpr + z);
2092
		snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",PLAYBACK,VOLUME), gpr, 0);
2093
		gpr += 2;
2094
	
2095
		/* IEC958 Optical Capture Volume */
2096
		for (z = 0; z < 2; z++) {
2097
			SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_TOSLINK_L + z, gpr + 2 + z);
2098
			VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2099
		}
2100
		snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,VOLUME), gpr, 0);
2101
		snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,SWITCH), gpr + 2, 0);
2102
		gpr += 4;
2103
	}
2104
	
2105
	if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE1_L)|(1<<EXTIN_LINE1_R))) {
2106
		/* Line LiveDrive Playback Volume */
2107
		for (z = 0; z < 2; z++)
2108
			VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE1_L + z, gpr + z);
2109
		snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Playback Volume", gpr, 0);
2110
		gpr += 2;
2111
	
2112
		/* Line LiveDrive Capture Volume + Switch */
2113
		for (z = 0; z < 2; z++) {
2114
			SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE1_L + z, gpr + 2 + z);
2115
			VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2116
		}
2117
		snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Capture Volume", gpr, 0);
2118
		snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line LiveDrive Capture Switch", gpr + 2, 0);
2119
		gpr += 4;
2120
	}
2121
	
2122
	if (emu->fx8010.extin_mask & ((1<<EXTIN_COAX_SPDIF_L)|(1<<EXTIN_COAX_SPDIF_R))) {
2123
		/* IEC958 Coax Playback Volume */
2124
		for (z = 0; z < 2; z++)
2125
			VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_COAX_SPDIF_L + z, gpr + z);
2126
		snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",PLAYBACK,VOLUME), gpr, 0);
2127
		gpr += 2;
2128
	
2129
		/* IEC958 Coax Capture Volume + Switch */
2130
		for (z = 0; z < 2; z++) {
2131
			SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_COAX_SPDIF_L + z, gpr + 2 + z);
2132
			VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2133
		}
2134
		snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,VOLUME), gpr, 0);
2135
		snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,SWITCH), gpr + 2, 0);
2136
		gpr += 4;
2137
	}
2138
	
2139
	if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE2_L)|(1<<EXTIN_LINE2_R))) {
2140
		/* Line LiveDrive Playback Volume */
2141
		for (z = 0; z < 2; z++)
2142
			VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE2_L + z, gpr + z);
2143
		snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Playback Volume", gpr, 0);
2144
		controls[i-1].id.index = 1;
2145
		gpr += 2;
2146
	
2147
		/* Line LiveDrive Capture Volume */
2148
		for (z = 0; z < 2; z++) {
2149
			SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE2_L + z, gpr + 2 + z);
2150
			VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
2151
		}
2152
		snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Capture Volume", gpr, 0);
2153
		controls[i-1].id.index = 1;
2154
		snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line2 LiveDrive Capture Switch", gpr + 2, 0);
2155
		controls[i-1].id.index = 1;
2156
		gpr += 4;
2157
	}
2158

2159
	/*
2160
	 *  Process tone control
2161
	 */
2162
	ctl = &controls[i + 0];
2163
	ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
2164
	strscpy(ctl->id.name, "Tone Control - Bass");
2165
	ctl->vcount = 2;
2166
	ctl->count = 10;
2167
	ctl->min = 0;
2168
	ctl->max = 40;
2169
	ctl->value[0] = ctl->value[1] = 20;
2170
	ctl->tlv = snd_emu10k1_bass_treble_db_scale;
2171
	ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
2172
	ctl = &controls[i + 1];
2173
	ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER;
2174
	strscpy(ctl->id.name, "Tone Control - Treble");
2175
	ctl->vcount = 2;
2176
	ctl->count = 10;
2177
	ctl->min = 0;
2178
	ctl->max = 40;
2179
	ctl->value[0] = ctl->value[1] = 20;
2180
	ctl->tlv = snd_emu10k1_bass_treble_db_scale;
2181
	ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
2182

2183
#define BASS_GPR	0x8c
2184
#define TREBLE_GPR	0x96
2185

2186
	for (z = 0; z < 5; z++) {
2187
		int j;
2188
		for (j = 0; j < 2; j++) {
2189
			controls[i + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
2190
			controls[i + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
2191
		}
2192
	}
2193
	i += 2;
2194

2195
	OP(icode, &ptr, iACC3, C_00000000, GPR(gpr), C_00000000, C_00000000);
2196
	snd_emu10k1_init_mono_onoff_control(controls + i++, "Tone Control - Switch", gpr, 0);
2197
	gpr++;
2198
	OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr));
2199
	ptr_skip = ptr;
2200
	for (z = 0; z < 3; z++) {		/* front/rear/center-lfe */
2201
		int j, k, l, d;
2202
		for (j = 0; j < 2; j++) {	/* left/right */
2203
			k = 0xa0 + (z * 8) + (j * 4);
2204
			l = 0xd0 + (z * 8) + (j * 4);
2205
			d = playback + z * 2 + j;
2206

2207
			OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(d), GPR(BASS_GPR + 0 + j));
2208
			OP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j));
2209
			OP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j));
2210
			OP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j));
2211
			OP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j));
2212
			OP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000);
2213

2214
			OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j));
2215
			OP(icode, &ptr, iMACMV, GPR(l+1), GPR(l), GPR(l+1), GPR(TREBLE_GPR + 4 + j));
2216
			OP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j));
2217
			OP(icode, &ptr, iMACMV, GPR(l+3), GPR(l+2), GPR(l+3), GPR(TREBLE_GPR + 8 + j));
2218
			OP(icode, &ptr, iMAC0, GPR(l+2), GPR_ACCU, GPR(l+2), GPR(TREBLE_GPR + 6 + j));
2219
			OP(icode, &ptr, iMACINT0, GPR(l+2), C_00000000, GPR(l+2), C_00000010);
2220

2221
			OP(icode, &ptr, iACC3, GPR(d), GPR(l+2), C_00000000, C_00000000);
2222

2223
			if (z == 2)	/* center */
2224
				break;
2225
		}
2226
	}
2227
	gpr_map[gpr++] = ptr - ptr_skip;
2228

2229
#undef BASS_GPR
2230
#undef TREBLE_GPR
2231

2232
	/*
2233
	 *  Process outputs
2234
	 */
2235
	if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_L)|(1<<EXTOUT_AC97_R))) {
2236
		/* AC'97 Playback Volume */
2237

2238
		for (z = 0; z < 2; z++)
2239
			OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + z), C_00000000, C_00000000);
2240
	}
2241

2242
	if (emu->fx8010.extout_mask & ((1<<EXTOUT_TOSLINK_L)|(1<<EXTOUT_TOSLINK_R))) {
2243
		/* IEC958 Optical Raw Playback Switch */
2244

2245
		for (z = 0; z < 2; z++) {
2246
			SWITCH(icode, &ptr, tmp + 0, 8 + z, gpr + z);
2247
			SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
2248
			SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
2249
			OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_TOSLINK_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
2250
#ifdef EMU10K1_CAPTURE_DIGITAL_OUT
2251
	 		OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
2252
#endif
2253
		}
2254

2255
		snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
2256
		gpr += 2;
2257
	}
2258

2259
	if (emu->fx8010.extout_mask & ((1<<EXTOUT_HEADPHONE_L)|(1<<EXTOUT_HEADPHONE_R))) {
2260
		/* Headphone Playback Volume */
2261

2262
		for (z = 0; z < 2; z++) {
2263
			SWITCH(icode, &ptr, tmp + 0, playback + 4 + z, gpr + 2 + z);
2264
			SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 2 + z);
2265
			SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
2266
			OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
2267
			VOLUME_OUT(icode, &ptr, EXTOUT_HEADPHONE_L + z, tmp + 0, gpr + z);
2268
		}
2269

2270
		snd_emu10k1_init_stereo_control(controls + i++, "Headphone Playback Volume", gpr + 0, 0);
2271
		controls[i-1].id.index = 1;	/* AC'97 can have also Headphone control */
2272
		snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone Center Playback Switch", gpr + 2, 0);
2273
		controls[i-1].id.index = 1;
2274
		snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone LFE Playback Switch", gpr + 3, 0);
2275
		controls[i-1].id.index = 1;
2276

2277
		gpr += 4;
2278
	}
2279
	
2280
	if (emu->fx8010.extout_mask & ((1<<EXTOUT_REAR_L)|(1<<EXTOUT_REAR_R)))
2281
		for (z = 0; z < 2; z++)
2282
			OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + 2 + z), C_00000000, C_00000000);
2283

2284
	if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_REAR_L)|(1<<EXTOUT_AC97_REAR_R)))
2285
		for (z = 0; z < 2; z++)
2286
			OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + 2 + z), C_00000000, C_00000000);
2287

2288
	if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_CENTER)) {
2289
#ifndef EMU10K1_CENTER_LFE_FROM_FRONT
2290
		OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + 4), C_00000000, C_00000000);
2291
		OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + 4), C_00000000, C_00000000);
2292
#else
2293
		OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + 0), C_00000000, C_00000000);
2294
		OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + 0), C_00000000, C_00000000);
2295
#endif
2296
	}
2297

2298
	if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_LFE)) {
2299
#ifndef EMU10K1_CENTER_LFE_FROM_FRONT
2300
		OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + 5), C_00000000, C_00000000);
2301
		OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + 5), C_00000000, C_00000000);
2302
#else
2303
		OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + 1), C_00000000, C_00000000);
2304
		OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + 1), C_00000000, C_00000000);
2305
#endif
2306
	}
2307
	
2308
#ifndef EMU10K1_CAPTURE_DIGITAL_OUT
2309
	for (z = 0; z < 2; z++)
2310
 		OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(capture + z), C_00000000, C_00000000);
2311
#endif
2312
	
2313
	if (emu->fx8010.extout_mask & (1<<EXTOUT_MIC_CAP))
2314
		OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_MIC_CAP), GPR(capture + 2), C_00000000, C_00000000);
2315

2316
	/* EFX capture - capture the 16 EXTINS */
2317
	if (emu->card_capabilities->sblive51) {
2318
		for (z = 0; z < 16; z++) {
2319
			s8 c = snd_emu10k1_sblive51_fxbus2_map[z];
2320
			if (c != -1)
2321
				OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(c));
2322
		}
2323
	} else {
2324
		for (z = 0; z < 16; z++)
2325
			OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
2326
	}
2327
	    
2328

2329
	if (gpr > tmp) {
2330
		snd_BUG();
2331
		err = -EIO;
2332
		goto __err;
2333
	}
2334
	if (i > SND_EMU10K1_GPR_CONTROLS) {
2335
		snd_BUG();
2336
		err = -EIO;
2337
		goto __err;
2338
	}
2339
	
2340
	/* clear remaining instruction memory */
2341
	while (ptr < 0x200)
2342
		OP(icode, &ptr, iACC3, C_00000000, C_00000000, C_00000000, C_00000000);
2343

2344
	err = snd_emu10k1_fx8010_tram_setup(emu, ipcm->buffer_size);
2345
	if (err < 0)
2346
		goto __err;
2347
	icode->gpr_add_control_count = i;
2348
	icode->gpr_add_controls = controls;
2349
	emu->support_tlv = 1; /* support TLV */
2350
	err = snd_emu10k1_icode_poke(emu, icode, true);
2351
	emu->support_tlv = 0; /* clear again */
2352
	if (err >= 0)
2353
		err = snd_emu10k1_ipcm_poke(emu, ipcm);
2354
__err:
2355
	kfree(ipcm);
2356
__err_ipcm:
2357
	kfree(controls);
2358
__err_ctrls:
2359
	kfree(icode->gpr_map);
2360
__err_gpr:
2361
	kfree(icode);
2362
	return err;
2363
}
2364

2365
int snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
2366
{
2367
	spin_lock_init(&emu->fx8010.irq_lock);
2368
	INIT_LIST_HEAD(&emu->fx8010.gpr_ctl);
2369
	if (emu->audigy)
2370
		return _snd_emu10k1_audigy_init_efx(emu);
2371
	else
2372
		return _snd_emu10k1_init_efx(emu);
2373
}
2374

2375
void snd_emu10k1_free_efx(struct snd_emu10k1 *emu)
2376
{
2377
	/* stop processor */
2378
	if (emu->audigy)
2379
		snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = A_DBG_SINGLE_STEP);
2380
	else
2381
		snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = EMU10K1_DBG_SINGLE_STEP);
2382
}
2383

2384
#if 0 /* FIXME: who use them? */
2385
int snd_emu10k1_fx8010_tone_control_activate(struct snd_emu10k1 *emu, int output)
2386
{
2387
	if (output < 0 || output >= 6)
2388
		return -EINVAL;
2389
	snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 1);
2390
	return 0;
2391
}
2392

2393
int snd_emu10k1_fx8010_tone_control_deactivate(struct snd_emu10k1 *emu, int output)
2394
{
2395
	if (output < 0 || output >= 6)
2396
		return -EINVAL;
2397
	snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 0);
2398
	return 0;
2399
}
2400
#endif
2401

2402
int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size)
2403
{
2404
	u8 size_reg = 0;
2405

2406
	/* size is in samples */
2407
	if (size != 0) {
2408
		size = (size - 1) >> 13;
2409

2410
		while (size) {
2411
			size >>= 1;
2412
			size_reg++;
2413
		}
2414
		size = 0x2000 << size_reg;
2415
	}
2416
	if ((emu->fx8010.etram_pages.bytes / 2) == size)
2417
		return 0;
2418
	spin_lock_irq(&emu->emu_lock);
2419
	outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
2420
	spin_unlock_irq(&emu->emu_lock);
2421
	snd_emu10k1_ptr_write(emu, TCB, 0, 0);
2422
	snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K);
2423
	if (emu->fx8010.etram_pages.area != NULL) {
2424
		snd_dma_free_pages(&emu->fx8010.etram_pages);
2425
		emu->fx8010.etram_pages.area = NULL;
2426
		emu->fx8010.etram_pages.bytes = 0;
2427
	}
2428

2429
	if (size > 0) {
2430
		if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &emu->pci->dev,
2431
					size * 2, &emu->fx8010.etram_pages) < 0)
2432
			return -ENOMEM;
2433
		memset(emu->fx8010.etram_pages.area, 0, size * 2);
2434
		snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
2435
		snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
2436
		spin_lock_irq(&emu->emu_lock);
2437
		outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
2438
		spin_unlock_irq(&emu->emu_lock);
2439
	}
2440

2441
	return 0;
2442
}
2443

2444
static int snd_emu10k1_fx8010_open(struct snd_hwdep * hw, struct file *file)
2445
{
2446
	return 0;
2447
}
2448

2449
static void copy_string(char *dst, const char *src, const char *null, int idx)
2450
{
2451
	if (src == NULL)
2452
		sprintf(dst, "%s %02X", null, idx);
2453
	else
2454
		strcpy(dst, src);
2455
}
2456

2457
static void snd_emu10k1_fx8010_info(struct snd_emu10k1 *emu,
2458
				   struct snd_emu10k1_fx8010_info *info)
2459
{
2460
	const char * const *fxbus, * const *extin, * const *extout;
2461
	unsigned short extin_mask, extout_mask;
2462
	int res;
2463

2464
	info->internal_tram_size = emu->fx8010.itram_size;
2465
	info->external_tram_size = emu->fx8010.etram_pages.bytes / 2;
2466
	fxbus = snd_emu10k1_fxbus;
2467
	extin = emu->audigy ? snd_emu10k1_audigy_ins : snd_emu10k1_sblive_ins;
2468
	extout = emu->audigy ? snd_emu10k1_audigy_outs : snd_emu10k1_sblive_outs;
2469
	extin_mask = emu->audigy ? ~0 : emu->fx8010.extin_mask;
2470
	extout_mask = emu->audigy ? ~0 : emu->fx8010.extout_mask;
2471
	for (res = 0; res < 16; res++, fxbus++, extin++, extout++) {
2472
		copy_string(info->fxbus_names[res], *fxbus, "FXBUS", res);
2473
		copy_string(info->extin_names[res], extin_mask & (1 << res) ? *extin : NULL, "Unused", res);
2474
		copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
2475
	}
2476
	for (res = 16; res < 32; res++, extout++)
2477
		copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
2478
	info->gpr_controls = emu->fx8010.gpr_count;
2479
}
2480

2481
static int snd_emu10k1_fx8010_ioctl(struct snd_hwdep * hw, struct file *file, unsigned int cmd, unsigned long arg)
2482
{
2483
	struct snd_emu10k1 *emu = hw->private_data;
2484
	struct snd_emu10k1_fx8010_info *info;
2485
	struct snd_emu10k1_fx8010_code *icode;
2486
	struct snd_emu10k1_fx8010_pcm_rec *ipcm;
2487
	unsigned int addr;
2488
	void __user *argp = (void __user *)arg;
2489
	int res;
2490
	
2491
	switch (cmd) {
2492
	case SNDRV_EMU10K1_IOCTL_PVERSION:
2493
		emu->support_tlv = 1;
2494
		return put_user(SNDRV_EMU10K1_VERSION, (int __user *)argp);
2495
	case SNDRV_EMU10K1_IOCTL_INFO:
2496
		info = kzalloc(sizeof(*info), GFP_KERNEL);
2497
		if (!info)
2498
			return -ENOMEM;
2499
		snd_emu10k1_fx8010_info(emu, info);
2500
		if (copy_to_user(argp, info, sizeof(*info))) {
2501
			kfree(info);
2502
			return -EFAULT;
2503
		}
2504
		kfree(info);
2505
		return 0;
2506
	case SNDRV_EMU10K1_IOCTL_CODE_POKE:
2507
		if (!capable(CAP_SYS_ADMIN))
2508
			return -EPERM;
2509

2510
		icode = memdup_user(argp, sizeof(*icode));
2511
		if (IS_ERR(icode))
2512
			return PTR_ERR(icode);
2513
		res = snd_emu10k1_icode_poke(emu, icode, false);
2514
		kfree(icode);
2515
		return res;
2516
	case SNDRV_EMU10K1_IOCTL_CODE_PEEK:
2517
		icode = memdup_user(argp, sizeof(*icode));
2518
		if (IS_ERR(icode))
2519
			return PTR_ERR(icode);
2520
		res = snd_emu10k1_icode_peek(emu, icode);
2521
		if (res == 0 && copy_to_user(argp, icode, sizeof(*icode))) {
2522
			kfree(icode);
2523
			return -EFAULT;
2524
		}
2525
		kfree(icode);
2526
		return res;
2527
	case SNDRV_EMU10K1_IOCTL_PCM_POKE:
2528
		ipcm = memdup_user(argp, sizeof(*ipcm));
2529
		if (IS_ERR(ipcm))
2530
			return PTR_ERR(ipcm);
2531
		res = snd_emu10k1_ipcm_poke(emu, ipcm);
2532
		kfree(ipcm);
2533
		return res;
2534
	case SNDRV_EMU10K1_IOCTL_PCM_PEEK:
2535
		ipcm = memdup_user(argp, sizeof(*ipcm));
2536
		if (IS_ERR(ipcm))
2537
			return PTR_ERR(ipcm);
2538
		res = snd_emu10k1_ipcm_peek(emu, ipcm);
2539
		if (res == 0 && copy_to_user(argp, ipcm, sizeof(*ipcm))) {
2540
			kfree(ipcm);
2541
			return -EFAULT;
2542
		}
2543
		kfree(ipcm);
2544
		return res;
2545
	case SNDRV_EMU10K1_IOCTL_TRAM_SETUP:
2546
		if (!capable(CAP_SYS_ADMIN))
2547
			return -EPERM;
2548
		if (get_user(addr, (unsigned int __user *)argp))
2549
			return -EFAULT;
2550
		mutex_lock(&emu->fx8010.lock);
2551
		res = snd_emu10k1_fx8010_tram_setup(emu, addr);
2552
		mutex_unlock(&emu->fx8010.lock);
2553
		return res;
2554
	case SNDRV_EMU10K1_IOCTL_STOP:
2555
		if (!capable(CAP_SYS_ADMIN))
2556
			return -EPERM;
2557
		if (emu->audigy)
2558
			snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP);
2559
		else
2560
			snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP);
2561
		return 0;
2562
	case SNDRV_EMU10K1_IOCTL_CONTINUE:
2563
		if (!capable(CAP_SYS_ADMIN))
2564
			return -EPERM;
2565
		if (emu->audigy)
2566
			snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = 0);
2567
		else
2568
			snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = 0);
2569
		return 0;
2570
	case SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER:
2571
		if (!capable(CAP_SYS_ADMIN))
2572
			return -EPERM;
2573
		if (emu->audigy)
2574
			snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_ZC);
2575
		else
2576
			snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_ZC);
2577
		udelay(10);
2578
		if (emu->audigy)
2579
			snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
2580
		else
2581
			snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
2582
		return 0;
2583
	case SNDRV_EMU10K1_IOCTL_SINGLE_STEP:
2584
		if (!capable(CAP_SYS_ADMIN))
2585
			return -EPERM;
2586
		if (get_user(addr, (unsigned int __user *)argp))
2587
			return -EFAULT;
2588
		if (emu->audigy) {
2589
			if (addr > A_DBG_STEP_ADDR)
2590
				return -EINVAL;
2591
			snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP);
2592
			udelay(10);
2593
			snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_STEP | addr);
2594
		} else {
2595
			if (addr > EMU10K1_DBG_SINGLE_STEP_ADDR)
2596
				return -EINVAL;
2597
			snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP);
2598
			udelay(10);
2599
			snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_STEP | addr);
2600
		}
2601
		return 0;
2602
	case SNDRV_EMU10K1_IOCTL_DBG_READ:
2603
		if (emu->audigy)
2604
			addr = snd_emu10k1_ptr_read(emu, A_DBG, 0);
2605
		else
2606
			addr = snd_emu10k1_ptr_read(emu, DBG, 0);
2607
		if (put_user(addr, (unsigned int __user *)argp))
2608
			return -EFAULT;
2609
		return 0;
2610
	}
2611
	return -ENOTTY;
2612
}
2613

2614
static int snd_emu10k1_fx8010_release(struct snd_hwdep * hw, struct file *file)
2615
{
2616
	return 0;
2617
}
2618

2619
int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device)
2620
{
2621
	struct snd_hwdep *hw;
2622
	int err;
2623
	
2624
	err = snd_hwdep_new(emu->card, "FX8010", device, &hw);
2625
	if (err < 0)
2626
		return err;
2627
	strscpy(hw->name, "EMU10K1 (FX8010)");
2628
	hw->iface = SNDRV_HWDEP_IFACE_EMU10K1;
2629
	hw->ops.open = snd_emu10k1_fx8010_open;
2630
	hw->ops.ioctl = snd_emu10k1_fx8010_ioctl;
2631
	hw->ops.release = snd_emu10k1_fx8010_release;
2632
	hw->private_data = emu;
2633
	return 0;
2634
}
2635

2636
#ifdef CONFIG_PM_SLEEP
2637
int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu)
2638
{
2639
	int len;
2640

2641
	len = emu->audigy ? 0x200 : 0x100;
2642
	emu->saved_gpr = kmalloc_array(len, 4, GFP_KERNEL);
2643
	if (! emu->saved_gpr)
2644
		return -ENOMEM;
2645
	len = emu->audigy ? 0x100 : 0xa0;
2646
	emu->tram_val_saved = kmalloc_array(len, 4, GFP_KERNEL);
2647
	emu->tram_addr_saved = kmalloc_array(len, 4, GFP_KERNEL);
2648
	if (! emu->tram_val_saved || ! emu->tram_addr_saved)
2649
		return -ENOMEM;
2650
	len = emu->audigy ? 2 * 1024 : 2 * 512;
2651
	emu->saved_icode = vmalloc(array_size(len, 4));
2652
	if (! emu->saved_icode)
2653
		return -ENOMEM;
2654
	return 0;
2655
}
2656

2657
void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu)
2658
{
2659
	kfree(emu->saved_gpr);
2660
	kfree(emu->tram_val_saved);
2661
	kfree(emu->tram_addr_saved);
2662
	vfree(emu->saved_icode);
2663
}
2664

2665
/*
2666
 * save/restore GPR, TRAM and codes
2667
 */
2668
void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu)
2669
{
2670
	int i, len;
2671

2672
	len = emu->audigy ? 0x200 : 0x100;
2673
	for (i = 0; i < len; i++)
2674
		emu->saved_gpr[i] = snd_emu10k1_ptr_read(emu, emu->gpr_base + i, 0);
2675

2676
	len = emu->audigy ? 0x100 : 0xa0;
2677
	for (i = 0; i < len; i++) {
2678
		emu->tram_val_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + i, 0);
2679
		emu->tram_addr_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + i, 0);
2680
		if (emu->audigy) {
2681
			emu->tram_addr_saved[i] >>= 12;
2682
			emu->tram_addr_saved[i] |=
2683
				snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + i, 0) << 20;
2684
		}
2685
	}
2686

2687
	len = emu->audigy ? 2 * 1024 : 2 * 512;
2688
	for (i = 0; i < len; i++)
2689
		emu->saved_icode[i] = snd_emu10k1_efx_read(emu, i);
2690
}
2691

2692
void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu)
2693
{
2694
	int i, len;
2695

2696
	/* set up TRAM */
2697
	if (emu->fx8010.etram_pages.bytes > 0) {
2698
		unsigned size, size_reg = 0;
2699
		size = emu->fx8010.etram_pages.bytes / 2;
2700
		size = (size - 1) >> 13;
2701
		while (size) {
2702
			size >>= 1;
2703
			size_reg++;
2704
		}
2705
		outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
2706
		snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
2707
		snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
2708
		outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
2709
	}
2710

2711
	if (emu->audigy)
2712
		snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
2713
	else
2714
		snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
2715

2716
	len = emu->audigy ? 0x200 : 0x100;
2717
	for (i = 0; i < len; i++)
2718
		snd_emu10k1_ptr_write(emu, emu->gpr_base + i, 0, emu->saved_gpr[i]);
2719

2720
	len = emu->audigy ? 0x100 : 0xa0;
2721
	for (i = 0; i < len; i++) {
2722
		snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + i, 0,
2723
				      emu->tram_val_saved[i]);
2724
		if (! emu->audigy)
2725
			snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
2726
					      emu->tram_addr_saved[i]);
2727
		else {
2728
			snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
2729
					      emu->tram_addr_saved[i] << 12);
2730
			snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
2731
					      emu->tram_addr_saved[i] >> 20);
2732
		}
2733
	}
2734

2735
	len = emu->audigy ? 2 * 1024 : 2 * 512;
2736
	for (i = 0; i < len; i++)
2737
		snd_emu10k1_efx_write(emu, i, emu->saved_icode[i]);
2738

2739
	/* start FX processor when the DSP code is updated */
2740
	if (emu->audigy)
2741
		snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
2742
	else
2743
		snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
2744
}
2745
#endif
2746

2747
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