Book a Demo!
CoCalc Logo Icon
StoreFeaturesDocsShareSupportNewsAboutPoliciesSign UpSign In
torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/sound/pci/ice1712/wm8766.h
26424 views
1
/* SPDX-License-Identifier: GPL-2.0-or-later */

2
#ifndef __SOUND_WM8766_H

3
#define __SOUND_WM8766_H

4


5
/*

6
 *   ALSA driver for ICEnsemble VT17xx

7
 *

8
 *   Lowlevel functions for WM8766 codec

9
 *

10
 *	Copyright (c) 2012 Ondrej Zary <[email protected]>

11
 */

12


13
#define WM8766_REG_DACL1	0x00

14
#define WM8766_REG_DACR1	0x01

15
#define WM8766_VOL_MASK			0x1ff		/* incl. update bit */

16
#define WM8766_VOL_UPDATE		(1 << 8)	/* update volume */

17
#define WM8766_REG_DACCTRL1	0x02

18
#define WM8766_DAC_MUTEALL		(1 << 0)

19
#define WM8766_DAC_DEEMPALL		(1 << 1)

20
#define WM8766_DAC_PDWN			(1 << 2)

21
#define WM8766_DAC_ATC			(1 << 3)

22
#define WM8766_DAC_IZD			(1 << 4)

23
#define WM8766_DAC_PL_MASK		0x1e0

24
#define WM8766_DAC_PL_LL		(1 << 5)	/* L chan: L signal */

25
#define WM8766_DAC_PL_LR		(2 << 5)	/* L chan: R signal */

26
#define WM8766_DAC_PL_LB		(3 << 5)	/* L chan: both */

27
#define WM8766_DAC_PL_RL		(1 << 7)	/* R chan: L signal */

28
#define WM8766_DAC_PL_RR		(2 << 7)	/* R chan: R signal */

29
#define WM8766_DAC_PL_RB		(3 << 7)	/* R chan: both */

30
#define WM8766_REG_IFCTRL	0x03

31
#define WM8766_IF_FMT_RIGHTJ		(0 << 0)

32
#define WM8766_IF_FMT_LEFTJ		(1 << 0)

33
#define WM8766_IF_FMT_I2S		(2 << 0)

34
#define WM8766_IF_FMT_DSP		(3 << 0)

35
#define WM8766_IF_DSP_LATE		(1 << 2)	/* in DSP mode */

36
#define WM8766_IF_LRC_INVERTED		(1 << 2)	/* in other modes */

37
#define WM8766_IF_BCLK_INVERTED		(1 << 3)

38
#define WM8766_IF_IWL_16BIT		(0 << 4)

39
#define WM8766_IF_IWL_20BIT		(1 << 4)

40
#define WM8766_IF_IWL_24BIT		(2 << 4)

41
#define WM8766_IF_IWL_32BIT		(3 << 4)

42
#define WM8766_IF_MASK			0x3f

43
#define WM8766_PHASE_INVERT1		(1 << 6)

44
#define WM8766_PHASE_INVERT2		(1 << 7)

45
#define WM8766_PHASE_INVERT3		(1 << 8)

46
#define WM8766_REG_DACL2	0x04

47
#define WM8766_REG_DACR2	0x05

48
#define WM8766_REG_DACL3	0x06

49
#define WM8766_REG_DACR3	0x07

50
#define WM8766_REG_MASTDA	0x08

51
#define WM8766_REG_DACCTRL2	0x09

52
#define WM8766_DAC2_ZCD			(1 << 0)

53
#define WM8766_DAC2_ZFLAG_ALL		(0 << 1)

54
#define WM8766_DAC2_ZFLAG_1		(1 << 1)

55
#define WM8766_DAC2_ZFLAG_2		(2 << 1)

56
#define WM8766_DAC2_ZFLAG_3		(3 << 1)

57
#define WM8766_DAC2_MUTE1		(1 << 3)

58
#define WM8766_DAC2_MUTE2		(1 << 4)

59
#define WM8766_DAC2_MUTE3		(1 << 5)

60
#define WM8766_DAC2_DEEMP1		(1 << 6)

61
#define WM8766_DAC2_DEEMP2		(1 << 7)

62
#define WM8766_DAC2_DEEMP3		(1 << 8)

63
#define WM8766_REG_DACCTRL3	0x0a

64
#define WM8766_DAC3_DACPD1		(1 << 1)

65
#define WM8766_DAC3_DACPD2		(1 << 2)

66
#define WM8766_DAC3_DACPD3		(1 << 3)

67
#define WM8766_DAC3_PWRDNALL		(1 << 4)

68
#define WM8766_DAC3_POWER_MASK		0x1e

69
#define WM8766_DAC3_MASTER		(1 << 5)

70
#define WM8766_DAC3_DAC128FS		(0 << 6)

71
#define WM8766_DAC3_DAC192FS		(1 << 6)

72
#define WM8766_DAC3_DAC256FS		(2 << 6)

73
#define WM8766_DAC3_DAC384FS		(3 << 6)

74
#define WM8766_DAC3_DAC512FS		(4 << 6)

75
#define WM8766_DAC3_DAC768FS		(5 << 6)

76
#define WM8766_DAC3_MSTR_MASK		0x1e0

77
#define WM8766_REG_MUTE1	0x0c

78
#define WM8766_MUTE1_MPD		(1 << 6)

79
#define WM8766_REG_MUTE2	0x0f

80
#define WM8766_MUTE2_MPD		(1 << 5)

81
#define WM8766_REG_RESET	0x1f

82


83
#define WM8766_REG_COUNT	0x10	/* don't cache the RESET register */

84


85
struct snd_wm8766;

86


87
struct snd_wm8766_ops {

88
	void (*write)(struct snd_wm8766 *wm, u16 addr, u16 data);

89
};

90


91
enum snd_wm8766_ctl_id {

92
	WM8766_CTL_CH1_VOL,

93
	WM8766_CTL_CH2_VOL,

94
	WM8766_CTL_CH3_VOL,

95
	WM8766_CTL_CH1_SW,

96
	WM8766_CTL_CH2_SW,

97
	WM8766_CTL_CH3_SW,

98
	WM8766_CTL_PHASE1_SW,

99
	WM8766_CTL_PHASE2_SW,

100
	WM8766_CTL_PHASE3_SW,

101
	WM8766_CTL_DEEMPH1_SW,

102
	WM8766_CTL_DEEMPH2_SW,

103
	WM8766_CTL_DEEMPH3_SW,

104
	WM8766_CTL_IZD_SW,

105
	WM8766_CTL_ZC_SW,

106


107
	WM8766_CTL_COUNT,

108
};

109


110
#define WM8766_ENUM_MAX		16

111


112
#define WM8766_FLAG_STEREO	(1 << 0)

113
#define WM8766_FLAG_VOL_UPDATE	(1 << 1)

114
#define WM8766_FLAG_INVERT	(1 << 2)

115
#define WM8766_FLAG_LIM		(1 << 3)

116
#define WM8766_FLAG_ALC		(1 << 4)

117


118
struct snd_wm8766_ctl {

119
	struct snd_kcontrol *kctl;

120
	const char *name;

121
	snd_ctl_elem_type_t type;

122
	const char *const enum_names[WM8766_ENUM_MAX];

123
	const unsigned int *tlv;

124
	u16 reg1, reg2, mask1, mask2, min, max, flags;

125
	void (*set)(struct snd_wm8766 *wm, u16 ch1, u16 ch2);

126
	void (*get)(struct snd_wm8766 *wm, u16 *ch1, u16 *ch2);

127
};

128


129
enum snd_wm8766_agc_mode { WM8766_AGC_OFF, WM8766_AGC_LIM, WM8766_AGC_ALC };

130


131
struct snd_wm8766 {

132
	struct snd_card *card;

133
	struct snd_wm8766_ctl ctl[WM8766_CTL_COUNT];

134
	enum snd_wm8766_agc_mode agc_mode;

135
	struct snd_wm8766_ops ops;

136
	u16 regs[WM8766_REG_COUNT];	/* 9-bit registers */

137
};

138


139


140


141
void snd_wm8766_init(struct snd_wm8766 *wm);

142
void snd_wm8766_resume(struct snd_wm8766 *wm);

143
void snd_wm8766_set_if(struct snd_wm8766 *wm, u16 dac);

144
void snd_wm8766_volume_restore(struct snd_wm8766 *wm);

145
int snd_wm8766_build_controls(struct snd_wm8766 *wm);

146


147
#endif /* __SOUND_WM8766_H */

148


149