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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/sound/pcmcia/vx/vxpocket.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */

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/*

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 * Driver for Digigram VXpocket soundcards

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 *

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 * Copyright (c) 2002 by Takashi Iwai <[email protected]>

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 */

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#ifndef __VXPOCKET_H

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#define __VXPOCKET_H

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#include <sound/vx_core.h>

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#include <pcmcia/cistpl.h>

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#include <pcmcia/ds.h>

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struct snd_vxpocket {

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	struct vx_core core;

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	unsigned long port;

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	int mic_level;	/* analog mic level (or boost) */

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	unsigned int regCDSP;	/* current CDSP register */

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	unsigned int regDIALOG;	/* current DIALOG register */

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	int index;	/* card index */

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	/* pcmcia stuff */

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	struct pcmcia_device	*p_dev;

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};

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#define to_vxpocket(x)	container_of(x, struct snd_vxpocket, core)

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extern const struct snd_vx_ops snd_vxpocket_ops;

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void vx_set_mic_boost(struct vx_core *chip, int boost);

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void vx_set_mic_level(struct vx_core *chip, int level);

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int vxp_add_mic_controls(struct vx_core *chip);

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/* Constants used to access the CDSP register (0x08). */

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#define CDSP_MAGIC	0xA7	/* magic value (for read) */

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/* for write */

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#define VXP_CDSP_CLOCKIN_SEL_MASK	0x80	/* 0 (internal), 1 (AES/EBU) */

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#define VXP_CDSP_DATAIN_SEL_MASK	0x40	/* 0 (analog), 1 (UER) */

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#define VXP_CDSP_SMPTE_SEL_MASK		0x20

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#define VXP_CDSP_RESERVED_MASK		0x10

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#define VXP_CDSP_MIC_SEL_MASK		0x08

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#define VXP_CDSP_VALID_IRQ_MASK		0x04

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#define VXP_CDSP_CODEC_RESET_MASK	0x02

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#define VXP_CDSP_DSP_RESET_MASK		0x01

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/* VXPOCKET 240/440 */

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#define P24_CDSP_MICS_SEL_MASK		0x18

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#define P24_CDSP_MIC20_SEL_MASK		0x10

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#define P24_CDSP_MIC38_SEL_MASK		0x08

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/* Constants used to access the MEMIRQ register (0x0C). */

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#define P44_MEMIRQ_MASTER_SLAVE_SEL_MASK 0x08

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#define P44_MEMIRQ_SYNCED_ALONE_SEL_MASK 0x04

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#define P44_MEMIRQ_WCLK_OUT_IN_SEL_MASK  0x02 /* Not used */

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#define P44_MEMIRQ_WCLK_UER_SEL_MASK     0x01 /* Not used */

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/* Micro levels (0x0C) */

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/* Constants used to access the DIALOG register (0x0D). */

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#define VXP_DLG_XILINX_REPROG_MASK	0x80	/* W */

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#define VXP_DLG_DATA_XICOR_MASK		0x80	/* R */

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#define VXP_DLG_RESERVED4_0_MASK	0x40

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#define VXP_DLG_RESERVED2_0_MASK	0x20

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#define VXP_DLG_RESERVED1_0_MASK	0x10

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#define VXP_DLG_DMAWRITE_SEL_MASK	0x08	/* W */

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#define VXP_DLG_DMAREAD_SEL_MASK	0x04	/* W */

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#define VXP_DLG_MEMIRQ_MASK		0x02	/* R */

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#define VXP_DLG_DMA16_SEL_MASK		0x02	/* W */

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#define VXP_DLG_ACK_MEMIRQ_MASK		0x01	/* R/W */

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#endif /* __VXPOCKET_H */

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