/* SPDX-License-Identifier: GPL-2.0-only */1/*2* Audio support for PS33* Copyright (C) 2007 Sony Computer Entertainment Inc.4* Copyright 2006, 2007 Sony Corporation5* All rights reserved.6*/78/*9* interrupt / configure registers10*/1112#define PS3_AUDIO_INTR_0 (0x00000100)13#define PS3_AUDIO_INTR_EN_0 (0x00000140)14#define PS3_AUDIO_CONFIG (0x00000200)1516/*17* DMAC registers18* n:0..919*/20#define PS3_AUDIO_DMAC_REGBASE(x) (0x0000210 + 0x20 * (x))2122#define PS3_AUDIO_KICK(n) (PS3_AUDIO_DMAC_REGBASE(n) + 0x00)23#define PS3_AUDIO_SOURCE(n) (PS3_AUDIO_DMAC_REGBASE(n) + 0x04)24#define PS3_AUDIO_DEST(n) (PS3_AUDIO_DMAC_REGBASE(n) + 0x08)25#define PS3_AUDIO_DMASIZE(n) (PS3_AUDIO_DMAC_REGBASE(n) + 0x0C)2627/*28* mute control29*/30#define PS3_AUDIO_AX_MCTRL (0x00004000)31#define PS3_AUDIO_AX_ISBP (0x00004004)32#define PS3_AUDIO_AX_AOBP (0x00004008)33#define PS3_AUDIO_AX_IC (0x00004010)34#define PS3_AUDIO_AX_IE (0x00004014)35#define PS3_AUDIO_AX_IS (0x00004018)3637/*38* three wire serial39* n:0..340*/41#define PS3_AUDIO_AO_MCTRL (0x00006000)42#define PS3_AUDIO_AO_3WMCTRL (0x00006004)4344#define PS3_AUDIO_AO_3WCTRL(n) (0x00006200 + 0x200 * (n))4546/*47* S/PDIF48* n:0..149* x:0..1150* y:0..551*/52#define PS3_AUDIO_AO_SPD_REGBASE(n) (0x00007200 + 0x200 * (n))5354#define PS3_AUDIO_AO_SPDCTRL(n) \55(PS3_AUDIO_AO_SPD_REGBASE(n) + 0x00)56#define PS3_AUDIO_AO_SPDUB(n, x) \57(PS3_AUDIO_AO_SPD_REGBASE(n) + 0x04 + 0x04 * (x))58#define PS3_AUDIO_AO_SPDCS(n, y) \59(PS3_AUDIO_AO_SPD_REGBASE(n) + 0x34 + 0x04 * (y))606162/*63PS3_AUDIO_INTR_0 register tells an interrupt handler which audio64DMA channel triggered the interrupt. The interrupt status for a channel65can be cleared by writing a '1' to the corresponding bit. A new interrupt66cannot be generated until the previous interrupt has been cleared.6768Note that the status reported by PS3_AUDIO_INTR_0 is independent of the69value of PS3_AUDIO_INTR_EN_0.707131 24 23 16 15 8 7 072+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+73|0 0 0 0 0 0 0 0 0 0 0 0 0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C| INTR_074+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+75*/76#define PS3_AUDIO_INTR_0_CHAN(n) (1 << ((n) * 2))77#define PS3_AUDIO_INTR_0_CHAN9 PS3_AUDIO_INTR_0_CHAN(9)78#define PS3_AUDIO_INTR_0_CHAN8 PS3_AUDIO_INTR_0_CHAN(8)79#define PS3_AUDIO_INTR_0_CHAN7 PS3_AUDIO_INTR_0_CHAN(7)80#define PS3_AUDIO_INTR_0_CHAN6 PS3_AUDIO_INTR_0_CHAN(6)81#define PS3_AUDIO_INTR_0_CHAN5 PS3_AUDIO_INTR_0_CHAN(5)82#define PS3_AUDIO_INTR_0_CHAN4 PS3_AUDIO_INTR_0_CHAN(4)83#define PS3_AUDIO_INTR_0_CHAN3 PS3_AUDIO_INTR_0_CHAN(3)84#define PS3_AUDIO_INTR_0_CHAN2 PS3_AUDIO_INTR_0_CHAN(2)85#define PS3_AUDIO_INTR_0_CHAN1 PS3_AUDIO_INTR_0_CHAN(1)86#define PS3_AUDIO_INTR_0_CHAN0 PS3_AUDIO_INTR_0_CHAN(0)8788/*89The PS3_AUDIO_INTR_EN_0 register specifies which DMA channels can generate90an interrupt to the PU. Each bit of PS3_AUDIO_INTR_EN_0 is ANDed with the91corresponding bit in PS3_AUDIO_INTR_0. The resulting bits are OR'd together92to generate the Audio interrupt.939431 24 23 16 15 8 7 095+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+96|0 0 0 0 0 0 0 0 0 0 0 0 0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C| INTR_EN_097+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+9899Bit assignments are same as PS3_AUDIO_INTR_0100*/101102/*103PS3_AUDIO_CONFIG10431 24 23 16 15 8 7 0105+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+106|0 0 0 0 0 0 0 0|0 0 0 0 0 0 0 0|0 0 0 0 0 0 0 C|0 0 0 0 0 0 0 0| CONFIG107+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+108109*/110111/* The CLEAR field cancels all pending transfers, and stops any running DMA112transfers. Any interrupts associated with the canceled transfers113will occur as if the transfer had finished.114Since this bit is designed to recover from DMA related issues115which are caused by unpredictable situations, it is preferred to wait116for normal DMA transfer end without using this bit.117*/118#define PS3_AUDIO_CONFIG_CLEAR (1 << 8) /* RWIVF */119120/*121PS3_AUDIO_AX_MCTRL: Audio Port Mute Control Register12212331 24 23 16 15 8 7 0124+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+125|0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|A|A|A|0 0 0 0 0 0 0|S|S|A|A|A|A| AX_MCTRL126+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+127*/128129/* 3 Wire Audio Serial Output Channel Mutes (0..3) */130#define PS3_AUDIO_AX_MCTRL_ASOMT(n) (1 << (3 - (n))) /* RWIVF */131#define PS3_AUDIO_AX_MCTRL_ASO3MT (1 << 0) /* RWIVF */132#define PS3_AUDIO_AX_MCTRL_ASO2MT (1 << 1) /* RWIVF */133#define PS3_AUDIO_AX_MCTRL_ASO1MT (1 << 2) /* RWIVF */134#define PS3_AUDIO_AX_MCTRL_ASO0MT (1 << 3) /* RWIVF */135136/* S/PDIF mutes (0,1)*/137#define PS3_AUDIO_AX_MCTRL_SPOMT(n) (1 << (5 - (n))) /* RWIVF */138#define PS3_AUDIO_AX_MCTRL_SPO1MT (1 << 4) /* RWIVF */139#define PS3_AUDIO_AX_MCTRL_SPO0MT (1 << 5) /* RWIVF */140141/* All 3 Wire Serial Outputs Mute */142#define PS3_AUDIO_AX_MCTRL_AASOMT (1 << 13) /* RWIVF */143144/* All S/PDIF Mute */145#define PS3_AUDIO_AX_MCTRL_ASPOMT (1 << 14) /* RWIVF */146147/* All Audio Outputs Mute */148#define PS3_AUDIO_AX_MCTRL_AAOMT (1 << 15) /* RWIVF */149150/*151S/PDIF Outputs Buffer Read/Write Pointer Register15215331 24 23 16 15 8 7 0154+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+155|0 0 0 0 0 0 0 0|0|SPO0B|0|SPO1B|0 0 0 0 0 0 0 0|0|SPO0B|0|SPO1B| AX_ISBP156+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+157158*/159/*160S/PDIF Output Channel Read Buffer Numbers161Buffer number is value of field.162Indicates current read access buffer ID from Audio Data163Transfer controller of S/PDIF Output164*/165166#define PS3_AUDIO_AX_ISBP_SPOBRN_MASK(n) (0x7 << 4 * (1 - (n))) /* R-IUF */167#define PS3_AUDIO_AX_ISBP_SPO1BRN_MASK (0x7 << 0) /* R-IUF */168#define PS3_AUDIO_AX_ISBP_SPO0BRN_MASK (0x7 << 4) /* R-IUF */169170/*171S/PDIF Output Channel Buffer Write Numbers172Indicates current write access buffer ID from bus master.173*/174#define PS3_AUDIO_AX_ISBP_SPOBWN_MASK(n) (0x7 << 4 * (5 - (n))) /* R-IUF */175#define PS3_AUDIO_AX_ISBP_SPO1BWN_MASK (0x7 << 16) /* R-IUF */176#define PS3_AUDIO_AX_ISBP_SPO0BWN_MASK (0x7 << 20) /* R-IUF */177178/*1793 Wire Audio Serial Outputs Buffer Read/Write180Pointer Register181Buffer number is value of field18218331 24 23 16 15 8 7 0184+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+185|0|ASO0B|0|ASO1B|0|ASO2B|0|ASO3B|0|ASO0B|0|ASO1B|0|ASO2B|0|ASO3B| AX_AOBP186+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+187*/188189/*1903 Wire Audio Serial Output Channel Buffer Read Numbers191Indicates current read access buffer Id from Audio Data Transfer192Controller of 3 Wire Audio Serial Output Channels193*/194#define PS3_AUDIO_AX_AOBP_ASOBRN_MASK(n) (0x7 << 4 * (3 - (n))) /* R-IUF */195196#define PS3_AUDIO_AX_AOBP_ASO3BRN_MASK (0x7 << 0) /* R-IUF */197#define PS3_AUDIO_AX_AOBP_ASO2BRN_MASK (0x7 << 4) /* R-IUF */198#define PS3_AUDIO_AX_AOBP_ASO1BRN_MASK (0x7 << 8) /* R-IUF */199#define PS3_AUDIO_AX_AOBP_ASO0BRN_MASK (0x7 << 12) /* R-IUF */200201/*2023 Wire Audio Serial Output Channel Buffer Write Numbers203Indicates current write access buffer ID from bus master.204*/205#define PS3_AUDIO_AX_AOBP_ASOBWN_MASK(n) (0x7 << 4 * (7 - (n))) /* R-IUF */206207#define PS3_AUDIO_AX_AOBP_ASO3BWN_MASK (0x7 << 16) /* R-IUF */208#define PS3_AUDIO_AX_AOBP_ASO2BWN_MASK (0x7 << 20) /* R-IUF */209#define PS3_AUDIO_AX_AOBP_ASO1BWN_MASK (0x7 << 24) /* R-IUF */210#define PS3_AUDIO_AX_AOBP_ASO0BWN_MASK (0x7 << 28) /* R-IUF */211212213214/*215Audio Port Interrupt Condition Register216For the fields in this register, the following values apply:2170 = Interrupt is generated every interrupt event.2181 = Interrupt is generated every 2 interrupt events.2192 = Interrupt is generated every 4 interrupt events.2203 = Reserved22122222331 24 23 16 15 8 7 0224+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+225|0 0 0 0 0 0 0 0|0 0|SPO|0 0|SPO|0 0|AAS|0 0 0 0 0 0 0 0 0 0 0 0| AX_IC226+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+227*/228/*229All 3-Wire Audio Serial Outputs Interrupt Mode230Configures the Interrupt and Signal Notification231condition of all 3-wire Audio Serial Outputs.232*/233#define PS3_AUDIO_AX_IC_AASOIMD_MASK (0x3 << 12) /* RWIVF */234#define PS3_AUDIO_AX_IC_AASOIMD_EVERY1 (0x0 << 12) /* RWI-V */235#define PS3_AUDIO_AX_IC_AASOIMD_EVERY2 (0x1 << 12) /* RW--V */236#define PS3_AUDIO_AX_IC_AASOIMD_EVERY4 (0x2 << 12) /* RW--V */237238/*239S/PDIF Output Channel Interrupt Modes240Configures the Interrupt and signal Notification241conditions of S/PDIF output channels.242*/243#define PS3_AUDIO_AX_IC_SPO1IMD_MASK (0x3 << 16) /* RWIVF */244#define PS3_AUDIO_AX_IC_SPO1IMD_EVERY1 (0x0 << 16) /* RWI-V */245#define PS3_AUDIO_AX_IC_SPO1IMD_EVERY2 (0x1 << 16) /* RW--V */246#define PS3_AUDIO_AX_IC_SPO1IMD_EVERY4 (0x2 << 16) /* RW--V */247248#define PS3_AUDIO_AX_IC_SPO0IMD_MASK (0x3 << 20) /* RWIVF */249#define PS3_AUDIO_AX_IC_SPO0IMD_EVERY1 (0x0 << 20) /* RWI-V */250#define PS3_AUDIO_AX_IC_SPO0IMD_EVERY2 (0x1 << 20) /* RW--V */251#define PS3_AUDIO_AX_IC_SPO0IMD_EVERY4 (0x2 << 20) /* RW--V */252253/*254Audio Port interrupt Enable Register255Configures whether to enable or disable each Interrupt Generation.25625725831 24 23 16 15 8 7 0259+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+260|0 0 0 0 0 0 0 0|S|S|0 0|A|A|A|A|0 0 0 0|S|S|0 0|S|S|0 0|A|A|A|A| AX_IE261+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+262263*/264265/*2663 Wire Audio Serial Output Channel Buffer Underflow267Interrupt Enables268Select enable/disable of Buffer Underflow Interrupts for2693-Wire Audio Serial Output Channels270DISABLED=Interrupt generation disabled.271*/272#define PS3_AUDIO_AX_IE_ASOBUIE(n) (1 << (3 - (n))) /* RWIVF */273#define PS3_AUDIO_AX_IE_ASO3BUIE (1 << 0) /* RWIVF */274#define PS3_AUDIO_AX_IE_ASO2BUIE (1 << 1) /* RWIVF */275#define PS3_AUDIO_AX_IE_ASO1BUIE (1 << 2) /* RWIVF */276#define PS3_AUDIO_AX_IE_ASO0BUIE (1 << 3) /* RWIVF */277278/* S/PDIF Output Channel Buffer Underflow Interrupt Enables */279280#define PS3_AUDIO_AX_IE_SPOBUIE(n) (1 << (7 - (n))) /* RWIVF */281#define PS3_AUDIO_AX_IE_SPO1BUIE (1 << 6) /* RWIVF */282#define PS3_AUDIO_AX_IE_SPO0BUIE (1 << 7) /* RWIVF */283284/* S/PDIF Output Channel One Block Transfer Completion Interrupt Enables */285286#define PS3_AUDIO_AX_IE_SPOBTCIE(n) (1 << (11 - (n))) /* RWIVF */287#define PS3_AUDIO_AX_IE_SPO1BTCIE (1 << 10) /* RWIVF */288#define PS3_AUDIO_AX_IE_SPO0BTCIE (1 << 11) /* RWIVF */289290/* 3-Wire Audio Serial Output Channel Buffer Empty Interrupt Enables */291292#define PS3_AUDIO_AX_IE_ASOBEIE(n) (1 << (19 - (n))) /* RWIVF */293#define PS3_AUDIO_AX_IE_ASO3BEIE (1 << 16) /* RWIVF */294#define PS3_AUDIO_AX_IE_ASO2BEIE (1 << 17) /* RWIVF */295#define PS3_AUDIO_AX_IE_ASO1BEIE (1 << 18) /* RWIVF */296#define PS3_AUDIO_AX_IE_ASO0BEIE (1 << 19) /* RWIVF */297298/* S/PDIF Output Channel Buffer Empty Interrupt Enables */299300#define PS3_AUDIO_AX_IE_SPOBEIE(n) (1 << (23 - (n))) /* RWIVF */301#define PS3_AUDIO_AX_IE_SPO1BEIE (1 << 22) /* RWIVF */302#define PS3_AUDIO_AX_IE_SPO0BEIE (1 << 23) /* RWIVF */303304/*305Audio Port Interrupt Status Register306Indicates Interrupt status, which interrupt has occurred, and can clear307each interrupt in this register.308Writing 1b to a field containing 1b clears field and de-asserts interrupt.309Writing 0b to a field has no effect.310Field values are the following:3110 - Interrupt hasn't occurred.3121 - Interrupt has occurred.31331431531 24 23 16 15 8 7 0316+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+317|0 0 0 0 0 0 0 0|S|S|0 0|A|A|A|A|0 0 0 0|S|S|0 0|S|S|0 0|A|A|A|A| AX_IS318+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+319320Bit assignment are same as AX_IE321*/322323/*324Audio Output Master Control Register325Configures Master Clock and other master Audio Output Settings32632732831 24 23 16 15 8 7 0329+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+330|0|SCKSE|0|SCKSE| MR0 | MR1 |MCL|MCL|0 0 0 0|0 0 0 0 0 0 0 0| AO_MCTRL331+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+332*/333334/*335MCLK Output Control336Controls mclko[1] output.3370 - Disable output (fixed at High)3381 - Output clock produced by clock selected339with scksel1 by mr13402 - Reserved3413 - Reserved342*/343344#define PS3_AUDIO_AO_MCTRL_MCLKC1_MASK (0x3 << 12) /* RWIVF */345#define PS3_AUDIO_AO_MCTRL_MCLKC1_DISABLED (0x0 << 12) /* RWI-V */346#define PS3_AUDIO_AO_MCTRL_MCLKC1_ENABLED (0x1 << 12) /* RW--V */347#define PS3_AUDIO_AO_MCTRL_MCLKC1_RESVD2 (0x2 << 12) /* RW--V */348#define PS3_AUDIO_AO_MCTRL_MCLKC1_RESVD3 (0x3 << 12) /* RW--V */349350/*351MCLK Output Control352Controls mclko[0] output.3530 - Disable output (fixed at High)3541 - Output clock produced by clock selected355with SCKSEL0 by MR03562 - Reserved3573 - Reserved358*/359#define PS3_AUDIO_AO_MCTRL_MCLKC0_MASK (0x3 << 14) /* RWIVF */360#define PS3_AUDIO_AO_MCTRL_MCLKC0_DISABLED (0x0 << 14) /* RWI-V */361#define PS3_AUDIO_AO_MCTRL_MCLKC0_ENABLED (0x1 << 14) /* RW--V */362#define PS3_AUDIO_AO_MCTRL_MCLKC0_RESVD2 (0x2 << 14) /* RW--V */363#define PS3_AUDIO_AO_MCTRL_MCLKC0_RESVD3 (0x3 << 14) /* RW--V */364/*365Master Clock Rate 1366Sets the divide ration of Master Clock1 (clock output from367mclko[1] for the input clock selected by scksel1.368*/369#define PS3_AUDIO_AO_MCTRL_MR1_MASK (0xf << 16)370#define PS3_AUDIO_AO_MCTRL_MR1_DEFAULT (0x0 << 16) /* RWI-V */371/*372Master Clock Rate 0373Sets the divide ratio of Master Clock0 (clock output from374mclko[0] for the input clock selected by scksel0).375*/376#define PS3_AUDIO_AO_MCTRL_MR0_MASK (0xf << 20) /* RWIVF */377#define PS3_AUDIO_AO_MCTRL_MR0_DEFAULT (0x0 << 20) /* RWI-V */378/*379System Clock Select 0/1380Selects the system clock to be used as Master Clock 0/1381Input the system clock that is appropriate for the sampling382rate.383*/384#define PS3_AUDIO_AO_MCTRL_SCKSEL1_MASK (0x7 << 24) /* RWIVF */385#define PS3_AUDIO_AO_MCTRL_SCKSEL1_DEFAULT (0x2 << 24) /* RWI-V */386387#define PS3_AUDIO_AO_MCTRL_SCKSEL0_MASK (0x7 << 28) /* RWIVF */388#define PS3_AUDIO_AO_MCTRL_SCKSEL0_DEFAULT (0x2 << 28) /* RWI-V */389390391/*3923-Wire Audio Output Master Control Register393Configures clock, 3-Wire Audio Serial Output Enable, and394other 3-Wire Audio Serial Output Master Settings39539639731 24 23 16 15 8 7 0398+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+399|A|A|A|A|0 0 0|A| ASOSR |0 0 0 0|A|A|A|A|A|A|0|1|0 0 0 0 0 0 0 0| AO_3WMCTRL400+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+401*/402403404/*405LRCKO Polarity4060 - Reserved4071 - default408*/409#define PS3_AUDIO_AO_3WMCTRL_ASOPLRCK (1 << 8) /* RWIVF */410#define PS3_AUDIO_AO_3WMCTRL_ASOPLRCK_DEFAULT (1 << 8) /* RW--V */411412/* LRCK Output Disable */413414#define PS3_AUDIO_AO_3WMCTRL_ASOLRCKD (1 << 10) /* RWIVF */415#define PS3_AUDIO_AO_3WMCTRL_ASOLRCKD_ENABLED (0 << 10) /* RW--V */416#define PS3_AUDIO_AO_3WMCTRL_ASOLRCKD_DISABLED (1 << 10) /* RWI-V */417418/* Bit Clock Output Disable */419420#define PS3_AUDIO_AO_3WMCTRL_ASOBCLKD (1 << 11) /* RWIVF */421#define PS3_AUDIO_AO_3WMCTRL_ASOBCLKD_ENABLED (0 << 11) /* RW--V */422#define PS3_AUDIO_AO_3WMCTRL_ASOBCLKD_DISABLED (1 << 11) /* RWI-V */423424/*4253-Wire Audio Serial Output Channel 0-3 Operational426Status. Each bit becomes 1 after each 3-Wire Audio427Serial Output Channel N is in action by setting 1 to428asoen.429Each bit becomes 0 after each 3-Wire Audio Serial Output430Channel N is out of action by setting 0 to asoen.431*/432#define PS3_AUDIO_AO_3WMCTRL_ASORUN(n) (1 << (15 - (n))) /* R-IVF */433#define PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(n) (0 << (15 - (n))) /* R-I-V */434#define PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(n) (1 << (15 - (n))) /* R---V */435#define PS3_AUDIO_AO_3WMCTRL_ASORUN0 \436PS3_AUDIO_AO_3WMCTRL_ASORUN(0)437#define PS3_AUDIO_AO_3WMCTRL_ASORUN0_STOPPED \438PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(0)439#define PS3_AUDIO_AO_3WMCTRL_ASORUN0_RUNNING \440PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(0)441#define PS3_AUDIO_AO_3WMCTRL_ASORUN1 \442PS3_AUDIO_AO_3WMCTRL_ASORUN(1)443#define PS3_AUDIO_AO_3WMCTRL_ASORUN1_STOPPED \444PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(1)445#define PS3_AUDIO_AO_3WMCTRL_ASORUN1_RUNNING \446PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(1)447#define PS3_AUDIO_AO_3WMCTRL_ASORUN2 \448PS3_AUDIO_AO_3WMCTRL_ASORUN(2)449#define PS3_AUDIO_AO_3WMCTRL_ASORUN2_STOPPED \450PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(2)451#define PS3_AUDIO_AO_3WMCTRL_ASORUN2_RUNNING \452PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(2)453#define PS3_AUDIO_AO_3WMCTRL_ASORUN3 \454PS3_AUDIO_AO_3WMCTRL_ASORUN(3)455#define PS3_AUDIO_AO_3WMCTRL_ASORUN3_STOPPED \456PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(3)457#define PS3_AUDIO_AO_3WMCTRL_ASORUN3_RUNNING \458PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(3)459460/*461Sampling Rate462Specifies the divide ratio of the bit clock (clock output463from bclko) used by the 3-wire Audio Output Clock, which464is applied to the master clock selected by mcksel.465Data output is synchronized with this clock.466*/467#define PS3_AUDIO_AO_3WMCTRL_ASOSR_MASK (0xf << 20) /* RWIVF */468#define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV2 (0x1 << 20) /* RWI-V */469#define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV4 (0x2 << 20) /* RW--V */470#define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV8 (0x4 << 20) /* RW--V */471#define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV12 (0x6 << 20) /* RW--V */472473/*474Master Clock Select4750 - Master Clock 04761 - Master Clock 1477*/478#define PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL (1 << 24) /* RWIVF */479#define PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL_CLK0 (0 << 24) /* RWI-V */480#define PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL_CLK1 (1 << 24) /* RW--V */481482/*483Enables and disables 4ch 3-Wire Audio Serial Output484operation. Each Bit from 0 to 3 corresponds to an485output channel, which means that each output channel486can be enabled or disabled individually. When487multiple channels are enabled at the same time, output488operations are performed in synchronization.489Bit 0 - Output Channel 0 (SDOUT[0])490Bit 1 - Output Channel 1 (SDOUT[1])491Bit 2 - Output Channel 2 (SDOUT[2])492Bit 3 - Output Channel 3 (SDOUT[3])493*/494#define PS3_AUDIO_AO_3WMCTRL_ASOEN(n) (1 << (31 - (n))) /* RWIVF */495#define PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(n) (0 << (31 - (n))) /* RWI-V */496#define PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(n) (1 << (31 - (n))) /* RW--V */497498#define PS3_AUDIO_AO_3WMCTRL_ASOEN0 \499PS3_AUDIO_AO_3WMCTRL_ASOEN(0) /* RWIVF */500#define PS3_AUDIO_AO_3WMCTRL_ASOEN0_DISABLED \501PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(0) /* RWI-V */502#define PS3_AUDIO_AO_3WMCTRL_ASOEN0_ENABLED \503PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(0) /* RW--V */504#define PS3_AUDIO_A1_3WMCTRL_ASOEN0 \505PS3_AUDIO_AO_3WMCTRL_ASOEN(1) /* RWIVF */506#define PS3_AUDIO_A1_3WMCTRL_ASOEN0_DISABLED \507PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(1) /* RWI-V */508#define PS3_AUDIO_A1_3WMCTRL_ASOEN0_ENABLED \509PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(1) /* RW--V */510#define PS3_AUDIO_A2_3WMCTRL_ASOEN0 \511PS3_AUDIO_AO_3WMCTRL_ASOEN(2) /* RWIVF */512#define PS3_AUDIO_A2_3WMCTRL_ASOEN0_DISABLED \513PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(2) /* RWI-V */514#define PS3_AUDIO_A2_3WMCTRL_ASOEN0_ENABLED \515PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(2) /* RW--V */516#define PS3_AUDIO_A3_3WMCTRL_ASOEN0 \517PS3_AUDIO_AO_3WMCTRL_ASOEN(3) /* RWIVF */518#define PS3_AUDIO_A3_3WMCTRL_ASOEN0_DISABLED \519PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(3) /* RWI-V */520#define PS3_AUDIO_A3_3WMCTRL_ASOEN0_ENABLED \521PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(3) /* RW--V */522523/*5243-Wire Audio Serial output Channel 0-3 Control Register525Configures settings for 3-Wire Serial Audio Output Channel 0-352652752831 24 23 16 15 8 7 0529+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+530|0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|A|0 0 0 0|A|0|ASO|0 0 0|0|0|0|0|0| AO_3WCTRL531+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+532533*/534/*535Data Bit Mode536Specifies the number of data bits5370 - 16 bits5381 - reserved5392 - 20 bits5403 - 24 bits541*/542#define PS3_AUDIO_AO_3WCTRL_ASODB_MASK (0x3 << 8) /* RWIVF */543#define PS3_AUDIO_AO_3WCTRL_ASODB_16BIT (0x0 << 8) /* RWI-V */544#define PS3_AUDIO_AO_3WCTRL_ASODB_RESVD (0x1 << 8) /* RWI-V */545#define PS3_AUDIO_AO_3WCTRL_ASODB_20BIT (0x2 << 8) /* RW--V */546#define PS3_AUDIO_AO_3WCTRL_ASODB_24BIT (0x3 << 8) /* RW--V */547/*548Data Format Mode549Specifies the data format where (LSB side or MSB) the data(in 20 bit550or 24 bit resolution mode) is put in a 32 bit field.5510 - Data put on LSB side5521 - Data put on MSB side553*/554#define PS3_AUDIO_AO_3WCTRL_ASODF (1 << 11) /* RWIVF */555#define PS3_AUDIO_AO_3WCTRL_ASODF_LSB (0 << 11) /* RWI-V */556#define PS3_AUDIO_AO_3WCTRL_ASODF_MSB (1 << 11) /* RW--V */557/*558Buffer Reset559Performs buffer reset. Writing 1 to this bit initializes the560corresponding 3-Wire Audio Output buffers(both L and R).561*/562#define PS3_AUDIO_AO_3WCTRL_ASOBRST (1 << 16) /* CWIVF */563#define PS3_AUDIO_AO_3WCTRL_ASOBRST_IDLE (0 << 16) /* -WI-V */564#define PS3_AUDIO_AO_3WCTRL_ASOBRST_RESET (1 << 16) /* -W--T */565566/*567S/PDIF Audio Output Channel 0/1 Control Register568Configures settings for S/PDIF Audio Output Channel 0/1.56957031 24 23 16 15 8 7 0571+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+572|S|0 0 0|S|0 0|S| SPOSR |0 0|SPO|0 0 0 0|S|0|SPO|0 0 0 0 0 0 0|S| AO_SPDCTRL573+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+574*/575/*576Buffer reset. Writing 1 to this bit initializes the577corresponding S/PDIF output buffer pointer.578*/579#define PS3_AUDIO_AO_SPDCTRL_SPOBRST (1 << 0) /* CWIVF */580#define PS3_AUDIO_AO_SPDCTRL_SPOBRST_IDLE (0 << 0) /* -WI-V */581#define PS3_AUDIO_AO_SPDCTRL_SPOBRST_RESET (1 << 0) /* -W--T */582583/*584Data Bit Mode585Specifies number of data bits5860 - 16 bits5871 - Reserved5882 - 20 bits5893 - 24 bits590*/591#define PS3_AUDIO_AO_SPDCTRL_SPODB_MASK (0x3 << 8) /* RWIVF */592#define PS3_AUDIO_AO_SPDCTRL_SPODB_16BIT (0x0 << 8) /* RWI-V */593#define PS3_AUDIO_AO_SPDCTRL_SPODB_RESVD (0x1 << 8) /* RW--V */594#define PS3_AUDIO_AO_SPDCTRL_SPODB_20BIT (0x2 << 8) /* RW--V */595#define PS3_AUDIO_AO_SPDCTRL_SPODB_24BIT (0x3 << 8) /* RW--V */596/*597Data format Mode598Specifies the data format, where (LSB side or MSB)599the data(in 20 or 24 bit resolution) is put in the60032 bit field.6010 - LSB Side6021 - MSB Side603*/604#define PS3_AUDIO_AO_SPDCTRL_SPODF (1 << 11) /* RWIVF */605#define PS3_AUDIO_AO_SPDCTRL_SPODF_LSB (0 << 11) /* RWI-V */606#define PS3_AUDIO_AO_SPDCTRL_SPODF_MSB (1 << 11) /* RW--V */607/*608Source Select609Specifies the source of the S/PDIF output. When 0, output610operation is controlled by 3wen[0] of AO_3WMCTRL register.611The SR must have the same setting as the a0_3wmctrl reg.6120 - 3-Wire Audio OUT Ch0 Buffer6131 - S/PDIF buffer614*/615#define PS3_AUDIO_AO_SPDCTRL_SPOSS_MASK (0x3 << 16) /* RWIVF */616#define PS3_AUDIO_AO_SPDCTRL_SPOSS_3WEN (0x0 << 16) /* RWI-V */617#define PS3_AUDIO_AO_SPDCTRL_SPOSS_SPDIF (0x1 << 16) /* RW--V */618/*619Sampling Rate620Specifies the divide ratio of the bit clock (clock output621from bclko) used by the S/PDIF Output Clock, which622is applied to the master clock selected by mcksel.623*/624#define PS3_AUDIO_AO_SPDCTRL_SPOSR (0xf << 20) /* RWIVF */625#define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV2 (0x1 << 20) /* RWI-V */626#define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV4 (0x2 << 20) /* RW--V */627#define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV8 (0x4 << 20) /* RW--V */628#define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV12 (0x6 << 20) /* RW--V */629/*630Master Clock Select6310 - Master Clock 06321 - Master Clock 1633*/634#define PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL (1 << 24) /* RWIVF */635#define PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL_CLK0 (0 << 24) /* RWI-V */636#define PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL_CLK1 (1 << 24) /* RW--V */637638/*639S/PDIF Output Channel Operational Status640This bit becomes 1 after S/PDIF Output Channel is in641action by setting 1 to spoen. This bit becomes 0642after S/PDIF Output Channel is out of action by setting6430 to spoen.644*/645#define PS3_AUDIO_AO_SPDCTRL_SPORUN (1 << 27) /* R-IVF */646#define PS3_AUDIO_AO_SPDCTRL_SPORUN_STOPPED (0 << 27) /* R-I-V */647#define PS3_AUDIO_AO_SPDCTRL_SPORUN_RUNNING (1 << 27) /* R---V */648649/*650S/PDIF Audio Output Channel Output Enable651Enables and disables output operation. This bit is used652only when sposs = 1653*/654#define PS3_AUDIO_AO_SPDCTRL_SPOEN (1 << 31) /* RWIVF */655#define PS3_AUDIO_AO_SPDCTRL_SPOEN_DISABLED (0 << 31) /* RWI-V */656#define PS3_AUDIO_AO_SPDCTRL_SPOEN_ENABLED (1 << 31) /* RW--V */657658/*659S/PDIF Audio Output Channel Channel Status660Setting Registers.661Configures channel status bit settings for each block662(192 bits).663Output is performed from the MSB(AO_SPDCS0 register bit 31).664The same value is added for subframes within the same frame.66531 24 23 16 15 8 7 0666+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+667| SPOCS | AO_SPDCS668+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+669670S/PDIF Audio Output Channel User Bit Setting671Configures user bit settings for each block (384 bits).672Output is performed from the MSB(ao_spdub0 register bit 31).67367467531 24 23 16 15 8 7 0676+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+677| SPOUB | AO_SPDUB678+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+679*/680/*****************************************************************************681*682* DMAC register683*684*****************************************************************************/685/*686The PS3_AUDIO_KICK register is used to initiate a DMA transfer and monitor687its status68868931 24 23 16 15 8 7 0690+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+691|0 0 0 0 0|STATU|0 0 0| EVENT |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|R| KICK692+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+693*/694/*695The REQUEST field is written to ACTIVE to initiate a DMA request when EVENT696occurs.697It will return to the DONE state when the request is completed.698The registers for a DMA channel should only be written if REQUEST is IDLE.699*/700701#define PS3_AUDIO_KICK_REQUEST (1 << 0) /* RWIVF */702#define PS3_AUDIO_KICK_REQUEST_IDLE (0 << 0) /* RWI-V */703#define PS3_AUDIO_KICK_REQUEST_ACTIVE (1 << 0) /* -W--T */704705/*706*The EVENT field is used to set the event in which707*the DMA request becomes active.708*/709#define PS3_AUDIO_KICK_EVENT_MASK (0x1f << 16) /* RWIVF */710#define PS3_AUDIO_KICK_EVENT_ALWAYS (0x00 << 16) /* RWI-V */711#define PS3_AUDIO_KICK_EVENT_SERIALOUT0_EMPTY (0x01 << 16) /* RW--V */712#define PS3_AUDIO_KICK_EVENT_SERIALOUT0_UNDERFLOW (0x02 << 16) /* RW--V */713#define PS3_AUDIO_KICK_EVENT_SERIALOUT1_EMPTY (0x03 << 16) /* RW--V */714#define PS3_AUDIO_KICK_EVENT_SERIALOUT1_UNDERFLOW (0x04 << 16) /* RW--V */715#define PS3_AUDIO_KICK_EVENT_SERIALOUT2_EMPTY (0x05 << 16) /* RW--V */716#define PS3_AUDIO_KICK_EVENT_SERIALOUT2_UNDERFLOW (0x06 << 16) /* RW--V */717#define PS3_AUDIO_KICK_EVENT_SERIALOUT3_EMPTY (0x07 << 16) /* RW--V */718#define PS3_AUDIO_KICK_EVENT_SERIALOUT3_UNDERFLOW (0x08 << 16) /* RW--V */719#define PS3_AUDIO_KICK_EVENT_SPDIF0_BLOCKTRANSFERCOMPLETE \720(0x09 << 16) /* RW--V */721#define PS3_AUDIO_KICK_EVENT_SPDIF0_UNDERFLOW (0x0A << 16) /* RW--V */722#define PS3_AUDIO_KICK_EVENT_SPDIF0_EMPTY (0x0B << 16) /* RW--V */723#define PS3_AUDIO_KICK_EVENT_SPDIF1_BLOCKTRANSFERCOMPLETE \724(0x0C << 16) /* RW--V */725#define PS3_AUDIO_KICK_EVENT_SPDIF1_UNDERFLOW (0x0D << 16) /* RW--V */726#define PS3_AUDIO_KICK_EVENT_SPDIF1_EMPTY (0x0E << 16) /* RW--V */727728#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA(n) \729((0x13 + (n)) << 16) /* RW--V */730#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA0 (0x13 << 16) /* RW--V */731#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA1 (0x14 << 16) /* RW--V */732#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA2 (0x15 << 16) /* RW--V */733#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA3 (0x16 << 16) /* RW--V */734#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA4 (0x17 << 16) /* RW--V */735#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA5 (0x18 << 16) /* RW--V */736#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA6 (0x19 << 16) /* RW--V */737#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA7 (0x1A << 16) /* RW--V */738#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA8 (0x1B << 16) /* RW--V */739#define PS3_AUDIO_KICK_EVENT_AUDIO_DMA9 (0x1C << 16) /* RW--V */740741/*742The STATUS field can be used to monitor the progress of a DMA request.743DONE indicates the previous request has completed.744EVENT indicates that the DMA engine is waiting for the EVENT to occur.745PENDING indicates that the DMA engine has not started processing this746request, but the EVENT has occurred.747DMA indicates that the data transfer is in progress.748NOTIFY indicates that the notifier signalling end of transfer is being written.749CLEAR indicated that the previous transfer was cleared.750ERROR indicates the previous transfer requested an unsupported751source/destination combination.752*/753754#define PS3_AUDIO_KICK_STATUS_MASK (0x7 << 24) /* R-IVF */755#define PS3_AUDIO_KICK_STATUS_DONE (0x0 << 24) /* R-I-V */756#define PS3_AUDIO_KICK_STATUS_EVENT (0x1 << 24) /* R---V */757#define PS3_AUDIO_KICK_STATUS_PENDING (0x2 << 24) /* R---V */758#define PS3_AUDIO_KICK_STATUS_DMA (0x3 << 24) /* R---V */759#define PS3_AUDIO_KICK_STATUS_NOTIFY (0x4 << 24) /* R---V */760#define PS3_AUDIO_KICK_STATUS_CLEAR (0x5 << 24) /* R---V */761#define PS3_AUDIO_KICK_STATUS_ERROR (0x6 << 24) /* R---V */762763/*764The PS3_AUDIO_SOURCE register specifies the source address for transfers.76576676731 24 23 16 15 8 7 0768+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+769| START |0 0 0 0 0|TAR| SOURCE770+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+771*/772773/*774The Audio DMA engine uses 128-byte transfers, thus the address must be aligned775to a 128 byte boundary. The low seven bits are assumed to be 0.776*/777778#define PS3_AUDIO_SOURCE_START_MASK (0x01FFFFFF << 7) /* RWIUF */779780/*781The TARGET field specifies the memory space containing the source address.782*/783784#define PS3_AUDIO_SOURCE_TARGET_MASK (3 << 0) /* RWIVF */785#define PS3_AUDIO_SOURCE_TARGET_SYSTEM_MEMORY (2 << 0) /* RW--V */786787/*788The PS3_AUDIO_DEST register specifies the destination address for transfers.78979079131 24 23 16 15 8 7 0792+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+793| START |0 0 0 0 0|TAR| DEST794+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+795*/796797/*798The Audio DMA engine uses 128-byte transfers, thus the address must be aligned799to a 128 byte boundary. The low seven bits are assumed to be 0.800*/801802#define PS3_AUDIO_DEST_START_MASK (0x01FFFFFF << 7) /* RWIUF */803804/*805The TARGET field specifies the memory space containing the destination address806AUDIOFIFO = Audio WriteData FIFO,807*/808809#define PS3_AUDIO_DEST_TARGET_MASK (3 << 0) /* RWIVF */810#define PS3_AUDIO_DEST_TARGET_AUDIOFIFO (1 << 0) /* RW--V */811812/*813PS3_AUDIO_DMASIZE specifies the number of 128-byte blocks + 1 to transfer.814So a value of 0 means 128-bytes will get transferred.81581681731 24 23 16 15 8 7 0818+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+819|0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| BLOCKS | DMASIZE820+-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+821*/822823824#define PS3_AUDIO_DMASIZE_BLOCKS_MASK (0x7f << 0) /* RWIUF */825826/*827* source/destination address for internal fifos828*/829#define PS3_AUDIO_AO_3W_LDATA(n) (0x1000 + (0x100 * (n)))830#define PS3_AUDIO_AO_3W_RDATA(n) (0x1080 + (0x100 * (n)))831832#define PS3_AUDIO_AO_SPD_DATA(n) (0x2000 + (0x400 * (n)))833834835/*836* field attiribute837*838* Read839* ' ' = Other Information840* '-' = Field is part of a write-only register841* 'C' = Value read is always the same, constant value line follows (C)842* 'R' = Value is read843*844* Write845* ' ' = Other Information846* '-' = Must not be written (D), value ignored when written (R,A,F)847* 'W' = Can be written848*849* Internal State850* ' ' = Other Information851* '-' = No internal state852* 'X' = Internal state, initial value is unknown853* 'I' = Internal state, initial value is known and follows (I)854*855* Declaration/Size856* ' ' = Other Information857* '-' = Does Not Apply858* 'V' = Type is void859* 'U' = Type is unsigned integer860* 'S' = Type is signed integer861* 'F' = Type is IEEE floating point862* '1' = Byte size (008)863* '2' = Short size (016)864* '3' = Three byte size (024)865* '4' = Word size (032)866* '8' = Double size (064)867*868* Define Indicator869* ' ' = Other Information870* 'D' = Device871* 'M' = Memory872* 'R' = Register873* 'A' = Array of Registers874* 'F' = Field875* 'V' = Value876* 'T' = Task877*/878879880881