Path: blob/master/sound/soc/amd/renoir/rn_chip_offset_byte.h
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/* SPDX-License-Identifier: GPL-2.0+ */1/*2* AMD ACP 3.1 Register Documentation3*4* Copyright 2020 Advanced Micro Devices, Inc.5*/67#ifndef _rn_OFFSET_HEADER8#define _rn_OFFSET_HEADER9// Registers from ACP_DMA block1011#define ACP_DMA_CNTL_0 0x124000012#define ACP_DMA_CNTL_1 0x124000413#define ACP_DMA_CNTL_2 0x124000814#define ACP_DMA_CNTL_3 0x124000C15#define ACP_DMA_CNTL_4 0x124001016#define ACP_DMA_CNTL_5 0x124001417#define ACP_DMA_CNTL_6 0x124001818#define ACP_DMA_CNTL_7 0x124001C19#define ACP_DMA_DSCR_STRT_IDX_0 0x124002020#define ACP_DMA_DSCR_STRT_IDX_1 0x124002421#define ACP_DMA_DSCR_STRT_IDX_2 0x124002822#define ACP_DMA_DSCR_STRT_IDX_3 0x124002C23#define ACP_DMA_DSCR_STRT_IDX_4 0x124003024#define ACP_DMA_DSCR_STRT_IDX_5 0x124003425#define ACP_DMA_DSCR_STRT_IDX_6 0x124003826#define ACP_DMA_DSCR_STRT_IDX_7 0x124003C27#define ACP_DMA_DSCR_CNT_0 0x124004028#define ACP_DMA_DSCR_CNT_1 0x124004429#define ACP_DMA_DSCR_CNT_2 0x124004830#define ACP_DMA_DSCR_CNT_3 0x124004C31#define ACP_DMA_DSCR_CNT_4 0x124005032#define ACP_DMA_DSCR_CNT_5 0x124005433#define ACP_DMA_DSCR_CNT_6 0x124005834#define ACP_DMA_DSCR_CNT_7 0x124005C35#define ACP_DMA_PRIO_0 0x124006036#define ACP_DMA_PRIO_1 0x124006437#define ACP_DMA_PRIO_2 0x124006838#define ACP_DMA_PRIO_3 0x124006C39#define ACP_DMA_PRIO_4 0x124007040#define ACP_DMA_PRIO_5 0x124007441#define ACP_DMA_PRIO_6 0x124007842#define ACP_DMA_PRIO_7 0x124007C43#define ACP_DMA_CUR_DSCR_0 0x124008044#define ACP_DMA_CUR_DSCR_1 0x124008445#define ACP_DMA_CUR_DSCR_2 0x124008846#define ACP_DMA_CUR_DSCR_3 0x124008C47#define ACP_DMA_CUR_DSCR_4 0x124009048#define ACP_DMA_CUR_DSCR_5 0x124009449#define ACP_DMA_CUR_DSCR_6 0x124009850#define ACP_DMA_CUR_DSCR_7 0x124009C51#define ACP_DMA_CUR_TRANS_CNT_0 0x12400A052#define ACP_DMA_CUR_TRANS_CNT_1 0x12400A453#define ACP_DMA_CUR_TRANS_CNT_2 0x12400A854#define ACP_DMA_CUR_TRANS_CNT_3 0x12400AC55#define ACP_DMA_CUR_TRANS_CNT_4 0x12400B056#define ACP_DMA_CUR_TRANS_CNT_5 0x12400B457#define ACP_DMA_CUR_TRANS_CNT_6 0x12400B858#define ACP_DMA_CUR_TRANS_CNT_7 0x12400BC59#define ACP_DMA_ERR_STS_0 0x12400C060#define ACP_DMA_ERR_STS_1 0x12400C461#define ACP_DMA_ERR_STS_2 0x12400C862#define ACP_DMA_ERR_STS_3 0x12400CC63#define ACP_DMA_ERR_STS_4 0x12400D064#define ACP_DMA_ERR_STS_5 0x12400D465#define ACP_DMA_ERR_STS_6 0x12400D866#define ACP_DMA_ERR_STS_7 0x12400DC67#define ACP_DMA_DESC_BASE_ADDR 0x12400E068#define ACP_DMA_DESC_MAX_NUM_DSCR 0x12400E469#define ACP_DMA_CH_STS 0x12400E870#define ACP_DMA_CH_GROUP 0x12400EC71#define ACP_DMA_CH_RST_STS 0x12400F07273// Registers from ACP_AXI2AXIATU block7475#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x1240C0076#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x1240C0477#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x1240C0878#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x1240C0C79#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x1240C1080#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x1240C1481#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x1240C1882#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x1240C1C83#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x1240C2084#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x1240C2485#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x1240C2886#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x1240C2C87#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x1240C3088#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x1240C3489#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x1240C3890#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x1240C3C91#define ACPAXI2AXI_ATU_CTRL 0x1240C409293// Registers from ACP_CLKRST block9495#define ACP_SOFT_RESET 0x124100096#define ACP_CONTROL 0x124100497#define ACP_STATUS 0x124100898#define ACP_DYNAMIC_CG_MASTER_CONTROL 0x124101099100// Registers from ACP_MISC block101102#define ACP_EXTERNAL_INTR_ENB 0x1241800103#define ACP_EXTERNAL_INTR_CNTL 0x1241804104#define ACP_EXTERNAL_INTR_STAT 0x1241808105#define ACP_PGMEM_CTRL 0x12418C0106#define ACP_ERROR_STATUS 0x12418C4107#define ACP_SW_I2S_ERROR_REASON 0x12418C8108#define ACP_MEM_PG_STS 0x12418CC109110// Registers from ACP_PGFSM block111112#define ACP_I2S_PIN_CONFIG 0x1241400113#define ACP_PAD_PULLUP_PULLDOWN_CTRL 0x1241404114#define ACP_PAD_DRIVE_STRENGTH_CTRL 0x1241408115#define ACP_SW_PAD_KEEPER_EN 0x124140C116#define ACP_PGFSM_CONTROL 0x124141C117#define ACP_PGFSM_STATUS 0x1241420118#define ACP_CLKMUX_SEL 0x1241424119#define ACP_DEVICE_STATE 0x1241428120#define AZ_DEVICE_STATE 0x124142C121#define ACP_INTR_URGENCY_TIMER 0x1241430122#define AZ_INTR_URGENCY_TIMER 0x1241434123124// Registers from ACP_SCRATCH block125126#define ACP_SCRATCH_REG_0 0x1250000127#define ACP_SCRATCH_REG_1 0x1250004128#define ACP_SCRATCH_REG_2 0x1250008129#define ACP_SCRATCH_REG_3 0x125000C130#define ACP_SCRATCH_REG_4 0x1250010131#define ACP_SCRATCH_REG_5 0x1250014132#define ACP_SCRATCH_REG_6 0x1250018133#define ACP_SCRATCH_REG_7 0x125001C134#define ACP_SCRATCH_REG_8 0x1250020135#define ACP_SCRATCH_REG_9 0x1250024136#define ACP_SCRATCH_REG_10 0x1250028137#define ACP_SCRATCH_REG_11 0x125002C138#define ACP_SCRATCH_REG_12 0x1250030139#define ACP_SCRATCH_REG_13 0x1250034140#define ACP_SCRATCH_REG_14 0x1250038141#define ACP_SCRATCH_REG_15 0x125003C142#define ACP_SCRATCH_REG_16 0x1250040143#define ACP_SCRATCH_REG_17 0x1250044144#define ACP_SCRATCH_REG_18 0x1250048145#define ACP_SCRATCH_REG_19 0x125004C146#define ACP_SCRATCH_REG_20 0x1250050147#define ACP_SCRATCH_REG_21 0x1250054148#define ACP_SCRATCH_REG_22 0x1250058149#define ACP_SCRATCH_REG_23 0x125005C150#define ACP_SCRATCH_REG_24 0x1250060151#define ACP_SCRATCH_REG_25 0x1250064152#define ACP_SCRATCH_REG_26 0x1250068153#define ACP_SCRATCH_REG_27 0x125006C154#define ACP_SCRATCH_REG_28 0x1250070155#define ACP_SCRATCH_REG_29 0x1250074156#define ACP_SCRATCH_REG_30 0x1250078157#define ACP_SCRATCH_REG_31 0x125007C158#define ACP_SCRATCH_REG_32 0x1250080159#define ACP_SCRATCH_REG_33 0x1250084160#define ACP_SCRATCH_REG_34 0x1250088161#define ACP_SCRATCH_REG_35 0x125008C162#define ACP_SCRATCH_REG_36 0x1250090163#define ACP_SCRATCH_REG_37 0x1250094164#define ACP_SCRATCH_REG_38 0x1250098165#define ACP_SCRATCH_REG_39 0x125009C166#define ACP_SCRATCH_REG_40 0x12500A0167#define ACP_SCRATCH_REG_41 0x12500A4168#define ACP_SCRATCH_REG_42 0x12500A8169#define ACP_SCRATCH_REG_43 0x12500AC170#define ACP_SCRATCH_REG_44 0x12500B0171#define ACP_SCRATCH_REG_45 0x12500B4172#define ACP_SCRATCH_REG_46 0x12500B8173#define ACP_SCRATCH_REG_47 0x12500BC174#define ACP_SCRATCH_REG_48 0x12500C0175#define ACP_SCRATCH_REG_49 0x12500C4176#define ACP_SCRATCH_REG_50 0x12500C8177#define ACP_SCRATCH_REG_51 0x12500CC178#define ACP_SCRATCH_REG_52 0x12500D0179#define ACP_SCRATCH_REG_53 0x12500D4180#define ACP_SCRATCH_REG_54 0x12500D8181#define ACP_SCRATCH_REG_55 0x12500DC182#define ACP_SCRATCH_REG_56 0x12500E0183#define ACP_SCRATCH_REG_57 0x12500E4184#define ACP_SCRATCH_REG_58 0x12500E8185#define ACP_SCRATCH_REG_59 0x12500EC186#define ACP_SCRATCH_REG_60 0x12500F0187#define ACP_SCRATCH_REG_61 0x12500F4188#define ACP_SCRATCH_REG_62 0x12500F8189#define ACP_SCRATCH_REG_63 0x12500FC190#define ACP_SCRATCH_REG_64 0x1250100191#define ACP_SCRATCH_REG_65 0x1250104192#define ACP_SCRATCH_REG_66 0x1250108193#define ACP_SCRATCH_REG_67 0x125010C194#define ACP_SCRATCH_REG_68 0x1250110195#define ACP_SCRATCH_REG_69 0x1250114196#define ACP_SCRATCH_REG_70 0x1250118197#define ACP_SCRATCH_REG_71 0x125011C198#define ACP_SCRATCH_REG_72 0x1250120199#define ACP_SCRATCH_REG_73 0x1250124200#define ACP_SCRATCH_REG_74 0x1250128201#define ACP_SCRATCH_REG_75 0x125012C202#define ACP_SCRATCH_REG_76 0x1250130203#define ACP_SCRATCH_REG_77 0x1250134204#define ACP_SCRATCH_REG_78 0x1250138205#define ACP_SCRATCH_REG_79 0x125013C206#define ACP_SCRATCH_REG_80 0x1250140207#define ACP_SCRATCH_REG_81 0x1250144208#define ACP_SCRATCH_REG_82 0x1250148209#define ACP_SCRATCH_REG_83 0x125014C210#define ACP_SCRATCH_REG_84 0x1250150211#define ACP_SCRATCH_REG_85 0x1250154212#define ACP_SCRATCH_REG_86 0x1250158213#define ACP_SCRATCH_REG_87 0x125015C214#define ACP_SCRATCH_REG_88 0x1250160215#define ACP_SCRATCH_REG_89 0x1250164216#define ACP_SCRATCH_REG_90 0x1250168217#define ACP_SCRATCH_REG_91 0x125016C218#define ACP_SCRATCH_REG_92 0x1250170219#define ACP_SCRATCH_REG_93 0x1250174220#define ACP_SCRATCH_REG_94 0x1250178221#define ACP_SCRATCH_REG_95 0x125017C222#define ACP_SCRATCH_REG_96 0x1250180223#define ACP_SCRATCH_REG_97 0x1250184224#define ACP_SCRATCH_REG_98 0x1250188225#define ACP_SCRATCH_REG_99 0x125018C226#define ACP_SCRATCH_REG_100 0x1250190227#define ACP_SCRATCH_REG_101 0x1250194228#define ACP_SCRATCH_REG_102 0x1250198229#define ACP_SCRATCH_REG_103 0x125019C230#define ACP_SCRATCH_REG_104 0x12501A0231#define ACP_SCRATCH_REG_105 0x12501A4232#define ACP_SCRATCH_REG_106 0x12501A8233#define ACP_SCRATCH_REG_107 0x12501AC234#define ACP_SCRATCH_REG_108 0x12501B0235#define ACP_SCRATCH_REG_109 0x12501B4236#define ACP_SCRATCH_REG_110 0x12501B8237#define ACP_SCRATCH_REG_111 0x12501BC238#define ACP_SCRATCH_REG_112 0x12501C0239#define ACP_SCRATCH_REG_113 0x12501C4240#define ACP_SCRATCH_REG_114 0x12501C8241#define ACP_SCRATCH_REG_115 0x12501CC242#define ACP_SCRATCH_REG_116 0x12501D0243#define ACP_SCRATCH_REG_117 0x12501D4244#define ACP_SCRATCH_REG_118 0x12501D8245#define ACP_SCRATCH_REG_119 0x12501DC246#define ACP_SCRATCH_REG_120 0x12501E0247#define ACP_SCRATCH_REG_121 0x12501E4248#define ACP_SCRATCH_REG_122 0x12501E8249#define ACP_SCRATCH_REG_123 0x12501EC250#define ACP_SCRATCH_REG_124 0x12501F0251#define ACP_SCRATCH_REG_125 0x12501F4252#define ACP_SCRATCH_REG_126 0x12501F8253#define ACP_SCRATCH_REG_127 0x12501FC254#define ACP_SCRATCH_REG_128 0x1250200255256// Registers from ACP_AUDIO_BUFFERS block257258#define ACP_I2S_RX_RINGBUFADDR 0x1242000259#define ACP_I2S_RX_RINGBUFSIZE 0x1242004260#define ACP_I2S_RX_LINKPOSITIONCNTR 0x1242008261#define ACP_I2S_RX_FIFOADDR 0x124200C262#define ACP_I2S_RX_FIFOSIZE 0x1242010263#define ACP_I2S_RX_DMA_SIZE 0x1242014264#define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x1242018265#define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW 0x124201C266#define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x1242020267#define ACP_I2S_TX_RINGBUFADDR 0x1242024268#define ACP_I2S_TX_RINGBUFSIZE 0x1242028269#define ACP_I2S_TX_LINKPOSITIONCNTR 0x124202C270#define ACP_I2S_TX_FIFOADDR 0x1242030271#define ACP_I2S_TX_FIFOSIZE 0x1242034272#define ACP_I2S_TX_DMA_SIZE 0x1242038273#define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x124203C274#define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW 0x1242040275#define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x1242044276#define ACP_BT_RX_RINGBUFADDR 0x1242048277#define ACP_BT_RX_RINGBUFSIZE 0x124204C278#define ACP_BT_RX_LINKPOSITIONCNTR 0x1242050279#define ACP_BT_RX_FIFOADDR 0x1242054280#define ACP_BT_RX_FIFOSIZE 0x1242058281#define ACP_BT_RX_DMA_SIZE 0x124205C282#define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH 0x1242060283#define ACP_BT_RX_LINEARPOSITIONCNTR_LOW 0x1242064284#define ACP_BT_RX_INTR_WATERMARK_SIZE 0x1242068285#define ACP_BT_TX_RINGBUFADDR 0x124206C286#define ACP_BT_TX_RINGBUFSIZE 0x1242070287#define ACP_BT_TX_LINKPOSITIONCNTR 0x1242074288#define ACP_BT_TX_FIFOADDR 0x1242078289#define ACP_BT_TX_FIFOSIZE 0x124207C290#define ACP_BT_TX_DMA_SIZE 0x1242080291#define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH 0x1242084292#define ACP_BT_TX_LINEARPOSITIONCNTR_LOW 0x1242088293#define ACP_BT_TX_INTR_WATERMARK_SIZE 0x124208C294#define ACP_HS_RX_RINGBUFADDR 0x1242090295#define ACP_HS_RX_RINGBUFSIZE 0x1242094296#define ACP_HS_RX_LINKPOSITIONCNTR 0x1242098297#define ACP_HS_RX_FIFOADDR 0x124209C298#define ACP_HS_RX_FIFOSIZE 0x12420A0299#define ACP_HS_RX_DMA_SIZE 0x12420A4300#define ACP_HS_RX_LINEARPOSITIONCNTR_HIGH 0x12420A8301#define ACP_HS_RX_LINEARPOSITIONCNTR_LOW 0x12420AC302#define ACP_HS_RX_INTR_WATERMARK_SIZE 0x12420B0303#define ACP_HS_TX_RINGBUFADDR 0x12420B4304#define ACP_HS_TX_RINGBUFSIZE 0x12420B8305#define ACP_HS_TX_LINKPOSITIONCNTR 0x12420BC306#define ACP_HS_TX_FIFOADDR 0x12420C0307#define ACP_HS_TX_FIFOSIZE 0x12420C4308#define ACP_HS_TX_DMA_SIZE 0x12420C8309#define ACP_HS_TX_LINEARPOSITIONCNTR_HIGH 0x12420CC310#define ACP_HS_TX_LINEARPOSITIONCNTR_LOW 0x12420D0311#define ACP_HS_TX_INTR_WATERMARK_SIZE 0x12420D4312313// Registers from ACP_I2S_TDM block314315#define ACP_I2STDM_IER 0x1242400316#define ACP_I2STDM_IRER 0x1242404317#define ACP_I2STDM_RXFRMT 0x1242408318#define ACP_I2STDM_ITER 0x124240C319#define ACP_I2STDM_TXFRMT 0x1242410320321// Registers from ACP_BT_TDM block322323#define ACP_BTTDM_IER 0x1242800324#define ACP_BTTDM_IRER 0x1242804325#define ACP_BTTDM_RXFRMT 0x1242808326#define ACP_BTTDM_ITER 0x124280C327#define ACP_BTTDM_TXFRMT 0x1242810328329// Registers from ACP_WOV block330331#define ACP_WOV_PDM_ENABLE 0x1242C04332#define ACP_WOV_PDM_DMA_ENABLE 0x1242C08333#define ACP_WOV_RX_RINGBUFADDR 0x1242C0C334#define ACP_WOV_RX_RINGBUFSIZE 0x1242C10335#define ACP_WOV_RX_LINKPOSITIONCNTR 0x1242C14336#define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x1242C18337#define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x1242C1C338#define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x1242C20339#define ACP_WOV_PDM_FIFO_FLUSH 0x1242C24340#define ACP_WOV_PDM_NO_OF_CHANNELS 0x1242C28341#define ACP_WOV_PDM_DECIMATION_FACTOR 0x1242C2C342#define ACP_WOV_PDM_VAD_CTRL 0x1242C30343#define ACP_WOV_BUFFER_STATUS 0x1242C58344#define ACP_WOV_MISC_CTRL 0x1242C5C345#define ACP_WOV_CLK_CTRL 0x1242C60346#define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x1242C64347#define ACP_WOV_ERROR_STATUS_REGISTER 0x1242C68348#endif349350351