/* SPDX-License-Identifier: GPL-2.0 */1/*2* Copyright 2017-2021 NXP3*/45#ifndef __FSL_RPMSG_H6#define __FSL_RPMSG_H78/*9* struct fsl_rpmsg_soc_data10* @rates: supported rates11* @formats: supported formats12*/13struct fsl_rpmsg_soc_data {14int rates;15u64 formats;16};1718/*19* struct fsl_rpmsg - rpmsg private data20*21* @ipg: ipg clock for cpu dai (SAI)22* @mclk: master clock for cpu dai (SAI)23* @dma: clock for dma device24* @pll8k: parent clock for multiple of 8kHz frequency25* @pll11k: parent clock for multiple of 11kHz frequency26* @card_pdev: Platform_device pointer to register a sound card27* @soc_data: soc specific data28* @mclk_streams: Active streams that are using baudclk29* @force_lpa: force enable low power audio routine if condition satisfy30* @enable_lpa: enable low power audio routine according to dts setting31* @buffer_size: pre allocated dma buffer size32*/33struct fsl_rpmsg {34struct clk *ipg;35struct clk *mclk;36struct clk *dma;37struct clk *pll8k;38struct clk *pll11k;39struct platform_device *card_pdev;40const struct fsl_rpmsg_soc_data *soc_data;41unsigned int mclk_streams;42int force_lpa;43int enable_lpa;44int buffer_size[2];45};46#endif /* __FSL_RPMSG_H */474849