CoCalc -- hi6210-i2s.h

GitHub Repository: torvalds/linux
Path: blob/master/sound/soc/hisilicon/hi6210-i2s.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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 * linux/sound/soc/hisilicon/hi6210-i2s.h
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 *
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 * Copyright (C) 2015 Linaro, Ltd
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 * Author: Andy Green <[email protected]>
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 *
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 * Note at least on 6220, S2 == BT, S1 == Digital FM Radio IF
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 */
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#ifndef _HI6210_I2S_H
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#define _HI6210_I2S_H
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#define HII2S_SW_RST_N				0
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#define HII2S_SW_RST_N__STEREO_UPLINK_WORDLEN_SHIFT			28
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#define HII2S_SW_RST_N__STEREO_UPLINK_WORDLEN_MASK			3
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#define HII2S_SW_RST_N__THIRDMD_UPLINK_WORDLEN_SHIFT			26
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#define HII2S_SW_RST_N__THIRDMD_UPLINK_WORDLEN_MASK			3
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#define HII2S_SW_RST_N__VOICE_UPLINK_WORDLEN_SHIFT			24
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#define HII2S_SW_RST_N__VOICE_UPLINK_WORDLEN_MASK			3
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#define HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT				20
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#define HII2S_SW_RST_N__ST_DL_WORDLEN_MASK				3
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#define HII2S_SW_RST_N__THIRDMD_DLINK_WORDLEN_SHIFT			18
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#define HII2S_SW_RST_N__THIRDMD_DLINK_WORDLEN_MASK			3
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#define HII2S_SW_RST_N__VOICE_DLINK_WORDLEN_SHIFT			16
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#define HII2S_SW_RST_N__VOICE_DLINK_WORDLEN_MASK			3
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#define HII2S_SW_RST_N__SW_RST_N					BIT(0)
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enum hi6210_bits {
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	HII2S_BITS_16,
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	HII2S_BITS_18,
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	HII2S_BITS_20,
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	HII2S_BITS_24,
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};
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#define HII2S_IF_CLK_EN_CFG			4
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#define HII2S_IF_CLK_EN_CFG__THIRDMD_UPLINK_EN				BIT(25)
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#define HII2S_IF_CLK_EN_CFG__THIRDMD_DLINK_EN				BIT(24)
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#define HII2S_IF_CLK_EN_CFG__S3_IF_CLK_EN				BIT(20)
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#define HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN				BIT(16)
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#define HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN				BIT(15)
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#define HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN				BIT(14)
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#define HII2S_IF_CLK_EN_CFG__S2_IR_PGA_EN				BIT(13)
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#define HII2S_IF_CLK_EN_CFG__S2_IL_PGA_EN				BIT(12)
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#define HII2S_IF_CLK_EN_CFG__S1_IR_PGA_EN				BIT(10)
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#define HII2S_IF_CLK_EN_CFG__S1_IL_PGA_EN				BIT(9)
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#define HII2S_IF_CLK_EN_CFG__S1_IF_CLK_EN				BIT(8)
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#define HII2S_IF_CLK_EN_CFG__VOICE_DLINK_SRC_EN				BIT(7)
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#define HII2S_IF_CLK_EN_CFG__VOICE_DLINK_EN				BIT(6)
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#define HII2S_IF_CLK_EN_CFG__ST_DL_R_EN					BIT(5)
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#define HII2S_IF_CLK_EN_CFG__ST_DL_L_EN					BIT(4)
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#define HII2S_IF_CLK_EN_CFG__VOICE_UPLINK_R_EN				BIT(3)
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#define HII2S_IF_CLK_EN_CFG__VOICE_UPLINK_L_EN				BIT(2)
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#define HII2S_IF_CLK_EN_CFG__STEREO_UPLINK_R_EN				BIT(1)
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#define HII2S_IF_CLK_EN_CFG__STEREO_UPLINK_L_EN				BIT(0)
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#define HII2S_DIG_FILTER_CLK_EN_CFG		8
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#define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN			BIT(30)
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#define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_HBF2I_EN			BIT(28)
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#define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN			BIT(25)
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#define HII2S_DIG_FILTER_CLK_EN_CFG__DACR_AGC_EN			BIT(24)
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#define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_SDM_EN			BIT(22)
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#define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_HBF2I_EN			BIT(20)
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#define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_MIXER_EN			BIT(17)
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#define HII2S_DIG_FILTER_CLK_EN_CFG__DACL_AGC_EN			BIT(16)
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#define HII2S_FS_CFG				0xc
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#define HII2S_FS_CFG__FS_S2_SHIFT					28
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#define HII2S_FS_CFG__FS_S2_MASK					7
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#define HII2S_FS_CFG__FS_S1_SHIFT					24
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#define HII2S_FS_CFG__FS_S1_MASK					7
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#define HII2S_FS_CFG__FS_ADCLR_SHIFT					20
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#define HII2S_FS_CFG__FS_ADCLR_MASK					7
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#define HII2S_FS_CFG__FS_DACLR_SHIFT					16
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#define HII2S_FS_CFG__FS_DACLR_MASK					7
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#define HII2S_FS_CFG__FS_ST_DL_R_SHIFT					8
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#define HII2S_FS_CFG__FS_ST_DL_R_MASK					7
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#define HII2S_FS_CFG__FS_ST_DL_L_SHIFT					4
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#define HII2S_FS_CFG__FS_ST_DL_L_MASK					7
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#define HII2S_FS_CFG__FS_VOICE_DLINK_SHIFT				0
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#define HII2S_FS_CFG__FS_VOICE_DLINK_MASK				7
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enum hi6210_i2s_rates {
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	HII2S_FS_RATE_8KHZ = 0,
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	HII2S_FS_RATE_16KHZ = 1,
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	HII2S_FS_RATE_32KHZ = 2,
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	HII2S_FS_RATE_48KHZ = 4,
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	HII2S_FS_RATE_96KHZ = 5,
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	HII2S_FS_RATE_192KHZ = 6,
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};
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#define HII2S_I2S_CFG				0x10
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#define HII2S_I2S_CFG__S2_IF_TX_EN					BIT(31)
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#define HII2S_I2S_CFG__S2_IF_RX_EN					BIT(30)
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#define HII2S_I2S_CFG__S2_FRAME_MODE					BIT(29)
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#define HII2S_I2S_CFG__S2_MST_SLV					BIT(28)
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#define HII2S_I2S_CFG__S2_LRCK_MODE					BIT(27)
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#define HII2S_I2S_CFG__S2_CHNNL_MODE					BIT(26)
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#define HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT			24
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#define HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_MASK			3
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#define HII2S_I2S_CFG__S2_DIRECT_LOOP_SHIFT				22
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#define HII2S_I2S_CFG__S2_DIRECT_LOOP_MASK				3
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#define HII2S_I2S_CFG__S2_TX_CLK_SEL					BIT(21)
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#define HII2S_I2S_CFG__S2_RX_CLK_SEL					BIT(20)
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#define HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT				BIT(19)
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#define HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT				16
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#define HII2S_I2S_CFG__S2_FUNC_MODE_MASK				7
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#define HII2S_I2S_CFG__S1_IF_TX_EN					BIT(15)
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#define HII2S_I2S_CFG__S1_IF_RX_EN					BIT(14)
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#define HII2S_I2S_CFG__S1_FRAME_MODE					BIT(13)
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#define HII2S_I2S_CFG__S1_MST_SLV					BIT(12)
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#define HII2S_I2S_CFG__S1_LRCK_MODE					BIT(11)
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#define HII2S_I2S_CFG__S1_CHNNL_MODE					BIT(10)
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#define HII2S_I2S_CFG__S1_CODEC_IO_WORDLENGTH_SHIFT			8
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#define HII2S_I2S_CFG__S1_CODEC_IO_WORDLENGTH_MASK			3
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#define HII2S_I2S_CFG__S1_DIRECT_LOOP_SHIFT				6
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#define HII2S_I2S_CFG__S1_DIRECT_LOOP_MASK				3
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#define HII2S_I2S_CFG__S1_TX_CLK_SEL					BIT(5)
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#define HII2S_I2S_CFG__S1_RX_CLK_SEL					BIT(4)
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#define HII2S_I2S_CFG__S1_CODEC_DATA_FORMAT				BIT(3)
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#define HII2S_I2S_CFG__S1_FUNC_MODE_SHIFT				0
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#define HII2S_I2S_CFG__S1_FUNC_MODE_MASK				7
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enum hi6210_i2s_formats {
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	HII2S_FORMAT_I2S,
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	HII2S_FORMAT_PCM_STD,
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	HII2S_FORMAT_PCM_USER,
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	HII2S_FORMAT_LEFT_JUST,
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	HII2S_FORMAT_RIGHT_JUST,
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};
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#define HII2S_DIG_FILTER_MODULE_CFG		0x14
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#define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_GAIN_SHIFT		28
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#define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_GAIN_MASK		3
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#define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN4_MUTE		BIT(27)
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#define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN3_MUTE		BIT(26)
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#define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE		BIT(25)
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#define HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN1_MUTE		BIT(24)
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#define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_GAIN_SHIFT		20
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#define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_GAIN_MASK		3
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#define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN4_MUTE		BIT(19)
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#define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN3_MUTE		BIT(18)
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#define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN2_MUTE		BIT(17)
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#define HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN1_MUTE		BIT(16)
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#define HII2S_DIG_FILTER_MODULE_CFG__SW_DACR_SDM_DITHER			BIT(9)
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#define HII2S_DIG_FILTER_MODULE_CFG__SW_DACL_SDM_DITHER			BIT(8)
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#define HII2S_DIG_FILTER_MODULE_CFG__LM_CODEC_DAC2ADC_SHIFT		4
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#define HII2S_DIG_FILTER_MODULE_CFG__LM_CODEC_DAC2ADC_MASK		7
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#define HII2S_DIG_FILTER_MODULE_CFG__RM_CODEC_DAC2ADC_SHIFT		0
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#define HII2S_DIG_FILTER_MODULE_CFG__RM_CODEC_DAC2ADC_MASK		7
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enum hi6210_gains {
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	HII2S_GAIN_100PC,
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	HII2S_GAIN_50PC,
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	HII2S_GAIN_25PC,
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};
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#define HII2S_MUX_TOP_MODULE_CFG		0x18
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#define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_GAIN_SHIFT		14
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#define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_GAIN_MASK		3
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#define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN2_MUTE		BIT(13)
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#define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN1_MUTE		BIT(12)
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#define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_GAIN_SHIFT		10
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#define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_GAIN_MASK			3
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#define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN2_MUTE			BIT(9)
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#define HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE			BIT(8)
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#define HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_RDY				BIT(6)
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#define HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_MODE_SHIFT			4
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#define HII2S_MUX_TOP_MODULE_CFG__S2_OL_SRC_MODE_MASK			3
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#define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_RDY			BIT(3)
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#define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_MODE_SHIFT		0
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#define HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_SRC_MODE_MASK		7
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enum hi6210_s2_src_mode {
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	HII2S_S2_SRC_MODE_3,
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	HII2S_S2_SRC_MODE_12,
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	HII2S_S2_SRC_MODE_6,
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	HII2S_S2_SRC_MODE_2,
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};
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enum hi6210_voice_dlink_src_mode {
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	HII2S_VOICE_DL_SRC_MODE_12 = 1,
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	HII2S_VOICE_DL_SRC_MODE_6,
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	HII2S_VOICE_DL_SRC_MODE_2,
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	HII2S_VOICE_DL_SRC_MODE_3,
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};
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#define HII2S_ADC_PGA_CFG			0x1c
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#define HII2S_S1_INPUT_PGA_CFG			0x20
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#define HII2S_S2_INPUT_PGA_CFG			0x24
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#define HII2S_ST_DL_PGA_CFG			0x28
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#define HII2S_VOICE_SIDETONE_DLINK_PGA_CFG	0x2c
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#define HII2S_APB_AFIFO_CFG_1			0x30
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#define HII2S_APB_AFIFO_CFG_2			0x34
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#define HII2S_ST_DL_FIFO_TH_CFG			0x38
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#define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT			24
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#define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_MASK			0x1f
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#define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT			16
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#define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_MASK			0x1f
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#define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT			8
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#define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_MASK			0x1f
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#define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT			0
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#define HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_MASK			0x1f
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#define HII2S_STEREO_UPLINK_FIFO_TH_CFG		0x3c
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#define HII2S_VOICE_UPLINK_FIFO_TH_CFG		0x40
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#define HII2S_CODEC_IRQ_MASK			0x44
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#define HII2S_CODEC_IRQ				0x48
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#define HII2S_DACL_AGC_CFG_1			0x4c
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#define HII2S_DACL_AGC_CFG_2			0x50
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#define HII2S_DACR_AGC_CFG_1			0x54
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#define HII2S_DACR_AGC_CFG_2			0x58
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#define HII2S_DMIC_SIF_CFG			0x5c
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#define HII2S_MISC_CFG				0x60
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#define HII2S_MISC_CFG__THIRDMD_DLINK_TEST_SEL				BIT(17)
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#define HII2S_MISC_CFG__THIRDMD_DLINK_DIN_SEL				BIT(16)
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#define HII2S_MISC_CFG__S3_DOUT_RIGHT_SEL				BIT(14)
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#define HII2S_MISC_CFG__S3_DOUT_LEFT_SEL				BIT(13)
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#define HII2S_MISC_CFG__S3_DIN_TEST_SEL					BIT(12)
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#define HII2S_MISC_CFG__VOICE_DLINK_SRC_UP_DOUT_VLD_SEL			BIT(8)
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#define HII2S_MISC_CFG__VOICE_DLINK_TEST_SEL				BIT(7)
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#define HII2S_MISC_CFG__VOICE_DLINK_DIN_SEL				BIT(6)
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#define HII2S_MISC_CFG__ST_DL_TEST_SEL					BIT(4)
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#define HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL				BIT(3)
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#define HII2S_MISC_CFG__S2_DOUT_TEST_SEL				BIT(2)
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#define HII2S_MISC_CFG__S1_DOUT_TEST_SEL				BIT(1)
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#define HII2S_MISC_CFG__S2_DOUT_LEFT_SEL				BIT(0)
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#define HII2S_S2_SRC_CFG			0x64
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#define HII2S_MEM_CFG				0x68
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#define HII2S_THIRDMD_PCM_PGA_CFG		0x6c
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#define HII2S_THIRD_MODEM_FIFO_TH		0x70
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#define HII2S_S3_ANTI_FREQ_JITTER_TX_INC_CNT	0x74
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#define HII2S_S3_ANTI_FREQ_JITTER_TX_DEC_CNT	0x78
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#define HII2S_S3_ANTI_FREQ_JITTER_RX_INC_CNT	0x7c
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#define HII2S_S3_ANTI_FREQ_JITTER_RX_DEC_CNT	0x80
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#define HII2S_ANTI_FREQ_JITTER_EN		0x84
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#define HII2S_CLK_SEL				0x88
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/* 0 = BT owns the i2s */
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#define HII2S_CLK_SEL__I2S_BT_FM_SEL					BIT(0)
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/* 0 = internal source, 1 = ext */
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#define HII2S_CLK_SEL__EXT_12_288MHZ_SEL				BIT(1)
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#define HII2S_THIRDMD_DLINK_CHANNEL		0xe8
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#define HII2S_THIRDMD_ULINK_CHANNEL		0xec
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#define HII2S_VOICE_DLINK_CHANNEL		0xf0
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/* shovel data in here for playback */
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#define HII2S_ST_DL_CHANNEL			0xf4
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#define HII2S_STEREO_UPLINK_CHANNEL		0xf8
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#define HII2S_VOICE_UPLINK_CHANNEL		0xfc
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#endif/* _HI6210_I2S_H */
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