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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/sound/soc/intel/keembay/kmb_platform.h
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/* SPDX-License-Identifier: GPL-2.0-only */

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/*

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 *  Intel KeemBay Platform driver

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 *

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 *  Copyright (C) 2020 Intel Corporation.

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 *

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 */

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#ifndef KMB_PLATFORM_H_

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#define KMB_PLATFORM_H_

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#include <linux/bits.h>

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#include <linux/bitfield.h>

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#include <linux/types.h>

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#include <sound/dmaengine_pcm.h>

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/* Register values with reference to KMB databook v1.1 */

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/* common register for all channel */

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#define IER		0x000

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#define IRER		0x004

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#define ITER		0x008

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#define CER		0x00C

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#define CCR		0x010

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#define RXFFR		0x014

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#define TXFFR		0x018

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/* Interrupt status register fields */

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#define ISR_TXFO	BIT(5)

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#define ISR_TXFE	BIT(4)

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#define ISR_RXFO	BIT(1)

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#define ISR_RXDA	BIT(0)

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/* I2S Tx Rx Registers for all channels */

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#define LRBR_LTHR(x)	(0x40 * (x) + 0x020)

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#define RRBR_RTHR(x)	(0x40 * (x) + 0x024)

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#define RER(x)		(0x40 * (x) + 0x028)

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#define TER(x)		(0x40 * (x) + 0x02C)

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#define RCR(x)		(0x40 * (x) + 0x030)

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#define TCR(x)		(0x40 * (x) + 0x034)

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#define ISR(x)		(0x40 * (x) + 0x038)

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#define IMR(x)		(0x40 * (x) + 0x03C)

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#define ROR(x)		(0x40 * (x) + 0x040)

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#define TOR(x)		(0x40 * (x) + 0x044)

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#define RFCR(x)		(0x40 * (x) + 0x048)

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#define TFCR(x)		(0x40 * (x) + 0x04C)

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#define RFF(x)		(0x40 * (x) + 0x050)

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#define TFF(x)		(0x40 * (x) + 0x054)

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/* I2S COMP Registers */

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#define I2S_COMP_PARAM_2	0x01F0

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#define I2S_COMP_PARAM_1	0x01F4

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#define I2S_COMP_VERSION	0x01F8

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#define I2S_COMP_TYPE		0x01FC

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/* PSS_GEN_CTRL_I2S_GEN_CFG_0 Registers */

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#define I2S_GEN_CFG_0		0x000

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#define PSS_CPR_RST_EN		0x010

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#define PSS_CPR_RST_SET		0x014

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#define PSS_CPR_CLK_CLR		0x000

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#define PSS_CPR_AUX_RST_EN	0x070

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#define CLOCK_PROVIDER_MODE	BIT(13)

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/* Interrupt Flag */

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#define TX_INT_FLAG		GENMASK(5, 4)

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#define RX_INT_FLAG		GENMASK(1, 0)

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/*

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 * Component parameter register fields - define the I2S block's

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 * configuration.

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 */

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#define	COMP1_TX_WORDSIZE_3(r)		FIELD_GET(GENMASK(27, 25), (r))

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#define	COMP1_TX_WORDSIZE_2(r)		FIELD_GET(GENMASK(24, 22), (r))

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#define	COMP1_TX_WORDSIZE_1(r)		FIELD_GET(GENMASK(21, 19), (r))

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#define	COMP1_TX_WORDSIZE_0(r)		FIELD_GET(GENMASK(18, 16), (r))

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#define	COMP1_RX_ENABLED(r)		FIELD_GET(BIT(6), (r))

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#define	COMP1_TX_ENABLED(r)		FIELD_GET(BIT(5), (r))

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#define	COMP1_MODE_EN(r)		FIELD_GET(BIT(4), (r))

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#define	COMP1_APB_DATA_WIDTH(r)		FIELD_GET(GENMASK(1, 0), (r))

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#define	COMP2_RX_WORDSIZE_3(r)		FIELD_GET(GENMASK(12, 10), (r))

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#define	COMP2_RX_WORDSIZE_2(r)		FIELD_GET(GENMASK(9, 7), (r))

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#define	COMP2_RX_WORDSIZE_1(r)		FIELD_GET(GENMASK(5, 3), (r))

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#define	COMP2_RX_WORDSIZE_0(r)		FIELD_GET(GENMASK(2, 0), (r))

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/* Add 1 to the below registers to indicate the actual size */

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#define	COMP1_TX_CHANNELS(r)	(FIELD_GET(GENMASK(10, 9), (r)) + 1)

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#define	COMP1_RX_CHANNELS(r)	(FIELD_GET(GENMASK(8, 7), (r)) + 1)

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#define	COMP1_FIFO_DEPTH(r)	(FIELD_GET(GENMASK(3, 2), (r)) + 1)

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/* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */

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#define	COMP_MAX_WORDSIZE	8	/* 3 bits register width */

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#define MAX_CHANNEL_NUM		8

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#define MIN_CHANNEL_NUM		2

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#define MAX_ISR			4

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#define TWO_CHANNEL_SUPPORT	2	/* up to 2.0 */

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#define FOUR_CHANNEL_SUPPORT	4	/* up to 3.1 */

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#define SIX_CHANNEL_SUPPORT	6	/* up to 5.1 */

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#define EIGHT_CHANNEL_SUPPORT	8	/* up to 7.1 */

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#define DWC_I2S_PLAY	BIT(0)

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#define DWC_I2S_RECORD	BIT(1)

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#define DW_I2S_CONSUMER	BIT(2)

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#define DW_I2S_PROVIDER	BIT(3)

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#define I2S_RXDMA	0x01C0

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#define I2S_RRXDMA	0x01C4

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#define I2S_TXDMA	0x01C8

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#define I2S_RTXDMA	0x01CC

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#define I2S_DMACR	0x0200

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#define I2S_DMAEN_RXBLOCK	(1 << 16)

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#define I2S_DMAEN_TXBLOCK	(1 << 17)

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/*

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 * struct i2s_clk_config_data - represent i2s clk configuration data

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 * @chan_nr: number of channel

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 * @data_width: number of bits per sample (8/16/24/32 bit)

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 * @sample_rate: sampling frequency (8Khz, 16Khz, 48Khz)

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 */

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struct i2s_clk_config_data {

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	int chan_nr;

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	u32 data_width;

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	u32 sample_rate;

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};

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struct kmb_i2s_info {

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	void __iomem *i2s_base;

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	void __iomem *pss_base;

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	struct clk *clk_i2s;

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	struct clk *clk_apb;

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	int active;

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	unsigned int capability;

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	unsigned int i2s_reg_comp1;

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	unsigned int i2s_reg_comp2;

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	struct device *dev;

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	u32 ccr;

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	u32 xfer_resolution;

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	u32 fifo_th;

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	bool clock_provider;

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	/* data related to DMA transfers b/w i2s and DMAC */

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	struct snd_dmaengine_dai_dma_data play_dma_data;

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	struct snd_dmaengine_dai_dma_data capture_dma_data;

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	struct i2s_clk_config_data config;

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	int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);

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	/* data related to PIO transfers */

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	bool use_pio;

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	struct snd_pcm_substream *tx_substream;

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	struct snd_pcm_substream *rx_substream;

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	unsigned int tx_ptr;

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	unsigned int rx_ptr;

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	bool iec958_fmt;

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};

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#endif /* KMB_PLATFORM_H_ */

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