Path: blob/master/sound/soc/mediatek/mt6797/mt6797-afe-clk.c
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// SPDX-License-Identifier: GPL-2.01//2// mt6797-afe-clk.c -- Mediatek 6797 afe clock ctrl3//4// Copyright (c) 2018 MediaTek Inc.5// Author: KaiChieh Chuang <[email protected]>67#include <linux/clk.h>89#include "mt6797-afe-common.h"10#include "mt6797-afe-clk.h"1112enum {13CLK_INFRA_SYS_AUD,14CLK_INFRA_SYS_AUD_26M,15CLK_TOP_MUX_AUD,16CLK_TOP_MUX_AUD_BUS,17CLK_TOP_SYSPLL3_D4,18CLK_TOP_SYSPLL1_D4,19CLK_CLK26M,20CLK_NUM21};2223static const char *aud_clks[CLK_NUM] = {24[CLK_INFRA_SYS_AUD] = "infra_sys_audio_clk",25[CLK_INFRA_SYS_AUD_26M] = "infra_sys_audio_26m",26[CLK_TOP_MUX_AUD] = "top_mux_audio",27[CLK_TOP_MUX_AUD_BUS] = "top_mux_aud_intbus",28[CLK_TOP_SYSPLL3_D4] = "top_sys_pll3_d4",29[CLK_TOP_SYSPLL1_D4] = "top_sys_pll1_d4",30[CLK_CLK26M] = "top_clk26m_clk",31};3233int mt6797_init_clock(struct mtk_base_afe *afe)34{35struct mt6797_afe_private *afe_priv = afe->platform_priv;36int i;3738afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),39GFP_KERNEL);40if (!afe_priv->clk)41return -ENOMEM;4243for (i = 0; i < CLK_NUM; i++) {44afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);45if (IS_ERR(afe_priv->clk[i])) {46dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",47__func__, aud_clks[i],48PTR_ERR(afe_priv->clk[i]));49return PTR_ERR(afe_priv->clk[i]);50}51}5253return 0;54}5556int mt6797_afe_enable_clock(struct mtk_base_afe *afe)57{58struct mt6797_afe_private *afe_priv = afe->platform_priv;59int ret;6061ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUD]);62if (ret) {63dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",64__func__, aud_clks[CLK_INFRA_SYS_AUD], ret);65goto CLK_INFRA_SYS_AUDIO_ERR;66}6768ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);69if (ret) {70dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",71__func__, aud_clks[CLK_INFRA_SYS_AUD_26M], ret);72goto CLK_INFRA_SYS_AUD_26M_ERR;73}7475ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD]);76if (ret) {77dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",78__func__, aud_clks[CLK_TOP_MUX_AUD], ret);79goto CLK_MUX_AUDIO_ERR;80}8182ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD],83afe_priv->clk[CLK_CLK26M]);84if (ret) {85dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",86__func__, aud_clks[CLK_TOP_MUX_AUD],87aud_clks[CLK_CLK26M], ret);88goto CLK_MUX_AUDIO_ERR;89}9091ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);92if (ret) {93dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",94__func__, aud_clks[CLK_TOP_MUX_AUD_BUS], ret);95goto CLK_MUX_AUDIO_INTBUS_ERR;96}9798return ret;99100CLK_MUX_AUDIO_INTBUS_ERR:101clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);102CLK_MUX_AUDIO_ERR:103clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD]);104CLK_INFRA_SYS_AUD_26M_ERR:105clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);106CLK_INFRA_SYS_AUDIO_ERR:107clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD]);108109return 0;110}111112int mt6797_afe_disable_clock(struct mtk_base_afe *afe)113{114struct mt6797_afe_private *afe_priv = afe->platform_priv;115116clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_BUS]);117clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD]);118clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD_26M]);119clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUD]);120121return 0;122}123124125