Path: blob/master/sound/soc/mediatek/mt8183/mt8183-afe-clk.h
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/* SPDX-License-Identifier: GPL-2.0 */1/*2* mt8183-afe-clk.h -- Mediatek 8183 afe clock ctrl definition3*4* Copyright (c) 2018 MediaTek Inc.5* Author: KaiChieh Chuang <[email protected]>6*/78#ifndef _MT8183_AFE_CLK_H_9#define _MT8183_AFE_CLK_H_1011/* APLL */12#define APLL1_W_NAME "APLL1"13#define APLL2_W_NAME "APLL2"14enum {15MT8183_APLL1 = 0,16MT8183_APLL2,17};1819struct mtk_base_afe;2021int mt8183_init_clock(struct mtk_base_afe *afe);22int mt8183_afe_enable_clock(struct mtk_base_afe *afe);23int mt8183_afe_disable_clock(struct mtk_base_afe *afe);2425int mt8183_apll1_enable(struct mtk_base_afe *afe);26void mt8183_apll1_disable(struct mtk_base_afe *afe);2728int mt8183_apll2_enable(struct mtk_base_afe *afe);29void mt8183_apll2_disable(struct mtk_base_afe *afe);3031int mt8183_get_apll_rate(struct mtk_base_afe *afe, int apll);32int mt8183_get_apll_by_rate(struct mtk_base_afe *afe, int rate);33int mt8183_get_apll_by_name(struct mtk_base_afe *afe, const char *name);3435int mt8183_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate);36void mt8183_mck_disable(struct mtk_base_afe *afe, int mck_id);37#endif383940