Book a Demo!
CoCalc Logo Icon
StoreFeaturesDocsShareSupportNewsAboutPoliciesSign UpSign In
torvalds
GitHub Repository: torvalds/linux
Path: blob/master/sound/soc/mediatek/mt8183/mt8183-dai-adda.c
26488 views
1
// SPDX-License-Identifier: GPL-2.0
2
//
3
// MediaTek ALSA SoC Audio DAI ADDA Control
4
//
5
// Copyright (c) 2018 MediaTek Inc.
6
// Author: KaiChieh Chuang <[email protected]>
7
8
#include <linux/regmap.h>
9
#include <linux/delay.h>
10
#include "mt8183-afe-common.h"
11
#include "mt8183-interconnection.h"
12
#include "mt8183-reg.h"
13
#include "../common/mtk-dai-adda-common.h"
14
15
enum {
16
AUDIO_SDM_LEVEL_MUTE = 0,
17
AUDIO_SDM_LEVEL_NORMAL = 0x1d,
18
/* if you change level normal */
19
/* you need to change formula of hp impedance and dc trim too */
20
};
21
22
/* dai component */
23
static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
24
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0),
25
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0),
26
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0),
27
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN3,
28
I_ADDA_UL_CH2, 1, 0),
29
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN3,
30
I_ADDA_UL_CH1, 1, 0),
31
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN3,
32
I_PCM_1_CAP_CH1, 1, 0),
33
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN3,
34
I_PCM_2_CAP_CH1, 1, 0),
35
};
36
37
static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
38
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN4, I_DL1_CH1, 1, 0),
39
SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN4, I_DL1_CH2, 1, 0),
40
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN4, I_DL2_CH1, 1, 0),
41
SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN4, I_DL2_CH2, 1, 0),
42
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN4, I_DL3_CH1, 1, 0),
43
SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN4, I_DL3_CH2, 1, 0),
44
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN4,
45
I_ADDA_UL_CH2, 1, 0),
46
SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN4,
47
I_ADDA_UL_CH1, 1, 0),
48
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN4,
49
I_PCM_1_CAP_CH1, 1, 0),
50
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN4,
51
I_PCM_2_CAP_CH1, 1, 0),
52
SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN4,
53
I_PCM_1_CAP_CH2, 1, 0),
54
SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN4,
55
I_PCM_2_CAP_CH2, 1, 0),
56
};
57
58
static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
59
struct snd_kcontrol *kcontrol,
60
int event)
61
{
62
struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
63
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
64
struct mt8183_afe_private *afe_priv = afe->platform_priv;
65
66
dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
67
__func__, w->name, event);
68
69
switch (event) {
70
case SND_SOC_DAPM_PRE_PMU:
71
/* update setting to dmic */
72
if (afe_priv->mtkaif_dmic) {
73
/* mtkaif_rxif_data_mode = 1, dmic */
74
regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
75
0x1, 0x1);
76
77
/* dmic mode, 3.25M*/
78
regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
79
0x0, 0xf << 20);
80
regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
81
0x0, 0x1 << 5);
82
regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
83
0x0, 0x3 << 14);
84
85
/* turn on dmic, ch1, ch2 */
86
regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
87
0x1 << 1, 0x1 << 1);
88
regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
89
0x3 << 21, 0x3 << 21);
90
}
91
break;
92
case SND_SOC_DAPM_POST_PMD:
93
/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
94
usleep_range(125, 135);
95
break;
96
default:
97
break;
98
}
99
100
return 0;
101
}
102
103
/* mtkaif dmic */
104
static const char * const mt8183_adda_off_on_str[] = {
105
"Off", "On"
106
};
107
108
static const struct soc_enum mt8183_adda_enum[] = {
109
SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8183_adda_off_on_str),
110
mt8183_adda_off_on_str),
111
};
112
113
static int mt8183_adda_dmic_get(struct snd_kcontrol *kcontrol,
114
struct snd_ctl_elem_value *ucontrol)
115
{
116
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
117
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
118
struct mt8183_afe_private *afe_priv = afe->platform_priv;
119
120
ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic;
121
122
return 0;
123
}
124
125
static int mt8183_adda_dmic_set(struct snd_kcontrol *kcontrol,
126
struct snd_ctl_elem_value *ucontrol)
127
{
128
struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
129
struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
130
struct mt8183_afe_private *afe_priv = afe->platform_priv;
131
struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
132
133
if (ucontrol->value.enumerated.item[0] >= e->items)
134
return -EINVAL;
135
136
afe_priv->mtkaif_dmic = ucontrol->value.integer.value[0];
137
138
dev_info(afe->dev, "%s(), kcontrol name %s, mtkaif_dmic %d\n",
139
__func__, kcontrol->id.name, afe_priv->mtkaif_dmic);
140
141
return 0;
142
}
143
144
static const struct snd_kcontrol_new mtk_adda_controls[] = {
145
SOC_ENUM_EXT("MTKAIF_DMIC", mt8183_adda_enum[0],
146
mt8183_adda_dmic_get, mt8183_adda_dmic_set),
147
};
148
149
enum {
150
SUPPLY_SEQ_ADDA_AFE_ON,
151
SUPPLY_SEQ_ADDA_DL_ON,
152
SUPPLY_SEQ_ADDA_UL_ON,
153
};
154
155
static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
156
/* adda */
157
SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
158
mtk_adda_dl_ch1_mix,
159
ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
160
SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
161
mtk_adda_dl_ch2_mix,
162
ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
163
164
SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
165
AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0,
166
NULL, 0),
167
168
SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
169
AFE_ADDA_DL_SRC2_CON0,
170
DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
171
NULL, 0),
172
173
SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
174
AFE_ADDA_UL_SRC_CON0,
175
UL_SRC_ON_TMP_CTL_SFT, 0,
176
mtk_adda_ul_event,
177
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
178
179
SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"),
180
SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"),
181
SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"),
182
SND_SOC_DAPM_CLOCK_SUPPLY("mtkaif_26m_clk"),
183
};
184
185
static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
186
/* playback */
187
{"ADDA_DL_CH1", "DL1_CH1", "DL1"},
188
{"ADDA_DL_CH2", "DL1_CH1", "DL1"},
189
{"ADDA_DL_CH2", "DL1_CH2", "DL1"},
190
191
{"ADDA_DL_CH1", "DL2_CH1", "DL2"},
192
{"ADDA_DL_CH2", "DL2_CH1", "DL2"},
193
{"ADDA_DL_CH2", "DL2_CH2", "DL2"},
194
195
{"ADDA_DL_CH1", "DL3_CH1", "DL3"},
196
{"ADDA_DL_CH2", "DL3_CH1", "DL3"},
197
{"ADDA_DL_CH2", "DL3_CH2", "DL3"},
198
199
{"ADDA Playback", NULL, "ADDA_DL_CH1"},
200
{"ADDA Playback", NULL, "ADDA_DL_CH2"},
201
202
/* adda enable */
203
{"ADDA Playback", NULL, "ADDA Enable"},
204
{"ADDA Playback", NULL, "ADDA Playback Enable"},
205
{"ADDA Capture", NULL, "ADDA Enable"},
206
{"ADDA Capture", NULL, "ADDA Capture Enable"},
207
208
/* clk */
209
{"ADDA Playback", NULL, "mtkaif_26m_clk"},
210
{"ADDA Playback", NULL, "aud_dac_clk"},
211
{"ADDA Playback", NULL, "aud_dac_predis_clk"},
212
213
{"ADDA Capture", NULL, "mtkaif_26m_clk"},
214
{"ADDA Capture", NULL, "aud_adc_clk"},
215
};
216
217
static int set_mtkaif_rx(struct mtk_base_afe *afe)
218
{
219
struct mt8183_afe_private *afe_priv = afe->platform_priv;
220
int delay_data;
221
int delay_cycle;
222
223
switch (afe_priv->mtkaif_protocol) {
224
case MT8183_MTKAIF_PROTOCOL_2_CLK_P2:
225
regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x38);
226
regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x39);
227
/* mtkaif_rxif_clkinv_adc inverse for calibration */
228
regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
229
0x80010000);
230
231
if (afe_priv->mtkaif_phase_cycle[0] >=
232
afe_priv->mtkaif_phase_cycle[1]) {
233
delay_data = DELAY_DATA_MISO1;
234
delay_cycle = afe_priv->mtkaif_phase_cycle[0] -
235
afe_priv->mtkaif_phase_cycle[1];
236
} else {
237
delay_data = DELAY_DATA_MISO2;
238
delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
239
afe_priv->mtkaif_phase_cycle[0];
240
}
241
242
regmap_update_bits(afe->regmap,
243
AFE_ADDA_MTKAIF_RX_CFG2,
244
MTKAIF_RXIF_DELAY_DATA_MASK_SFT,
245
delay_data << MTKAIF_RXIF_DELAY_DATA_SFT);
246
247
regmap_update_bits(afe->regmap,
248
AFE_ADDA_MTKAIF_RX_CFG2,
249
MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT,
250
delay_cycle << MTKAIF_RXIF_DELAY_CYCLE_SFT);
251
break;
252
case MT8183_MTKAIF_PROTOCOL_2:
253
regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31);
254
regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
255
0x00010000);
256
break;
257
case MT8183_MTKAIF_PROTOCOL_1:
258
regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31);
259
regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x0);
260
break;
261
default:
262
break;
263
}
264
265
return 0;
266
}
267
268
/* dai ops */
269
static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
270
struct snd_pcm_hw_params *params,
271
struct snd_soc_dai *dai)
272
{
273
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
274
unsigned int rate = params_rate(params);
275
276
dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
277
__func__, dai->id, substream->stream, rate);
278
279
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
280
unsigned int dl_src2_con0 = 0;
281
unsigned int dl_src2_con1 = 0;
282
283
/* clean predistortion */
284
regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0);
285
regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0);
286
287
/* set sampling rate */
288
dl_src2_con0 = mtk_adda_dl_rate_transform(afe, rate) << 28;
289
290
/* set output mode */
291
switch (rate) {
292
case 192000:
293
dl_src2_con0 |= (0x1 << 24); /* UP_SAMPLING_RATE_X2 */
294
dl_src2_con0 |= 1 << 14;
295
break;
296
case 96000:
297
dl_src2_con0 |= (0x2 << 24); /* UP_SAMPLING_RATE_X4 */
298
dl_src2_con0 |= 1 << 14;
299
break;
300
default:
301
dl_src2_con0 |= (0x3 << 24); /* UP_SAMPLING_RATE_X8 */
302
break;
303
}
304
305
/* turn off mute function */
306
dl_src2_con0 |= (0x03 << 11);
307
308
/* set voice input data if input sample rate is 8k or 16k */
309
if (rate == 8000 || rate == 16000)
310
dl_src2_con0 |= 0x01 << 5;
311
312
/* SA suggest apply -0.3db to audio/speech path */
313
dl_src2_con1 = 0xf74f0000;
314
315
/* turn on down-link gain */
316
dl_src2_con0 = dl_src2_con0 | (0x01 << 1);
317
318
regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON0, dl_src2_con0);
319
regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON1, dl_src2_con1);
320
321
/* set sdm gain */
322
regmap_update_bits(afe->regmap,
323
AFE_ADDA_DL_SDM_DCCOMP_CON,
324
ATTGAIN_CTL_MASK_SFT,
325
AUDIO_SDM_LEVEL_NORMAL << ATTGAIN_CTL_SFT);
326
} else {
327
unsigned int voice_mode = 0;
328
unsigned int ul_src_con0 = 0; /* default value */
329
330
/* set mtkaif protocol */
331
set_mtkaif_rx(afe);
332
333
/* Using Internal ADC */
334
regmap_update_bits(afe->regmap,
335
AFE_ADDA_TOP_CON0,
336
0x1 << 0,
337
0x0 << 0);
338
339
voice_mode = mtk_adda_ul_rate_transform(afe, rate);
340
341
ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);
342
343
/* enable iir */
344
ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) &
345
UL_IIR_ON_TMP_CTL_MASK_SFT;
346
347
/* 35Hz @ 48k */
348
regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_02_01, 0x00000000);
349
regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_04_03, 0x00003FB8);
350
regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_06_05, 0x3FB80000);
351
regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_08_07, 0x3FB80000);
352
regmap_write(afe->regmap, AFE_ADDA_IIR_COEF_10_09, 0x0000C048);
353
354
regmap_write(afe->regmap, AFE_ADDA_UL_SRC_CON0, ul_src_con0);
355
356
/* mtkaif_rxif_data_mode = 0, amic */
357
regmap_update_bits(afe->regmap,
358
AFE_ADDA_MTKAIF_RX_CFG0,
359
0x1 << 0,
360
0x0 << 0);
361
}
362
363
return 0;
364
}
365
366
static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
367
.hw_params = mtk_dai_adda_hw_params,
368
};
369
370
/* dai driver */
371
#define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
372
SNDRV_PCM_RATE_96000 |\
373
SNDRV_PCM_RATE_192000)
374
375
#define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
376
SNDRV_PCM_RATE_16000 |\
377
SNDRV_PCM_RATE_32000 |\
378
SNDRV_PCM_RATE_48000)
379
380
#define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
381
SNDRV_PCM_FMTBIT_S24_LE |\
382
SNDRV_PCM_FMTBIT_S32_LE)
383
384
static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
385
{
386
.name = "ADDA",
387
.id = MT8183_DAI_ADDA,
388
.playback = {
389
.stream_name = "ADDA Playback",
390
.channels_min = 1,
391
.channels_max = 2,
392
.rates = MTK_ADDA_PLAYBACK_RATES,
393
.formats = MTK_ADDA_FORMATS,
394
},
395
.capture = {
396
.stream_name = "ADDA Capture",
397
.channels_min = 1,
398
.channels_max = 2,
399
.rates = MTK_ADDA_CAPTURE_RATES,
400
.formats = MTK_ADDA_FORMATS,
401
},
402
.ops = &mtk_dai_adda_ops,
403
},
404
};
405
406
int mt8183_dai_adda_register(struct mtk_base_afe *afe)
407
{
408
struct mtk_base_afe_dai *dai;
409
410
dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
411
if (!dai)
412
return -ENOMEM;
413
414
list_add(&dai->list, &afe->sub_dais);
415
416
dai->dai_drivers = mtk_dai_adda_driver;
417
dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
418
419
dai->controls = mtk_adda_controls;
420
dai->num_controls = ARRAY_SIZE(mtk_adda_controls);
421
dai->dapm_widgets = mtk_dai_adda_widgets;
422
dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
423
dai->dapm_routes = mtk_dai_adda_routes;
424
dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
425
return 0;
426
}
427
428