CoCalc -- mt8186-reg.h

GitHub Repository: torvalds/linux
Path: blob/master/sound/soc/mediatek/mt8186/mt8186-reg.h
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/* SPDX-License-Identifier: GPL-2.0
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 *
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 * mt8186-reg.h  --  Mediatek 8186 audio driver reg definition
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 *
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 * Copyright (c) 2022 MediaTek Inc.
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 * Author: Jiaxin Yu <[email protected]>
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 */
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#ifndef _MT8186_REG_H_
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#define _MT8186_REG_H_
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/* reg bit enum */
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enum {
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	MT8186_MEMIF_PBUF_SIZE_32_BYTES,
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	MT8186_MEMIF_PBUF_SIZE_64_BYTES,
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	MT8186_MEMIF_PBUF_SIZE_128_BYTES,
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	MT8186_MEMIF_PBUF_SIZE_256_BYTES,
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	MT8186_MEMIF_PBUF_SIZE_NUM,
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};
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/*****************************************************************************
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 *                  R E G I S T E R       D E F I N I T I O N
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 *****************************************************************************/
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/* AUDIO_TOP_CON0 */
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#define RESERVED_SFT					31
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#define RESERVED_MASK_SFT				BIT(31)
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#define AHB_IDLE_EN_INT_SFT				30
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#define AHB_IDLE_EN_INT_MASK_SFT			BIT(30)
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#define AHB_IDLE_EN_EXT_SFT				29
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#define AHB_IDLE_EN_EXT_MASK_SFT			BIT(29)
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#define PDN_NLE_SFT					28
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#define PDN_NLE_MASK_SFT				BIT(28)
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#define PDN_TML_SFT					27
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#define PDN_TML_MASK_SFT				BIT(27)
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#define PDN_DAC_PREDIS_SFT				26
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#define PDN_DAC_PREDIS_MASK_SFT				BIT(26)
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#define PDN_DAC_SFT					25
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#define PDN_DAC_MASK_SFT				BIT(25)
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#define PDN_ADC_SFT					24
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#define PDN_ADC_MASK_SFT				BIT(24)
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#define PDN_TDM_CK_SFT					20
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#define PDN_TDM_CK_MASK_SFT				BIT(20)
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#define PDN_APLL_TUNER_SFT				19
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#define PDN_APLL_TUNER_MASK_SFT				BIT(19)
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#define PDN_APLL2_TUNER_SFT				18
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#define PDN_APLL2_TUNER_MASK_SFT			BIT(18)
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#define APB3_SEL_SFT					14
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#define APB3_SEL_MASK_SFT				BIT(14)
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#define APB_R2T_SFT					13
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#define APB_R2T_MASK_SFT				BIT(13)
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#define APB_W2T_SFT					12
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#define APB_W2T_MASK_SFT				BIT(12)
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#define PDN_24M_SFT					9
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#define PDN_24M_MASK_SFT				BIT(9)
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#define PDN_22M_SFT					8
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#define PDN_22M_MASK_SFT				BIT(8)
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#define PDN_AFE_SFT					2
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#define PDN_AFE_MASK_SFT				BIT(2)
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/* AUDIO_TOP_CON1 */
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#define PDN_3RD_DAC_HIRES_SFT				31
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#define PDN_3RD_DAC_HIRES_MASK_SFT			BIT(31)
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#define PDN_3RD_DAC_TML_SFT				30
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#define PDN_3RD_DAC_TML_MASK_SFT			BIT(30)
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#define PDN_3RD_DAC_PREDIS_SFT				29
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#define PDN_3RD_DAC_PREDIS_MASK_SFT			BIT(29)
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#define PDN_3RD_DAC_SFT					28
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#define PDN_3RD_DAC_MASK_SFT				BIT(28)
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#define I2S_SOFT_RST5_SFT				22
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#define I2S_SOFT_RST5_MASK_SFT				BIT(22)
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#define PDN_ADDA6_ADC_HIRES_SFT				21
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#define PDN_ADDA6_ADC_HIRES_MASK_SFT			BIT(21)
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#define PDN_ADDA6_ADC_SFT				20
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#define PDN_ADDA6_ADC_MASK_SFT				BIT(20)
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#define PDN_ADC_HIRES_TML_SFT				17
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#define PDN_ADC_HIRES_TML_MASK_SFT			BIT(17)
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#define PDN_ADC_HIRES_SFT				16
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#define PDN_ADC_HIRES_MASK_SFT				BIT(16)
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#define PDN_DAC_HIRES_SFT				15
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#define PDN_DAC_HIRES_MASK_SFT				BIT(15)
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#define PDN_GENERAL2_ASRC_SFT				14
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#define PDN_GENERAL2_ASRC_MASK_SFT			BIT(14)
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#define PDN_GENERAL1_ASRC_SFT				13
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#define PDN_GENERAL1_ASRC_MASK_SFT			BIT(13)
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#define PDN_CONNSYS_I2S_ASRC_SFT			12
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#define PDN_CONNSYS_I2S_ASRC_MASK_SFT			BIT(12)
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#define I2S4_BCLK_SW_CG_SFT				7
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#define I2S4_BCLK_SW_CG_MASK_SFT			BIT(7)
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#define I2S3_BCLK_SW_CG_SFT				6
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#define I2S3_BCLK_SW_CG_MASK_SFT			BIT(6)
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#define I2S2_BCLK_SW_CG_SFT				5
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#define I2S2_BCLK_SW_CG_MASK_SFT			BIT(5)
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#define I2S1_BCLK_SW_CG_SFT				4
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#define I2S1_BCLK_SW_CG_MASK_SFT			BIT(4)
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#define I2S_SOFT_RST2_SFT				2
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#define I2S_SOFT_RST2_MASK_SFT				BIT(2)
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#define I2S_SOFT_RST_SFT				1
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#define I2S_SOFT_RST_MASK_SFT				BIT(1)
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/* AUDIO_TOP_CON3 */
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#define BUSY_SFT					31
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#define BUSY_MASK_SFT					BIT(31)
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#define OS_DISABLE_SFT					30
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#define OS_DISABLE_MASK_SFT				BIT(30)
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#define CG_DISABLE_SFT					29
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#define CG_DISABLE_MASK_SFT				BIT(29)
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#define CLEAR_FLAG_SFT					0
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#define CLEAR_FLAG_MASK_SFT				BIT(0)
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/* AFE_DAC_CON0 */
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#define VUL12_ON_SFT					31
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#define VUL12_ON_MASK_SFT				BIT(31)
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#define MOD_DAI_ON_SFT					30
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#define MOD_DAI_ON_MASK_SFT				BIT(30)
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#define DAI_ON_SFT					29
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#define DAI_ON_MASK_SFT					BIT(29)
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#define DAI2_ON_SFT					28
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#define DAI2_ON_MASK_SFT				BIT(28)
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#define VUL6_ON_SFT					23
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#define VUL6_ON_MASK_SFT				BIT(23)
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#define VUL5_ON_SFT					22
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#define VUL5_ON_MASK_SFT				BIT(22)
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#define VUL4_ON_SFT					21
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#define VUL4_ON_MASK_SFT				BIT(21)
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#define VUL3_ON_SFT					20
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#define VUL3_ON_MASK_SFT				BIT(20)
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#define VUL2_ON_SFT					19
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#define VUL2_ON_MASK_SFT				BIT(19)
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#define VUL_ON_SFT					18
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#define VUL_ON_MASK_SFT					BIT(18)
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#define AWB2_ON_SFT					17
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#define AWB2_ON_MASK_SFT				BIT(17)
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#define AWB_ON_SFT					16
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#define AWB_ON_MASK_SFT					BIT(16)
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#define DL12_ON_SFT					15
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#define DL12_ON_MASK_SFT				BIT(15)
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#define DL8_ON_SFT					11
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#define DL8_ON_MASK_SFT					BIT(11)
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#define DL7_ON_SFT					10
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#define DL7_ON_MASK_SFT					BIT(10)
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#define DL6_ON_SFT					9
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#define DL6_ON_MASK_SFT					BIT(9)
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#define DL5_ON_SFT					8
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#define DL5_ON_MASK_SFT					BIT(8)
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#define DL4_ON_SFT					7
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#define DL4_ON_MASK_SFT					BIT(7)
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#define DL3_ON_SFT					6
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#define DL3_ON_MASK_SFT					BIT(6)
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#define DL2_ON_SFT					5
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#define DL2_ON_MASK_SFT					BIT(5)
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#define DL1_ON_SFT					4
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#define DL1_ON_MASK_SFT					BIT(4)
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#define AUDIO_AFE_ON_SFT				0
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#define AUDIO_AFE_ON_MASK_SFT				BIT(0)
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/* AFE_DAC_MON */
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#define AFE_ON_RETM_SFT					0
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#define AFE_ON_RETM_MASK_SFT				BIT(0)
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/* AFE_I2S_CON */
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#define BCK_NEG_EG_LATCH_SFT				30
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#define BCK_NEG_EG_LATCH_MASK_SFT			BIT(30)
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#define BCK_INV_SFT					29
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#define BCK_INV_MASK_SFT				BIT(29)
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#define I2SIN_PAD_SEL_SFT				28
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#define I2SIN_PAD_SEL_MASK_SFT				BIT(28)
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#define I2S_LOOPBACK_SFT				20
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#define I2S_LOOPBACK_MASK_SFT				BIT(20)
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#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT		17
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#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT		BIT(17)
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#define I2S1_HD_EN_SFT					12
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#define I2S1_HD_EN_MASK_SFT				BIT(12)
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#define I2S_OUT_MODE_SFT				8
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#define I2S_OUT_MODE_MASK_SFT				GENMASK(11, 8)
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#define INV_PAD_CTRL_SFT				7
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#define INV_PAD_CTRL_MASK_SFT				BIT(7)
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#define I2S_BYPSRC_SFT					6
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#define I2S_BYPSRC_MASK_SFT				BIT(6)
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#define INV_LRCK_SFT					5
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#define INV_LRCK_MASK_SFT				BIT(5)
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#define I2S_FMT_SFT					3
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#define I2S_FMT_MASK_SFT				BIT(3)
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#define I2S_SRC_SFT					2
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#define I2S_SRC_MASK_SFT				BIT(2)
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#define I2S_WLEN_SFT					1
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#define I2S_WLEN_MASK_SFT				BIT(1)
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#define I2S_EN_SFT					0
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#define I2S_EN_MASK_SFT					BIT(0)
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/* AFE_I2S_CON1 */
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#define I2S2_LR_SWAP_SFT				31
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#define I2S2_LR_SWAP_MASK_SFT				BIT(31)
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#define I2S2_SEL_O19_O20_SFT				18
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#define I2S2_SEL_O19_O20_MASK_SFT			BIT(18)
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#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT		17
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#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT		BIT(17)
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#define I2S2_SEL_O03_O04_SFT				16
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#define I2S2_SEL_O03_O04_MASK_SFT			BIT(16)
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#define I2S2_HD_EN_SFT					12
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#define I2S2_HD_EN_MASK_SFT				BIT(12)
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#define I2S2_OUT_MODE_SFT				8
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#define I2S2_OUT_MODE_MASK_SFT				GENMASK(11, 8)
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#define INV_LRCK_SFT					5
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#define INV_LRCK_MASK_SFT				BIT(5)
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#define I2S2_FMT_SFT					3
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#define I2S2_FMT_MASK_SFT				BIT(3)
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#define I2S2_WLEN_SFT					1
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#define I2S2_WLEN_MASK_SFT				BIT(1)
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#define I2S2_EN_SFT					0
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#define I2S2_EN_MASK_SFT				BIT(0)
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/* AFE_I2S_CON2 */
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#define I2S3_LR_SWAP_SFT				31
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#define I2S3_LR_SWAP_MASK_SFT				BIT(31)
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#define I2S3_UPDATE_WORD_SFT				24
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#define I2S3_UPDATE_WORD_MASK_SFT			GENMASK(28, 24)
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#define I2S3_BCK_INV_SFT				23
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#define I2S3_BCK_INV_MASK_SFT				BIT(23)
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#define I2S3_FPGA_BIT_TEST_SFT				22
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#define I2S3_FPGA_BIT_TEST_MASK_SFT			BIT(22)
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#define I2S3_FPGA_BIT_SFT				21
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#define I2S3_FPGA_BIT_MASK_SFT				BIT(21)
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#define I2S3_LOOPBACK_SFT				20
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#define I2S3_LOOPBACK_MASK_SFT				BIT(20)
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#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT		17
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#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT		BIT(17)
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#define I2S3_HD_EN_SFT					12
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#define I2S3_HD_EN_MASK_SFT				BIT(12)
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#define I2S3_OUT_MODE_SFT				8
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#define I2S3_OUT_MODE_MASK_SFT				GENMASK(11, 8)
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#define I2S3_FMT_SFT					3
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#define I2S3_FMT_MASK_SFT				BIT(3)
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#define I2S3_WLEN_SFT					1
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#define I2S3_WLEN_MASK_SFT				BIT(1)
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#define I2S3_EN_SFT					0
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#define I2S3_EN_MASK_SFT				BIT(0)
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/* AFE_I2S_CON3 */
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#define I2S4_LR_SWAP_SFT				31
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#define I2S4_LR_SWAP_MASK_SFT				BIT(31)
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#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT		17
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#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT		BIT(17)
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#define I2S4_HD_EN_SFT					12
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#define I2S4_HD_EN_MASK_SFT				BIT(12)
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#define I2S4_OUT_MODE_SFT				8
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#define I2S4_OUT_MODE_MASK_SFT				GENMASK(11, 8)
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#define INV_LRCK_SFT					5
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#define INV_LRCK_MASK_SFT				BIT(5)
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#define I2S4_FMT_SFT					3
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#define I2S4_FMT_MASK_SFT				BIT(3)
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#define I2S4_WLEN_SFT					1
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#define I2S4_WLEN_MASK_SFT				BIT(1)
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#define I2S4_EN_SFT					0
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#define I2S4_EN_MASK_SFT				BIT(0)
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/* AFE_I2S_CON4 */
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#define I2S_LOOPBACK_SFT				20
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#define I2S_LOOPBACK_MASK				0x1
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#define I2S_LOOPBACK_MASK_SFT				BIT(20)
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#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT		17
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#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK		0x1
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#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT		BIT(17)
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#define INV_LRCK_SFT					5
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#define INV_LRCK_MASK					0x1
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#define INV_LRCK_MASK_SFT				BIT(5)
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/* AFE_CONNSYS_I2S_CON */
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#define BCK_NEG_EG_LATCH_SFT				30
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#define BCK_NEG_EG_LATCH_MASK_SFT			BIT(30)
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#define BCK_INV_SFT					29
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#define BCK_INV_MASK_SFT				BIT(29)
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#define I2SIN_PAD_SEL_SFT				28
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#define I2SIN_PAD_SEL_MASK_SFT				BIT(28)
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#define I2S_LOOPBACK_SFT				20
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#define I2S_LOOPBACK_MASK_SFT				BIT(20)
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#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT		17
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#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT		BIT(17)
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#define I2S_MODE_SFT					8
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#define I2S_MODE_MASK_SFT				GENMASK(11, 8)
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#define INV_PAD_CTRL_SFT				7
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#define INV_PAD_CTRL_MASK_SFT				BIT(7)
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#define I2S_BYPSRC_SFT					6
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#define I2S_BYPSRC_MASK_SFT				BIT(6)
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#define INV_LRCK_SFT					5
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#define INV_LRCK_MASK_SFT				BIT(5)
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#define I2S_FMT_SFT					3
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#define I2S_FMT_MASK_SFT				BIT(3)
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#define I2S_SRC_SFT					2
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#define I2S_SRC_MASK_SFT				BIT(2)
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#define I2S_WLEN_SFT					1
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#define I2S_WLEN_MASK_SFT				BIT(1)
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#define I2S_EN_SFT					0
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#define I2S_EN_MASK_SFT					BIT(0)
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/* AFE_ASRC_2CH_CON2 */
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#define CHSET_O16BIT_SFT				19
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#define CHSET_O16BIT_MASK_SFT				BIT(19)
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#define CHSET_CLR_IIR_HISTORY_SFT			17
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#define CHSET_CLR_IIR_HISTORY_MASK_SFT			BIT(17)
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#define CHSET_IS_MONO_SFT				16
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#define CHSET_IS_MONO_MASK_SFT				BIT(16)
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#define CHSET_IIR_EN_SFT				11
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#define CHSET_IIR_EN_MASK_SFT				BIT(11)
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#define CHSET_IIR_STAGE_SFT				8
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#define CHSET_IIR_STAGE_MASK_SFT			GENMASK(10, 8)
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#define CHSET_STR_CLR_SFT				5
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#define CHSET_STR_CLR_MASK_SFT				BIT(5)
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#define CHSET_ON_SFT					2
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#define CHSET_ON_MASK_SFT				BIT(2)
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#define COEFF_SRAM_CTRL_SFT				1
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#define COEFF_SRAM_CTRL_MASK_SFT			BIT(1)
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#define ASM_ON_SFT					0
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#define ASM_ON_MASK_SFT					BIT(0)
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/* AFE_GAIN1_CON0 */
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#define GAIN1_SAMPLE_PER_STEP_SFT			8
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#define GAIN1_SAMPLE_PER_STEP_MASK_SFT			GENMASK(15, 8)
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#define GAIN1_MODE_SFT					4
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#define GAIN1_MODE_MASK_SFT				GENMASK(7, 4)
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#define GAIN1_ON_SFT					0
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#define GAIN1_ON_MASK_SFT				BIT(0)
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/* AFE_GAIN1_CON1 */
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#define GAIN1_TARGET_SFT				0
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#define GAIN1_TARGET_MASK				0xfffffff
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#define GAIN1_TARGET_MASK_SFT				GENMASK(27, 0)
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/* AFE_GAIN2_CON0 */
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#define GAIN2_SAMPLE_PER_STEP_SFT			8
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#define GAIN2_SAMPLE_PER_STEP_MASK_SFT			GENMASK(15, 8)
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#define GAIN2_MODE_SFT					4
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#define GAIN2_MODE_MASK_SFT				GENMASK(7, 4)
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#define GAIN2_ON_SFT					0
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#define GAIN2_ON_MASK_SFT				BIT(0)
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/* AFE_GAIN2_CON1 */
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#define GAIN2_TARGET_SFT				0
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#define GAIN2_TARGET_MASK				0xfffffff
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#define GAIN2_TARGET_MASK_SFT				GENMASK(27, 0)
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/* AFE_GAIN1_CUR */
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#define AFE_GAIN1_CUR_SFT				0
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#define AFE_GAIN1_CUR_MASK_SFT				GENMASK(27, 0)
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/* AFE_GAIN2_CUR */
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#define AFE_GAIN2_CUR_SFT				0
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#define AFE_GAIN2_CUR_MASK_SFT				GENMASK(27, 0)
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/* PCM_INTF_CON1 */
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#define PCM_FIX_VALUE_SEL_SFT				31
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#define PCM_FIX_VALUE_SEL_MASK_SFT			BIT(31)
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#define PCM_BUFFER_LOOPBACK_SFT				30
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#define PCM_BUFFER_LOOPBACK_MASK_SFT			BIT(30)
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#define PCM_PARALLEL_LOOPBACK_SFT			29
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#define PCM_PARALLEL_LOOPBACK_MASK_SFT			BIT(29)
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#define PCM_SERIAL_LOOPBACK_SFT				28
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#define PCM_SERIAL_LOOPBACK_MASK_SFT			BIT(28)
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#define PCM_DAI_PCM_LOOPBACK_SFT			27
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#define PCM_DAI_PCM_LOOPBACK_MASK_SFT			BIT(27)
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#define PCM_I2S_PCM_LOOPBACK_SFT			26
361
#define PCM_I2S_PCM_LOOPBACK_MASK_SFT			BIT(26)
362
#define PCM_SYNC_DELSEL_SFT				25
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#define PCM_SYNC_DELSEL_MASK_SFT			BIT(25)
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#define PCM_TX_LR_SWAP_SFT				24
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#define PCM_TX_LR_SWAP_MASK_SFT				BIT(24)
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#define PCM_SYNC_OUT_INV_SFT				23
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#define PCM_SYNC_OUT_INV_MASK_SFT			BIT(23)
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#define PCM_BCLK_OUT_INV_SFT				22
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#define PCM_BCLK_OUT_INV_MASK_SFT			BIT(22)
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#define PCM_SYNC_IN_INV_SFT				21
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#define PCM_SYNC_IN_INV_MASK_SFT			BIT(21)
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#define PCM_BCLK_IN_INV_SFT				20
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#define PCM_BCLK_IN_INV_MASK_SFT			BIT(20)
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#define PCM_TX_LCH_RPT_SFT				19
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#define PCM_TX_LCH_RPT_MASK_SFT				BIT(19)
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#define PCM_VBT_16K_MODE_SFT				18
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#define PCM_VBT_16K_MODE_MASK_SFT			BIT(18)
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#define PCM_EXT_MODEM_SFT				17
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#define PCM_EXT_MODEM_MASK_SFT				BIT(17)
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#define PCM_24BIT_SFT					16
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#define PCM_24BIT_MASK_SFT				BIT(16)
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#define PCM_WLEN_SFT					14
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#define PCM_WLEN_MASK_SFT				GENMASK(15, 14)
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#define PCM_SYNC_LENGTH_SFT				9
385
#define PCM_SYNC_LENGTH_MASK_SFT			GENMASK(13, 9)
386
#define PCM_SYNC_TYPE_SFT				8
387
#define PCM_SYNC_TYPE_MASK_SFT				BIT(8)
388
#define PCM_BT_MODE_SFT					7
389
#define PCM_BT_MODE_MASK_SFT				BIT(7)
390
#define PCM_BYP_ASRC_SFT				6
391
#define PCM_BYP_ASRC_MASK_SFT				BIT(6)
392
#define PCM_SLAVE_SFT					5
393
#define PCM_SLAVE_MASK_SFT				BIT(5)
394
#define PCM_MODE_SFT					3
395
#define PCM_MODE_MASK_SFT				GENMASK(4, 3)
396
#define PCM_FMT_SFT					1
397
#define PCM_FMT_MASK_SFT				GENMASK(2, 1)
398
#define PCM_EN_SFT					0
399
#define PCM_EN_MASK_SFT					BIT(0)
400

401
/* PCM_INTF_CON2 */
402
#define PCM1_TX_FIFO_OV_SFT				31
403
#define PCM1_TX_FIFO_OV_MASK_SFT			BIT(31)
404
#define PCM1_RX_FIFO_OV_SFT				30
405
#define PCM1_RX_FIFO_OV_MASK_SFT			BIT(30)
406
#define PCM2_TX_FIFO_OV_SFT				29
407
#define PCM2_TX_FIFO_OV_MASK_SFT			BIT(29)
408
#define PCM2_RX_FIFO_OV_SFT				28
409
#define PCM2_RX_FIFO_OV_MASK_SFT			BIT(28)
410
#define PCM1_SYNC_GLITCH_SFT				27
411
#define PCM1_SYNC_GLITCH_MASK_SFT			BIT(27)
412
#define PCM2_SYNC_GLITCH_SFT				26
413
#define PCM2_SYNC_GLITCH_MASK_SFT			BIT(26)
414
#define TX3_RCH_DBG_MODE_SFT				17
415
#define TX3_RCH_DBG_MODE_MASK_SFT			BIT(17)
416
#define PCM1_PCM2_LOOPBACK_SFT				16
417
#define PCM1_PCM2_LOOPBACK_MASK_SFT			BIT(16)
418
#define DAI_PCM_LOOPBACK_CH_SFT				14
419
#define DAI_PCM_LOOPBACK_CH_MASK_SFT			GENMASK(15, 14)
420
#define I2S_PCM_LOOPBACK_CH_SFT				12
421
#define I2S_PCM_LOOPBACK_CH_MASK_SFT			GENMASK(13, 12)
422
#define TX_FIX_VALUE_SFT				0
423
#define TX_FIX_VALUE_MASK_SFT				GENMASK(7, 0)
424

425
/* PCM2_INTF_CON */
426
#define PCM2_TX_FIX_VALUE_SFT				24
427
#define PCM2_TX_FIX_VALUE_MASK_SFT			GENMASK(31, 24)
428
#define PCM2_FIX_VALUE_SEL_SFT				23
429
#define PCM2_FIX_VALUE_SEL_MASK_SFT			BIT(23)
430
#define PCM2_BUFFER_LOOPBACK_SFT			22
431
#define PCM2_BUFFER_LOOPBACK_MASK_SFT			BIT(22)
432
#define PCM2_PARALLEL_LOOPBACK_SFT			21
433
#define PCM2_PARALLEL_LOOPBACK_MASK_SFT			BIT(21)
434
#define PCM2_SERIAL_LOOPBACK_SFT			20
435
#define PCM2_SERIAL_LOOPBACK_MASK_SFT			BIT(20)
436
#define PCM2_DAI_PCM_LOOPBACK_SFT			19
437
#define PCM2_DAI_PCM_LOOPBACK_MASK_SFT			BIT(19)
438
#define PCM2_I2S_PCM_LOOPBACK_SFT			18
439
#define PCM2_I2S_PCM_LOOPBACK_MASK_SFT			BIT(18)
440
#define PCM2_SYNC_DELSEL_SFT				17
441
#define PCM2_SYNC_DELSEL_MASK_SFT			BIT(17)
442
#define PCM2_TX_LR_SWAP_SFT				16
443
#define PCM2_TX_LR_SWAP_MASK_SFT			BIT(16)
444
#define PCM2_SYNC_IN_INV_SFT				15
445
#define PCM2_SYNC_IN_INV_MASK_SFT			BIT(15)
446
#define PCM2_BCLK_IN_INV_SFT				14
447
#define PCM2_BCLK_IN_INV_MASK_SFT			BIT(14)
448
#define PCM2_TX_LCH_RPT_SFT				13
449
#define PCM2_TX_LCH_RPT_MASK_SFT			BIT(13)
450
#define PCM2_VBT_16K_MODE_SFT				12
451
#define PCM2_VBT_16K_MODE_MASK_SFT			BIT(12)
452
#define PCM2_LOOPBACK_CH_SEL_SFT			10
453
#define PCM2_LOOPBACK_CH_SEL_MASK_SFT			GENMASK(11, 10)
454
#define PCM2_TX2_BT_MODE_SFT				8
455
#define PCM2_TX2_BT_MODE_MASK_SFT			BIT(8)
456
#define PCM2_BT_MODE_SFT				7
457
#define PCM2_BT_MODE_MASK_SFT				BIT(7)
458
#define PCM2_AFIFO_SFT					6
459
#define PCM2_AFIFO_MASK_SFT				BIT(6)
460
#define PCM2_WLEN_SFT					5
461
#define PCM2_WLEN_MASK_SFT				BIT(5)
462
#define PCM2_MODE_SFT					3
463
#define PCM2_MODE_MASK_SFT				GENMASK(4, 3)
464
#define PCM2_FMT_SFT					1
465
#define PCM2_FMT_MASK_SFT				GENMASK(2, 1)
466
#define PCM2_EN_SFT					0
467
#define PCM2_EN_MASK_SFT				BIT(0)
468

469
// AFE_CM1_CON
470
#define CHANNEL_MERGE0_DEBUG_MODE_SFT			(31)
471
#define CHANNEL_MERGE0_DEBUG_MODE_MASK_SFT		BIT(31)
472
#define VUL3_BYPASS_CM_SFT				(30)
473
#define VUL3_BYPASS_CM_MASK				(0x1)
474
#define VUL3_BYPASS_CM_MASK_SFT				BIT(30)
475
#define CM1_DEBUG_MODE_SEL_SFT				(29)
476
#define CM1_DEBUG_MODE_SEL_MASK_SFT			BIT(29)
477
#define CHANNEL_MERGE0_UPDATE_CNT_SFT			(16)
478
#define CHANNEL_MERGE0_UPDATE_CNT_MASK_SFT		GENMASK(28, 16)
479
#define CM1_FS_SELECT_SFT				(8)
480
#define CM1_FS_SELECT_MASK_SFT				GENMASK(12, 8)
481
#define CHANNEL_MERGE0_CHNUM_SFT			(3)
482
#define CHANNEL_MERGE0_CHNUM_MASK_SFT			GENMASK(7, 3)
483
#define CHANNEL_MERGE0_BYTE_SWAP_SFT			(1)
484
#define CHANNEL_MERGE0_BYTE_SWAP_MASK_SFT		BIT(1)
485
#define CHANNEL_MERGE0_EN_SFT				(0)
486
#define CHANNEL_MERGE0_EN_MASK_SFT			BIT(0)
487

488
/* AFE_ADDA_MTKAIF_CFG0 */
489
#define MTKAIF_RXIF_CLKINV_ADC_SFT			31
490
#define MTKAIF_RXIF_CLKINV_ADC_MASK_SFT			BIT(31)
491
#define MTKAIF_RXIF_BYPASS_SRC_SFT			17
492
#define MTKAIF_RXIF_BYPASS_SRC_MASK_SFT			BIT(17)
493
#define MTKAIF_RXIF_PROTOCOL2_SFT			16
494
#define MTKAIF_RXIF_PROTOCOL2_MASK_SFT			BIT(16)
495
#define MTKAIF_TXIF_BYPASS_SRC_SFT			5
496
#define MTKAIF_TXIF_BYPASS_SRC_MASK_SFT			BIT(5)
497
#define MTKAIF_TXIF_PROTOCOL2_SFT			4
498
#define MTKAIF_TXIF_PROTOCOL2_MASK_SFT			BIT(4)
499
#define MTKAIF_TXIF_8TO5_SFT				2
500
#define MTKAIF_TXIF_8TO5_MASK_SFT			BIT(2)
501
#define MTKAIF_RXIF_8TO5_SFT				1
502
#define MTKAIF_RXIF_8TO5_MASK_SFT			BIT(1)
503
#define MTKAIF_IF_LOOPBACK1_SFT				0
504
#define MTKAIF_IF_LOOPBACK1_MASK_SFT			BIT(0)
505

506
/* AFE_ADDA_MTKAIF_RX_CFG2 */
507
#define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT		16
508
#define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT	BIT(16)
509
#define MTKAIF_RXIF_DELAY_CYCLE_SFT			12
510
#define MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT		GENMASK(15, 12)
511
#define MTKAIF_RXIF_DELAY_DATA_SFT			8
512
#define MTKAIF_RXIF_DELAY_DATA_MASK			0x1
513
#define MTKAIF_RXIF_DELAY_DATA_MASK_SFT			BIT(8)
514
#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SFT		4
515
#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT		GENMASK(6, 4)
516

517
/* AFE_ADDA_DL_SRC2_CON0 */
518
#define DL_2_INPUT_MODE_CTL_SFT				28
519
#define DL_2_INPUT_MODE_CTL_MASK_SFT			GENMASK(31, 28)
520
#define DL_2_CH1_SATURATION_EN_CTL_SFT			27
521
#define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT		BIT(27)
522
#define DL_2_CH2_SATURATION_EN_CTL_SFT			26
523
#define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT		BIT(26)
524
#define DL_2_OUTPUT_SEL_CTL_SFT				24
525
#define DL_2_OUTPUT_SEL_CTL_MASK_SFT			GENMASK(25, 24)
526
#define DL_2_FADEIN_0START_EN_SFT			16
527
#define DL_2_FADEIN_0START_EN_MASK_SFT			GENMASK(17, 16)
528
#define DL_DISABLE_HW_CG_CTL_SFT			15
529
#define DL_DISABLE_HW_CG_CTL_MASK_SFT			BIT(15)
530
#define C_DATA_EN_SEL_CTL_PRE_SFT			14
531
#define C_DATA_EN_SEL_CTL_PRE_MASK_SFT			BIT(14)
532
#define DL_2_SIDE_TONE_ON_CTL_PRE_SFT			13
533
#define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT		BIT(13)
534
#define DL_2_MUTE_CH1_OFF_CTL_PRE_SFT			12
535
#define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT		BIT(12)
536
#define DL_2_MUTE_CH2_OFF_CTL_PRE_SFT			11
537
#define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT		BIT(11)
538
#define DL2_ARAMPSP_CTL_PRE_SFT				9
539
#define DL2_ARAMPSP_CTL_PRE_MASK_SFT			GENMASK(10, 9)
540
#define DL_2_IIRMODE_CTL_PRE_SFT			6
541
#define DL_2_IIRMODE_CTL_PRE_MASK_SFT			GENMASK(8, 6)
542
#define DL_2_VOICE_MODE_CTL_PRE_SFT			5
543
#define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT		BIT(5)
544
#define D2_2_MUTE_CH1_ON_CTL_PRE_SFT			4
545
#define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT		BIT(4)
546
#define D2_2_MUTE_CH2_ON_CTL_PRE_SFT			3
547
#define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT		BIT(3)
548
#define DL_2_IIR_ON_CTL_PRE_SFT				2
549
#define DL_2_IIR_ON_CTL_PRE_MASK_SFT			BIT(2)
550
#define DL_2_GAIN_ON_CTL_PRE_SFT			1
551
#define DL_2_GAIN_ON_CTL_PRE_MASK_SFT			BIT(1)
552
#define DL_2_SRC_ON_CTL_PRE_SFT				0
553
#define DL_2_SRC_ON_CTL_PRE_MASK_SFT			BIT(0)
554

555
/* AFE_ADDA_DL_SRC2_CON1 */
556
#define DL_2_GAIN_CTL_PRE_SFT				16
557
#define DL_2_GAIN_CTL_PRE_MASK				0xffff
558
#define DL_2_GAIN_CTL_PRE_MASK_SFT			GENMASK(31, 16)
559
#define DL_2_GAIN_MODE_CTL_SFT				0
560
#define DL_2_GAIN_MODE_CTL_MASK_SFT			BIT(0)
561

562
/* AFE_ADDA_UL_SRC_CON0 */
563
#define ULCF_CFG_EN_CTL_SFT				31
564
#define ULCF_CFG_EN_CTL_MASK_SFT			BIT(31)
565
#define UL_DMIC_PHASE_SEL_CH1_SFT			27
566
#define UL_DMIC_PHASE_SEL_CH1_MASK_SFT			GENMASK(29, 27)
567
#define UL_DMIC_PHASE_SEL_CH2_SFT			24
568
#define UL_DMIC_PHASE_SEL_CH2_MASK_SFT			GENMASK(26, 24)
569
#define UL_MODE_3P25M_CH2_CTL_SFT			22
570
#define UL_MODE_3P25M_CH2_CTL_MASK_SFT			BIT(22)
571
#define UL_MODE_3P25M_CH1_CTL_SFT			21
572
#define UL_MODE_3P25M_CH1_CTL_MASK_SFT			BIT(21)
573
#define UL_VOICE_MODE_CH1_CH2_CTL_SFT			17
574
#define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT		GENMASK(19, 17)
575
#define UL_AP_DMIC_ON_SFT				16
576
#define UL_AP_DMIC_ON_MASK_SFT				BIT(16)
577
#define DMIC_LOW_POWER_CTL_SFT				14
578
#define DMIC_LOW_POWER_CTL_MASK_SFT			GENMASK(15, 14)
579
#define UL_DISABLE_HW_CG_CTL_SFT			12
580
#define UL_DISABLE_HW_CG_CTL_MASK_SFT			BIT(12)
581
#define UL_IIR_ON_TMP_CTL_SFT				10
582
#define UL_IIR_ON_TMP_CTL_MASK_SFT			BIT(10)
583
#define UL_IIRMODE_CTL_SFT				7
584
#define UL_IIRMODE_CTL_MASK_SFT				GENMASK(9, 7)
585
#define DIGMIC_4P33M_SEL_SFT				6
586
#define DIGMIC_4P33M_SEL_MASK_SFT			BIT(6)
587
#define DIGMIC_3P25M_1P625M_SEL_SFT			5
588
#define DIGMIC_3P25M_1P625M_SEL_MASK_SFT		BIT(5)
589
#define UL_LOOP_BACK_MODE_SFT				2
590
#define UL_LOOP_BACK_MODE_MASK_SFT			BIT(2)
591
#define UL_SDM_3_LEVEL_SFT				1
592
#define UL_SDM_3_LEVEL_MASK_SFT				BIT(1)
593
#define UL_SRC_ON_CTL_SFT				0
594
#define UL_SRC_ON_CTL_MASK_SFT				BIT(0)
595

596
/* AFE_ADDA_UL_SRC_CON1 */
597
#define C_DAC_EN_CTL_SFT				27
598
#define C_DAC_EN_CTL_MASK_SFT				BIT(27)
599
#define C_MUTE_SW_CTL_SFT				26
600
#define C_MUTE_SW_CTL_MASK_SFT				BIT(26)
601
#define ASDM_SRC_SEL_CTL_SFT				25
602
#define ASDM_SRC_SEL_CTL_MASK_SFT			BIT(25)
603
#define C_AMP_DIV_CH2_CTL_SFT				21
604
#define C_AMP_DIV_CH2_CTL_MASK_SFT			GENMASK(23, 21)
605
#define C_FREQ_DIV_CH2_CTL_SFT				16
606
#define C_FREQ_DIV_CH2_CTL_MASK_SFT			GENMASK(20, 16)
607
#define C_SINE_MODE_CH2_CTL_SFT				12
608
#define C_SINE_MODE_CH2_CTL_MASK_SFT			GENMASK(15, 12)
609
#define C_AMP_DIV_CH1_CTL_SFT				9
610
#define C_AMP_DIV_CH1_CTL_MASK_SFT			GENMASK(11, 9)
611
#define C_FREQ_DIV_CH1_CTL_SFT				4
612
#define C_FREQ_DIV_CH1_CTL_MASK_SFT			GENMASK(8, 4)
613
#define C_SINE_MODE_CH1_CTL_SFT				0
614
#define C_SINE_MODE_CH1_CTL_MASK_SFT			GENMASK(3, 0)
615

616
/* AFE_ADDA_TOP_CON0 */
617
#define C_LOOP_BACK_MODE_CTL_SFT			12
618
#define C_LOOP_BACK_MODE_CTL_MASK_SFT			GENMASK(15, 12)
619
#define ADDA_UL_GAIN_MODE_SFT				8
620
#define ADDA_UL_GAIN_MODE_MASK_SFT			GENMASK(9, 8)
621
#define C_EXT_ADC_CTL_SFT				0
622
#define C_EXT_ADC_CTL_MASK_SFT				BIT(0)
623

624
/* AFE_ADDA_UL_DL_CON0 */
625
#define AFE_ADDA_UL_LR_SWAP_SFT				31
626
#define AFE_ADDA_UL_LR_SWAP_MASK_SFT			BIT(31)
627
#define AFE_ADDA_CKDIV_RST_SFT				30
628
#define AFE_ADDA_CKDIV_RST_MASK_SFT			BIT(30)
629
#define AFE_ADDA_FIFO_AUTO_RST_SFT			29
630
#define AFE_ADDA_FIFO_AUTO_RST_MASK_SFT			BIT(29)
631
#define AFE_ADDA_UL_FIFO_DIGMIC_TESTIN_SFT		21
632
#define AFE_ADDA_UL_FIFO_DIGMIC_TESTIN_MASK_SFT		GENMASK(22, 21)
633
#define AFE_ADDA_UL_FIFO_DIGMIC_WDATA_TESTEN_SFT	20
634
#define AFE_ADDA_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT	BIT(20)
635
#define AFE_ADDA6_UL_LR_SWAP_SFT			15
636
#define AFE_ADDA6_UL_LR_SWAP_MASK_SFT			BIT(15)
637
#define AFE_ADDA6_CKDIV_RST_SFT				14
638
#define AFE_ADDA6_CKDIV_RST_MASK_SFT			BIT(14)
639
#define AFE_ADDA6_FIFO_AUTO_RST_SFT			13
640
#define AFE_ADDA6_FIFO_AUTO_RST_MASK_SFT		BIT(13)
641
#define AFE_ADDA6_UL_FIFO_DIGMIC_TESTIN_SFT		5
642
#define AFE_ADDA6_UL_FIFO_DIGMIC_TESTIN_MASK_SFT	GENMASK(6, 5)
643
#define AFE_ADDA6_UL_FIFO_DIGMIC_WDATA_TESTEN_SFT	4
644
#define AFE_ADDA6_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT	BIT(4)
645
#define ADDA_AFE_ON_SFT					0
646
#define ADDA_AFE_ON_MASK_SFT				BIT(0)
647

648
/* AFE_SIDETONE_CON0 */
649
#define R_RDY_SFT					30
650
#define R_RDY_MASK_SFT					BIT(30)
651
#define W_RDY_SFT					29
652
#define W_RDY_MASK_SFT					BIT(29)
653
#define R_W_EN_SFT					25
654
#define R_W_EN_MASK_SFT					BIT(25)
655
#define R_W_SEL_SFT					24
656
#define R_W_SEL_MASK_SFT				BIT(24)
657
#define SEL_CH2_SFT					23
658
#define SEL_CH2_MASK_SFT				BIT(23)
659
#define SIDE_TONE_COEFFICIENT_ADDR_SFT			16
660
#define SIDE_TONE_COEFFICIENT_ADDR_MASK_SFT		GENMASK(20, 16)
661
#define SIDE_TONE_COEFFICIENT_SFT			0
662
#define SIDE_TONE_COEFFICIENT_MASK_SFT			GENMASK(15, 0)
663

664
/* AFE_SIDETONE_COEFF */
665
#define SIDE_TONE_COEFF_SFT				0
666
#define SIDE_TONE_COEFF_MASK_SFT			GENMASK(15, 0)
667

668
/* AFE_SIDETONE_CON1 */
669
#define STF_BYPASS_MODE_SFT				31
670
#define STF_BYPASS_MODE_MASK_SFT			BIT(31)
671
#define STF_BYPASS_MODE_O28_O29_SFT			30
672
#define STF_BYPASS_MODE_O28_O29_MASK_SFT		BIT(30)
673
#define STF_BYPASS_MODE_I2S4_SFT			29
674
#define STF_BYPASS_MODE_I2S4_MASK_SFT			BIT(29)
675
#define STF_BYPASS_MODE_DL3_SFT				27
676
#define STF_BYPASS_MODE_DL3_MASK_SFT			BIT(27)
677
#define STF_BYPASS_MODE_I2S7_SFT			26
678
#define STF_BYPASS_MODE_I2S7_MASK_SFT			BIT(26)
679
#define STF_BYPASS_MODE_I2S9_SFT			25
680
#define STF_BYPASS_MODE_I2S9_MASK_SFT			BIT(25)
681
#define STF_O19O20_OUT_EN_SEL_SFT			13
682
#define STF_O19O20_OUT_EN_SEL_MASK_SFT			BIT(13)
683
#define STF_SOURCE_FROM_O19O20_SFT			12
684
#define STF_SOURCE_FROM_O19O20_MASK_SFT			BIT(12)
685
#define SIDE_TONE_ON_SFT				8
686
#define SIDE_TONE_ON_MASK_SFT				BIT(8)
687
#define SIDE_TONE_HALF_TAP_NUM_SFT			0
688
#define SIDE_TONE_HALF_TAP_NUM_MASK_SFT			GENMASK(5, 0)
689

690
/* AFE_SIDETONE_GAIN */
691
#define POSITIVE_GAIN_SFT				16
692
#define POSITIVE_GAIN_MASK_SFT				GENMASK(18, 16)
693
#define SIDE_TONE_GAIN_SFT				0
694
#define SIDE_TONE_GAIN_MASK_SFT				GENMASK(15, 0)
695

696
/* AFE_ADDA_DL_SDM_DCCOMP_CON */
697
#define USE_3RD_SDM_SFT					28
698
#define USE_3RD_SDM_MASK_SFT				BIT(28)
699
#define DL_FIFO_START_POINT_SFT				24
700
#define DL_FIFO_START_POINT_MASK_SFT			GENMASK(26, 24)
701
#define DL_FIFO_SWAP_SFT				20
702
#define DL_FIFO_SWAP_MASK_SFT				BIT(20)
703
#define C_AUDSDM1ORDSELECT_CTL_SFT			19
704
#define C_AUDSDM1ORDSELECT_CTL_MASK_SFT			BIT(19)
705
#define C_SDM7BITSEL_CTL_SFT				18
706
#define C_SDM7BITSEL_CTL_MASK_SFT			BIT(18)
707
#define GAIN_AT_SDM_RST_PRE_CTL_SFT			15
708
#define GAIN_AT_SDM_RST_PRE_CTL_MASK_SFT		BIT(15)
709
#define DL_DCM_AUTO_IDLE_EN_SFT				14
710
#define DL_DCM_AUTO_IDLE_EN_MASK_SFT			BIT(14)
711
#define AFE_DL_SRC_DCM_EN_SFT				13
712
#define AFE_DL_SRC_DCM_EN_MASK_SFT			BIT(13)
713
#define AFE_DL_POST_SRC_DCM_EN_SFT			12
714
#define AFE_DL_POST_SRC_DCM_EN_MASK_SFT			BIT(12)
715
#define AUD_SDM_MONO_SFT				9
716
#define AUD_SDM_MONO_MASK_SFT				BIT(9)
717
#define AUD_DC_COMP_EN_SFT				8
718
#define AUD_DC_COMP_EN_MASK_SFT				BIT(8)
719
#define ATTGAIN_CTL_SFT					0
720
#define ATTGAIN_CTL_MASK_SFT				GENMASK(5, 0)
721

722
/* AFE_SINEGEN_CON0 */
723
#define DAC_EN_SFT					26
724
#define DAC_EN_MASK					0x1
725
#define DAC_EN_MASK_SFT					BIT(26)
726
#define MUTE_SW_CH2_SFT					25
727
#define MUTE_SW_CH2_MASK				0x1
728
#define MUTE_SW_CH2_MASK_SFT				BIT(25)
729
#define MUTE_SW_CH1_SFT					24
730
#define MUTE_SW_CH1_MASK				0x1
731
#define MUTE_SW_CH1_MASK_SFT				BIT(24)
732
#define SINE_MODE_CH2_SFT				20
733
#define SINE_MODE_CH2_MASK				0xf
734
#define SINE_MODE_CH2_MASK_SFT				GENMASK(23, 20)
735
#define AMP_DIV_CH2_SFT					17
736
#define AMP_DIV_CH2_MASK				0x7
737
#define AMP_DIV_CH2_MASK_SFT				GENMASK(19, 17)
738
#define FREQ_DIV_CH2_SFT				12
739
#define FREQ_DIV_CH2_MASK				0x1f
740
#define FREQ_DIV_CH2_MASK_SFT				GENMASK(16, 12)
741
#define SINE_MODE_CH1_SFT				8
742
#define SINE_MODE_CH1_MASK				0xf
743
#define SINE_MODE_CH1_MASK_SFT				GENMASK(11, 8)
744
#define AMP_DIV_CH1_SFT					5
745
#define AMP_DIV_CH1_MASK				0x7
746
#define AMP_DIV_CH1_MASK_SFT				GENMASK(7, 5)
747
#define FREQ_DIV_CH1_SFT				0
748
#define FREQ_DIV_CH1_MASK				0x1f
749
#define FREQ_DIV_CH1_MASK_SFT				GENMASK(4, 0)
750

751
/* AFE_SINEGEN_CON2 */
752
#define INNER_LOOP_BACK_MODE_SFT			0
753
#define INNER_LOOP_BACK_MODE_MASK_SFT			GENMASK(7, 0)
754

755
/* AFE_HD_ENGEN_ENABLE */
756
#define AFE_24M_ON_SFT					1
757
#define AFE_24M_ON_MASK_SFT				BIT(1)
758
#define AFE_22M_ON_SFT					0
759
#define AFE_22M_ON_MASK_SFT				BIT(0)
760

761
/* AFE_ADDA_DL_NLE_FIFO_MON */
762
#define DL_NLE_FIFO_WBIN_SFT				8
763
#define DL_NLE_FIFO_WBIN_MASK_SFT			GENMASK(11, 8)
764
#define DL_NLE_FIFO_RBIN_SFT				4
765
#define DL_NLE_FIFO_RBIN_MASK_SFT			GENMASK(7, 4)
766
#define DL_NLE_FIFO_RDACTIVE_SFT			3
767
#define DL_NLE_FIFO_RDACTIVE_MASK_SFT			BIT(3)
768
#define DL_NLE_FIFO_STARTRD_SFT				2
769
#define DL_NLE_FIFO_STARTRD_MASK_SFT			BIT(2)
770
#define DL_NLE_FIFO_RD_EMPTY_SFT			1
771
#define DL_NLE_FIFO_RD_EMPTY_MASK_SFT			BIT(1)
772
#define DL_NLE_FIFO_WR_FULL_SFT				0
773
#define DL_NLE_FIFO_WR_FULL_MASK_SFT			BIT(0)
774

775
/* AFE_DL1_CON0 */
776
#define DL1_MODE_SFT					24
777
#define DL1_MODE_MASK					0xf
778
#define DL1_MODE_MASK_SFT				GENMASK(27, 24)
779
#define DL1_MINLEN_SFT					20
780
#define DL1_MINLEN_MASK					0xf
781
#define DL1_MINLEN_MASK_SFT				GENMASK(23, 20)
782
#define DL1_MAXLEN_SFT					16
783
#define DL1_MAXLEN_MASK					0xf
784
#define DL1_MAXLEN_MASK_SFT				GENMASK(19, 16)
785
#define DL1_SW_CLEAR_BUF_EMPTY_SFT			15
786
#define DL1_SW_CLEAR_BUF_EMPTY_MASK			0x1
787
#define DL1_SW_CLEAR_BUF_EMPTY_MASK_SFT			BIT(15)
788
#define DL1_PBUF_SIZE_SFT				12
789
#define DL1_PBUF_SIZE_MASK				0x3
790
#define DL1_PBUF_SIZE_MASK_SFT				GENMASK(13, 12)
791
#define DL1_MONO_SFT					8
792
#define DL1_MONO_MASK					0x1
793
#define DL1_MONO_MASK_SFT				BIT(8)
794
#define DL1_NORMAL_MODE_SFT				5
795
#define DL1_NORMAL_MODE_MASK				0x1
796
#define DL1_NORMAL_MODE_MASK_SFT			BIT(5)
797
#define DL1_HALIGN_SFT					4
798
#define DL1_HALIGN_MASK					0x1
799
#define DL1_HALIGN_MASK_SFT				BIT(4)
800
#define DL1_HD_MODE_SFT					0
801
#define DL1_HD_MODE_MASK				0x3
802
#define DL1_HD_MODE_MASK_SFT				GENMASK(1, 0)
803

804
/* AFE_DL2_CON0 */
805
#define DL2_MODE_SFT					24
806
#define DL2_MODE_MASK					0xf
807
#define DL2_MODE_MASK_SFT				GENMASK(27, 24)
808
#define DL2_MINLEN_SFT					20
809
#define DL2_MINLEN_MASK					0xf
810
#define DL2_MINLEN_MASK_SFT				GENMASK(23, 20)
811
#define DL2_MAXLEN_SFT					16
812
#define DL2_MAXLEN_MASK					0xf
813
#define DL2_MAXLEN_MASK_SFT				GENMASK(19, 16)
814
#define DL2_SW_CLEAR_BUF_EMPTY_SFT			15
815
#define DL2_SW_CLEAR_BUF_EMPTY_MASK			0x1
816
#define DL2_SW_CLEAR_BUF_EMPTY_MASK_SFT			BIT(15)
817
#define DL2_PBUF_SIZE_SFT				12
818
#define DL2_PBUF_SIZE_MASK				0x3
819
#define DL2_PBUF_SIZE_MASK_SFT				GENMASK(13, 12)
820
#define DL2_MONO_SFT					8
821
#define DL2_MONO_MASK					0x1
822
#define DL2_MONO_MASK_SFT				BIT(8)
823
#define DL2_NORMAL_MODE_SFT				5
824
#define DL2_NORMAL_MODE_MASK				0x1
825
#define DL2_NORMAL_MODE_MASK_SFT			BIT(5)
826
#define DL2_HALIGN_SFT					4
827
#define DL2_HALIGN_MASK					0x1
828
#define DL2_HALIGN_MASK_SFT				BIT(4)
829
#define DL2_HD_MODE_SFT					0
830
#define DL2_HD_MODE_MASK				0x3
831
#define DL2_HD_MODE_MASK_SFT				GENMASK(1, 0)
832

833
/* AFE_DL3_CON0 */
834
#define DL3_MODE_SFT					24
835
#define DL3_MODE_MASK					0xf
836
#define DL3_MODE_MASK_SFT				GENMASK(27, 24)
837
#define DL3_MINLEN_SFT					20
838
#define DL3_MINLEN_MASK					0xf
839
#define DL3_MINLEN_MASK_SFT				GENMASK(23, 20)
840
#define DL3_MAXLEN_SFT					16
841
#define DL3_MAXLEN_MASK					0xf
842
#define DL3_MAXLEN_MASK_SFT				GENMASK(19, 16)
843
#define DL3_SW_CLEAR_BUF_EMPTY_SFT			15
844
#define DL3_SW_CLEAR_BUF_EMPTY_MASK			0x1
845
#define DL3_SW_CLEAR_BUF_EMPTY_MASK_SFT			BIT(15)
846
#define DL3_PBUF_SIZE_SFT				12
847
#define DL3_PBUF_SIZE_MASK				0x3
848
#define DL3_PBUF_SIZE_MASK_SFT				GENMASK(13, 12)
849
#define DL3_MONO_SFT					8
850
#define DL3_MONO_MASK					0x1
851
#define DL3_MONO_MASK_SFT				BIT(8)
852
#define DL3_NORMAL_MODE_SFT				5
853
#define DL3_NORMAL_MODE_MASK				0x1
854
#define DL3_NORMAL_MODE_MASK_SFT			BIT(5)
855
#define DL3_HALIGN_SFT					4
856
#define DL3_HALIGN_MASK					0x1
857
#define DL3_HALIGN_MASK_SFT				BIT(4)
858
#define DL3_HD_MODE_SFT					0
859
#define DL3_HD_MODE_MASK				0x3
860
#define DL3_HD_MODE_MASK_SFT				GENMASK(1, 0)
861

862
/* AFE_DL4_CON0 */
863
#define DL4_MODE_SFT					24
864
#define DL4_MODE_MASK					0xf
865
#define DL4_MODE_MASK_SFT				GENMASK(27, 24)
866
#define DL4_MINLEN_SFT					20
867
#define DL4_MINLEN_MASK					0xf
868
#define DL4_MINLEN_MASK_SFT				GENMASK(23, 20)
869
#define DL4_MAXLEN_SFT					16
870
#define DL4_MAXLEN_MASK					0xf
871
#define DL4_MAXLEN_MASK_SFT				GENMASK(19, 16)
872
#define DL4_SW_CLEAR_BUF_EMPTY_SFT			15
873
#define DL4_SW_CLEAR_BUF_EMPTY_MASK			0x1
874
#define DL4_SW_CLEAR_BUF_EMPTY_MASK_SFT			BIT(15)
875
#define DL4_PBUF_SIZE_SFT				12
876
#define DL4_PBUF_SIZE_MASK				0x3
877
#define DL4_PBUF_SIZE_MASK_SFT				GENMASK(13, 12)
878
#define DL4_MONO_SFT					8
879
#define DL4_MONO_MASK					0x1
880
#define DL4_MONO_MASK_SFT				BIT(8)
881
#define DL4_NORMAL_MODE_SFT				5
882
#define DL4_NORMAL_MODE_MASK				0x1
883
#define DL4_NORMAL_MODE_MASK_SFT			BIT(5)
884
#define DL4_HALIGN_SFT					4
885
#define DL4_HALIGN_MASK					0x1
886
#define DL4_HALIGN_MASK_SFT				BIT(4)
887
#define DL4_HD_MODE_SFT					0
888
#define DL4_HD_MODE_MASK				0x3
889
#define DL4_HD_MODE_MASK_SFT				GENMASK(1, 0)
890

891
/* AFE_DL5_CON0 */
892
#define DL5_MODE_SFT					24
893
#define DL5_MODE_MASK					0xf
894
#define DL5_MODE_MASK_SFT				GENMASK(27, 24)
895
#define DL5_MINLEN_SFT					20
896
#define DL5_MINLEN_MASK					0xf
897
#define DL5_MINLEN_MASK_SFT				GENMASK(23, 20)
898
#define DL5_MAXLEN_SFT					16
899
#define DL5_MAXLEN_MASK					0xf
900
#define DL5_MAXLEN_MASK_SFT				GENMASK(19, 16)
901
#define DL5_SW_CLEAR_BUF_EMPTY_SFT			15
902
#define DL5_SW_CLEAR_BUF_EMPTY_MASK			0x1
903
#define DL5_SW_CLEAR_BUF_EMPTY_MASK_SFT			BIT(15)
904
#define DL5_PBUF_SIZE_SFT				12
905
#define DL5_PBUF_SIZE_MASK				0x3
906
#define DL5_PBUF_SIZE_MASK_SFT				GENMASK(13, 12)
907
#define DL5_MONO_SFT					8
908
#define DL5_MONO_MASK					0x1
909
#define DL5_MONO_MASK_SFT				BIT(8)
910
#define DL5_NORMAL_MODE_SFT				5
911
#define DL5_NORMAL_MODE_MASK				0x1
912
#define DL5_NORMAL_MODE_MASK_SFT			BIT(5)
913
#define DL5_HALIGN_SFT					4
914
#define DL5_HALIGN_MASK					0x1
915
#define DL5_HALIGN_MASK_SFT				BIT(4)
916
#define DL5_HD_MODE_SFT					0
917
#define DL5_HD_MODE_MASK				0x3
918
#define DL5_HD_MODE_MASK_SFT				GENMASK(1, 0)
919

920
/* AFE_DL6_CON0 */
921
#define DL6_MODE_SFT					24
922
#define DL6_MODE_MASK					0xf
923
#define DL6_MODE_MASK_SFT				GENMASK(27, 24)
924
#define DL6_MINLEN_SFT					20
925
#define DL6_MINLEN_MASK					0xf
926
#define DL6_MINLEN_MASK_SFT				GENMASK(23, 20)
927
#define DL6_MAXLEN_SFT					16
928
#define DL6_MAXLEN_MASK					0xf
929
#define DL6_MAXLEN_MASK_SFT				GENMASK(19, 16)
930
#define DL6_SW_CLEAR_BUF_EMPTY_SFT			15
931
#define DL6_SW_CLEAR_BUF_EMPTY_MASK			0x1
932
#define DL6_SW_CLEAR_BUF_EMPTY_MASK_SFT			BIT(15)
933
#define DL6_PBUF_SIZE_SFT				12
934
#define DL6_PBUF_SIZE_MASK				0x3
935
#define DL6_PBUF_SIZE_MASK_SFT				GENMASK(13, 12)
936
#define DL6_MONO_SFT					8
937
#define DL6_MONO_MASK					0x1
938
#define DL6_MONO_MASK_SFT				BIT(8)
939
#define DL6_NORMAL_MODE_SFT				5
940
#define DL6_NORMAL_MODE_MASK				0x1
941
#define DL6_NORMAL_MODE_MASK_SFT			BIT(5)
942
#define DL6_HALIGN_SFT					4
943
#define DL6_HALIGN_MASK					0x1
944
#define DL6_HALIGN_MASK_SFT				BIT(4)
945
#define DL6_HD_MODE_SFT					0
946
#define DL6_HD_MODE_MASK				0x3
947
#define DL6_HD_MODE_MASK_SFT				GENMASK(1, 0)
948

949
/* AFE_DL7_CON0 */
950
#define DL7_MODE_SFT					24
951
#define DL7_MODE_MASK					0xf
952
#define DL7_MODE_MASK_SFT				GENMASK(27, 24)
953
#define DL7_MINLEN_SFT					20
954
#define DL7_MINLEN_MASK					0xf
955
#define DL7_MINLEN_MASK_SFT				GENMASK(23, 20)
956
#define DL7_MAXLEN_SFT					16
957
#define DL7_MAXLEN_MASK					0xf
958
#define DL7_MAXLEN_MASK_SFT				GENMASK(19, 16)
959
#define DL7_SW_CLEAR_BUF_EMPTY_SFT			15
960
#define DL7_SW_CLEAR_BUF_EMPTY_MASK			0x1
961
#define DL7_SW_CLEAR_BUF_EMPTY_MASK_SFT			BIT(15)
962
#define DL7_PBUF_SIZE_SFT				12
963
#define DL7_PBUF_SIZE_MASK				0x3
964
#define DL7_PBUF_SIZE_MASK_SFT				GENMASK(13, 12)
965
#define DL7_MONO_SFT					8
966
#define DL7_MONO_MASK					0x1
967
#define DL7_MONO_MASK_SFT				BIT(8)
968
#define DL7_NORMAL_MODE_SFT				5
969
#define DL7_NORMAL_MODE_MASK				0x1
970
#define DL7_NORMAL_MODE_MASK_SFT			BIT(5)
971
#define DL7_HALIGN_SFT					4
972
#define DL7_HALIGN_MASK					0x1
973
#define DL7_HALIGN_MASK_SFT				BIT(4)
974
#define DL7_HD_MODE_SFT					0
975
#define DL7_HD_MODE_MASK				0x3
976
#define DL7_HD_MODE_MASK_SFT				GENMASK(1, 0)
977

978
/* AFE_DL8_CON0 */
979
#define DL8_MODE_SFT					24
980
#define DL8_MODE_MASK					0xf
981
#define DL8_MODE_MASK_SFT				GENMASK(27, 24)
982
#define DL8_MINLEN_SFT					20
983
#define DL8_MINLEN_MASK					0xf
984
#define DL8_MINLEN_MASK_SFT				GENMASK(23, 20)
985
#define DL8_MAXLEN_SFT					16
986
#define DL8_MAXLEN_MASK					0xf
987
#define DL8_MAXLEN_MASK_SFT				GENMASK(19, 16)
988
#define DL8_SW_CLEAR_BUF_EMPTY_SFT			15
989
#define DL8_SW_CLEAR_BUF_EMPTY_MASK			0x1
990
#define DL8_SW_CLEAR_BUF_EMPTY_MASK_SFT			BIT(15)
991
#define DL8_PBUF_SIZE_SFT				12
992
#define DL8_PBUF_SIZE_MASK				0x3
993
#define DL8_PBUF_SIZE_MASK_SFT				GENMASK(13, 12)
994
#define DL8_MONO_SFT					8
995
#define DL8_MONO_MASK					0x1
996
#define DL8_MONO_MASK_SFT				BIT(8)
997
#define DL8_NORMAL_MODE_SFT				5
998
#define DL8_NORMAL_MODE_MASK				0x1
999
#define DL8_NORMAL_MODE_MASK_SFT			BIT(5)
1000
#define DL8_HALIGN_SFT					4
1001
#define DL8_HALIGN_MASK					0x1
1002
#define DL8_HALIGN_MASK_SFT				BIT(4)
1003
#define DL8_HD_MODE_SFT					0
1004
#define DL8_HD_MODE_MASK				0x3
1005
#define DL8_HD_MODE_MASK_SFT				GENMASK(1, 0)
1006

1007
/* AFE_DL12_CON0 */
1008
#define DL12_MODE_SFT					24
1009
#define DL12_MODE_MASK					0xf
1010
#define DL12_MODE_MASK_SFT				GENMASK(27, 24)
1011
#define DL12_MINLEN_SFT					20
1012
#define DL12_MINLEN_MASK				0xf
1013
#define DL12_MINLEN_MASK_SFT				GENMASK(23, 20)
1014
#define DL12_MAXLEN_SFT					16
1015
#define DL12_MAXLEN_MASK				0xf
1016
#define DL12_MAXLEN_MASK_SFT				GENMASK(19, 16)
1017
#define DL12_SW_CLEAR_BUF_EMPTY_SFT			15
1018
#define DL12_SW_CLEAR_BUF_EMPTY_MASK			0x1
1019
#define DL12_SW_CLEAR_BUF_EMPTY_MASK_SFT		BIT(15)
1020
#define DL12_PBUF_SIZE_SFT				12
1021
#define DL12_PBUF_SIZE_MASK				0x3
1022
#define DL12_PBUF_SIZE_MASK_SFT				GENMASK(13, 12)
1023
#define DL12_4CH_EN_SFT					11
1024
#define DL12_4CH_EN_MASK				0x1
1025
#define DL12_4CH_EN_MASK_SFT				BIT(11)
1026
#define DL12_MONO_SFT					8
1027
#define DL12_MONO_MASK					0x1
1028
#define DL12_MONO_MASK_SFT				BIT(8)
1029
#define DL12_NORMAL_MODE_SFT				5
1030
#define DL12_NORMAL_MODE_MASK				0x1
1031
#define DL12_NORMAL_MODE_MASK_SFT			BIT(5)
1032
#define DL12_HALIGN_SFT					4
1033
#define DL12_HALIGN_MASK				0x1
1034
#define DL12_HALIGN_MASK_SFT				BIT(4)
1035
#define DL12_HD_MODE_SFT				0
1036
#define DL12_HD_MODE_MASK				0x3
1037
#define DL12_HD_MODE_MASK_SFT				GENMASK(1, 0)
1038

1039
/* AFE_AWB_CON0 */
1040
#define AWB_MODE_SFT					24
1041
#define AWB_MODE_MASK					0xf
1042
#define AWB_MODE_MASK_SFT				GENMASK(27, 24)
1043
#define AWB_SW_CLEAR_BUF_FULL_SFT			15
1044
#define AWB_SW_CLEAR_BUF_FULL_MASK			0x1
1045
#define AWB_SW_CLEAR_BUF_FULL_MASK_SFT			BIT(15)
1046
#define AWB_R_MONO_SFT					9
1047
#define AWB_R_MONO_MASK					0x1
1048
#define AWB_R_MONO_MASK_SFT				BIT(9)
1049
#define AWB_MONO_SFT					8
1050
#define AWB_MONO_MASK					0x1
1051
#define AWB_MONO_MASK_SFT				BIT(8)
1052
#define AWB_WR_SIGN_SFT					6
1053
#define AWB_WR_SIGN_MASK				0x1
1054
#define AWB_WR_SIGN_MASK_SFT				BIT(6)
1055
#define AWB_NORMAL_MODE_SFT				5
1056
#define AWB_NORMAL_MODE_MASK				0x1
1057
#define AWB_NORMAL_MODE_MASK_SFT			BIT(5)
1058
#define AWB_HALIGN_SFT					4
1059
#define AWB_HALIGN_MASK					0x1
1060
#define AWB_HALIGN_MASK_SFT				BIT(4)
1061
#define AWB_HD_MODE_SFT					0
1062
#define AWB_HD_MODE_MASK				0x3
1063
#define AWB_HD_MODE_MASK_SFT				GENMASK(1, 0)
1064

1065
/* AFE_AWB2_CON0 */
1066
#define AWB2_MODE_SFT					24
1067
#define AWB2_MODE_MASK					0xf
1068
#define AWB2_MODE_MASK_SFT				GENMASK(27, 24)
1069
#define AWB2_SW_CLEAR_BUF_FULL_SFT			15
1070
#define AWB2_SW_CLEAR_BUF_FULL_MASK			0x1
1071
#define AWB2_SW_CLEAR_BUF_FULL_MASK_SFT			BIT(15)
1072
#define AWB2_R_MONO_SFT					9
1073
#define AWB2_R_MONO_MASK				0x1
1074
#define AWB2_R_MONO_MASK_SFT				BIT(9)
1075
#define AWB2_MONO_SFT					8
1076
#define AWB2_MONO_MASK					0x1
1077
#define AWB2_MONO_MASK_SFT				BIT(8)
1078
#define AWB2_WR_SIGN_SFT				6
1079
#define AWB2_WR_SIGN_MASK				0x1
1080
#define AWB2_WR_SIGN_MASK_SFT				BIT(6)
1081
#define AWB2_NORMAL_MODE_SFT				5
1082
#define AWB2_NORMAL_MODE_MASK				0x1
1083
#define AWB2_NORMAL_MODE_MASK_SFT			BIT(5)
1084
#define AWB2_HALIGN_SFT					4
1085
#define AWB2_HALIGN_MASK				0x1
1086
#define AWB2_HALIGN_MASK_SFT				BIT(4)
1087
#define AWB2_HD_MODE_SFT				0
1088
#define AWB2_HD_MODE_MASK				0x3
1089
#define AWB2_HD_MODE_MASK_SFT				GENMASK(1, 0)
1090

1091
/* AFE_VUL_CON0 */
1092
#define VUL_MODE_SFT					24
1093
#define VUL_MODE_MASK					0xf
1094
#define VUL_MODE_MASK_SFT				GENMASK(27, 24)
1095
#define VUL_SW_CLEAR_BUF_FULL_SFT			15
1096
#define VUL_SW_CLEAR_BUF_FULL_MASK			0x1
1097
#define VUL_SW_CLEAR_BUF_FULL_MASK_SFT			BIT(15)
1098
#define VUL_R_MONO_SFT					9
1099
#define VUL_R_MONO_MASK					0x1
1100
#define VUL_R_MONO_MASK_SFT				BIT(9)
1101
#define VUL_MONO_SFT					8
1102
#define VUL_MONO_MASK					0x1
1103
#define VUL_MONO_MASK_SFT				BIT(8)
1104
#define VUL_WR_SIGN_SFT					6
1105
#define VUL_WR_SIGN_MASK				0x1
1106
#define VUL_WR_SIGN_MASK_SFT				BIT(6)
1107
#define VUL_NORMAL_MODE_SFT				5
1108
#define VUL_NORMAL_MODE_MASK				0x1
1109
#define VUL_NORMAL_MODE_MASK_SFT			BIT(5)
1110
#define VUL_HALIGN_SFT					4
1111
#define VUL_HALIGN_MASK					0x1
1112
#define VUL_HALIGN_MASK_SFT				BIT(4)
1113
#define VUL_HD_MODE_SFT					0
1114
#define VUL_HD_MODE_MASK				0x3
1115
#define VUL_HD_MODE_MASK_SFT				GENMASK(1, 0)
1116

1117
/* AFE_VUL12_CON0 */
1118
#define VUL12_MODE_SFT					24
1119
#define VUL12_MODE_MASK					0xf
1120
#define VUL12_MODE_MASK_SFT				GENMASK(27, 24)
1121
#define VUL12_SW_CLEAR_BUF_FULL_SFT			15
1122
#define VUL12_SW_CLEAR_BUF_FULL_MASK			0x1
1123
#define VUL12_SW_CLEAR_BUF_FULL_MASK_SFT		BIT(15)
1124
#define VUL12_4CH_EN_SFT				11
1125
#define VUL12_4CH_EN_MASK				0x1
1126
#define VUL12_4CH_EN_MASK_SFT				BIT(11)
1127
#define VUL12_R_MONO_SFT				9
1128
#define VUL12_R_MONO_MASK				0x1
1129
#define VUL12_R_MONO_MASK_SFT				BIT(9)
1130
#define VUL12_MONO_SFT					8
1131
#define VUL12_MONO_MASK					0x1
1132
#define VUL12_MONO_MASK_SFT				BIT(8)
1133
#define VUL12_WR_SIGN_SFT				6
1134
#define VUL12_WR_SIGN_MASK				0x1
1135
#define VUL12_WR_SIGN_MASK_SFT				BIT(6)
1136
#define VUL12_NORMAL_MODE_SFT				5
1137
#define VUL12_NORMAL_MODE_MASK				0x1
1138
#define VUL12_NORMAL_MODE_MASK_SFT			BIT(5)
1139
#define VUL12_HALIGN_SFT				4
1140
#define VUL12_HALIGN_MASK				0x1
1141
#define VUL12_HALIGN_MASK_SFT				BIT(4)
1142
#define VUL12_HD_MODE_SFT				0
1143
#define VUL12_HD_MODE_MASK				0x3
1144
#define VUL12_HD_MODE_MASK_SFT				GENMASK(1, 0)
1145

1146
/* AFE_VUL2_CON0 */
1147
#define VUL2_MODE_SFT					24
1148
#define VUL2_MODE_MASK					0xf
1149
#define VUL2_MODE_MASK_SFT				GENMASK(27, 24)
1150
#define VUL2_SW_CLEAR_BUF_FULL_SFT			15
1151
#define VUL2_SW_CLEAR_BUF_FULL_MASK			0x1
1152
#define VUL2_SW_CLEAR_BUF_FULL_MASK_SFT			BIT(15)
1153
#define VUL2_R_MONO_SFT					9
1154
#define VUL2_R_MONO_MASK				0x1
1155
#define VUL2_R_MONO_MASK_SFT				BIT(9)
1156
#define VUL2_MONO_SFT					8
1157
#define VUL2_MONO_MASK					0x1
1158
#define VUL2_MONO_MASK_SFT				BIT(8)
1159
#define VUL2_WR_SIGN_SFT				6
1160
#define VUL2_WR_SIGN_MASK				0x1
1161
#define VUL2_WR_SIGN_MASK_SFT				BIT(6)
1162
#define VUL2_NORMAL_MODE_SFT				5
1163
#define VUL2_NORMAL_MODE_MASK				0x1
1164
#define VUL2_NORMAL_MODE_MASK_SFT			BIT(5)
1165
#define VUL2_HALIGN_SFT					4
1166
#define VUL2_HALIGN_MASK				0x1
1167
#define VUL2_HALIGN_MASK_SFT				BIT(4)
1168
#define VUL2_HD_MODE_SFT				0
1169
#define VUL2_HD_MODE_MASK				0x3
1170
#define VUL2_HD_MODE_MASK_SFT				GENMASK(1, 0)
1171

1172
/* AFE_VUL3_CON0 */
1173
#define VUL3_MODE_SFT					24
1174
#define VUL3_MODE_MASK					0xf
1175
#define VUL3_MODE_MASK_SFT				GENMASK(27, 24)
1176
#define VUL3_SW_CLEAR_BUF_FULL_SFT			15
1177
#define VUL3_SW_CLEAR_BUF_FULL_MASK			0x1
1178
#define VUL3_SW_CLEAR_BUF_FULL_MASK_SFT			BIT(15)
1179
#define VUL3_R_MONO_SFT					9
1180
#define VUL3_R_MONO_MASK				0x1
1181
#define VUL3_R_MONO_MASK_SFT				BIT(9)
1182
#define VUL3_MONO_SFT					8
1183
#define VUL3_MONO_MASK					0x1
1184
#define VUL3_MONO_MASK_SFT				BIT(8)
1185
#define VUL3_WR_SIGN_SFT				6
1186
#define VUL3_WR_SIGN_MASK				0x1
1187
#define VUL3_WR_SIGN_MASK_SFT				BIT(6)
1188
#define VUL3_NORMAL_MODE_SFT				5
1189
#define VUL3_NORMAL_MODE_MASK				0x1
1190
#define VUL3_NORMAL_MODE_MASK_SFT			BIT(5)
1191
#define VUL3_HALIGN_SFT					4
1192
#define VUL3_HALIGN_MASK				0x1
1193
#define VUL3_HALIGN_MASK_SFT				BIT(4)
1194
#define VUL3_HD_MODE_SFT				0
1195
#define VUL3_HD_MODE_MASK				0x3
1196
#define VUL3_HD_MODE_MASK_SFT				GENMASK(1, 0)
1197

1198
/* AFE_VUL4_CON0 */
1199
#define VUL4_MODE_SFT					24
1200
#define VUL4_MODE_MASK					0xf
1201
#define VUL4_MODE_MASK_SFT				GENMASK(27, 24)
1202
#define VUL4_SW_CLEAR_BUF_FULL_SFT			15
1203
#define VUL4_SW_CLEAR_BUF_FULL_MASK			0x1
1204
#define VUL4_SW_CLEAR_BUF_FULL_MASK_SFT			BIT(15)
1205
#define VUL4_R_MONO_SFT					9
1206
#define VUL4_R_MONO_MASK				0x1
1207
#define VUL4_R_MONO_MASK_SFT				BIT(9)
1208
#define VUL4_MONO_SFT					8
1209
#define VUL4_MONO_MASK					0x1
1210
#define VUL4_MONO_MASK_SFT				BIT(8)
1211
#define VUL4_WR_SIGN_SFT				6
1212
#define VUL4_WR_SIGN_MASK				0x1
1213
#define VUL4_WR_SIGN_MASK_SFT				BIT(6)
1214
#define VUL4_NORMAL_MODE_SFT				5
1215
#define VUL4_NORMAL_MODE_MASK				0x1
1216
#define VUL4_NORMAL_MODE_MASK_SFT			BIT(5)
1217
#define VUL4_HALIGN_SFT					4
1218
#define VUL4_HALIGN_MASK				0x1
1219
#define VUL4_HALIGN_MASK_SFT				BIT(4)
1220
#define VUL4_HD_MODE_SFT				0
1221
#define VUL4_HD_MODE_MASK				0x3
1222
#define VUL4_HD_MODE_MASK_SFT				GENMASK(1, 0)
1223

1224
/* AFE_VUL5_CON0 */
1225
#define VUL5_MODE_SFT					24
1226
#define VUL5_MODE_MASK					0xf
1227
#define VUL5_MODE_MASK_SFT				GENMASK(27, 24)
1228
#define VUL5_SW_CLEAR_BUF_FULL_SFT			15
1229
#define VUL5_SW_CLEAR_BUF_FULL_MASK			0x1
1230
#define VUL5_SW_CLEAR_BUF_FULL_MASK_SFT			BIT(15)
1231
#define VUL5_R_MONO_SFT					9
1232
#define VUL5_R_MONO_MASK				0x1
1233
#define VUL5_R_MONO_MASK_SFT				BIT(9)
1234
#define VUL5_MONO_SFT					8
1235
#define VUL5_MONO_MASK					0x1
1236
#define VUL5_MONO_MASK_SFT				BIT(8)
1237
#define VUL5_WR_SIGN_SFT				6
1238
#define VUL5_WR_SIGN_MASK				0x1
1239
#define VUL5_WR_SIGN_MASK_SFT				BIT(6)
1240
#define VUL5_NORMAL_MODE_SFT				5
1241
#define VUL5_NORMAL_MODE_MASK				0x1
1242
#define VUL5_NORMAL_MODE_MASK_SFT			BIT(5)
1243
#define VUL5_HALIGN_SFT					4
1244
#define VUL5_HALIGN_MASK				0x1
1245
#define VUL5_HALIGN_MASK_SFT				BIT(4)
1246
#define VUL5_HD_MODE_SFT				0
1247
#define VUL5_HD_MODE_MASK				0x3
1248
#define VUL5_HD_MODE_MASK_SFT				GENMASK(1, 0)
1249

1250
/* AFE_VUL6_CON0 */
1251
#define VUL6_MODE_SFT					24
1252
#define VUL6_MODE_MASK					0xf
1253
#define VUL6_MODE_MASK_SFT				GENMASK(27, 24)
1254
#define VUL6_SW_CLEAR_BUF_FULL_SFT			15
1255
#define VUL6_SW_CLEAR_BUF_FULL_MASK			0x1
1256
#define VUL6_SW_CLEAR_BUF_FULL_MASK_SFT			BIT(15)
1257
#define VUL6_R_MONO_SFT					9
1258
#define VUL6_R_MONO_MASK				0x1
1259
#define VUL6_R_MONO_MASK_SFT				BIT(9)
1260
#define VUL6_MONO_SFT					8
1261
#define VUL6_MONO_MASK					0x1
1262
#define VUL6_MONO_MASK_SFT				BIT(8)
1263
#define VUL6_WR_SIGN_SFT				6
1264
#define VUL6_WR_SIGN_MASK				0x1
1265
#define VUL6_WR_SIGN_MASK_SFT				BIT(6)
1266
#define VUL6_NORMAL_MODE_SFT				5
1267
#define VUL6_NORMAL_MODE_MASK				0x1
1268
#define VUL6_NORMAL_MODE_MASK_SFT			BIT(5)
1269
#define VUL6_HALIGN_SFT					4
1270
#define VUL6_HALIGN_MASK				0x1
1271
#define VUL6_HALIGN_MASK_SFT				BIT(4)
1272
#define VUL6_HD_MODE_SFT				0
1273
#define VUL6_HD_MODE_MASK				0x3
1274
#define VUL6_HD_MODE_MASK_SFT				GENMASK(1, 0)
1275

1276
/* AFE_DAI_CON0 */
1277
#define DAI_MODE_SFT					24
1278
#define DAI_MODE_MASK					0x3
1279
#define DAI_MODE_MASK_SFT				GENMASK(25, 24)
1280
#define DAI_SW_CLEAR_BUF_FULL_SFT			15
1281
#define DAI_SW_CLEAR_BUF_FULL_MASK			0x1
1282
#define DAI_SW_CLEAR_BUF_FULL_MASK_SFT			BIT(15)
1283
#define DAI_DUPLICATE_WR_SFT				10
1284
#define DAI_DUPLICATE_WR_MASK				0x1
1285
#define DAI_DUPLICATE_WR_MASK_SFT			BIT(10)
1286
#define DAI_MONO_SFT					8
1287
#define DAI_MONO_MASK					0x1
1288
#define DAI_MONO_MASK_SFT				BIT(8)
1289
#define DAI_WR_SIGN_SFT					6
1290
#define DAI_WR_SIGN_MASK				0x1
1291
#define DAI_WR_SIGN_MASK_SFT				BIT(6)
1292
#define DAI_NORMAL_MODE_SFT				5
1293
#define DAI_NORMAL_MODE_MASK				0x1
1294
#define DAI_NORMAL_MODE_MASK_SFT			BIT(5)
1295
#define DAI_HALIGN_SFT					4
1296
#define DAI_HALIGN_MASK					0x1
1297
#define DAI_HALIGN_MASK_SFT				BIT(4)
1298
#define DAI_HD_MODE_SFT					0
1299
#define DAI_HD_MODE_MASK				0x3
1300
#define DAI_HD_MODE_MASK_SFT				GENMASK(1, 0)
1301

1302
/* AFE_MOD_DAI_CON0 */
1303
#define MOD_DAI_MODE_SFT				24
1304
#define MOD_DAI_MODE_MASK				0x3
1305
#define MOD_DAI_MODE_MASK_SFT				GENMASK(25, 24)
1306
#define MOD_DAI_SW_CLEAR_BUF_FULL_SFT			15
1307
#define MOD_DAI_SW_CLEAR_BUF_FULL_MASK			0x1
1308
#define MOD_DAI_SW_CLEAR_BUF_FULL_MASK_SFT		BIT(15)
1309
#define MOD_DAI_DUPLICATE_WR_SFT			10
1310
#define MOD_DAI_DUPLICATE_WR_MASK			0x1
1311
#define MOD_DAI_DUPLICATE_WR_MASK_SFT			BIT(10)
1312
#define MOD_DAI_MONO_SFT				8
1313
#define MOD_DAI_MONO_MASK				0x1
1314
#define MOD_DAI_MONO_MASK_SFT				BIT(8)
1315
#define MOD_DAI_WR_SIGN_SFT				6
1316
#define MOD_DAI_WR_SIGN_MASK				0x1
1317
#define MOD_DAI_WR_SIGN_MASK_SFT			BIT(6)
1318
#define MOD_DAI_NORMAL_MODE_SFT				5
1319
#define MOD_DAI_NORMAL_MODE_MASK			0x1
1320
#define MOD_DAI_NORMAL_MODE_MASK_SFT			BIT(5)
1321
#define MOD_DAI_HALIGN_SFT				4
1322
#define MOD_DAI_HALIGN_MASK				0x1
1323
#define MOD_DAI_HALIGN_MASK_SFT				BIT(4)
1324
#define MOD_DAI_HD_MODE_SFT				0
1325
#define MOD_DAI_HD_MODE_MASK				0x3
1326
#define MOD_DAI_HD_MODE_MASK_SFT			GENMASK(1, 0)
1327

1328
/* AFE_DAI2_CON0 */
1329
#define DAI2_MODE_SFT					24
1330
#define DAI2_MODE_MASK					0xf
1331
#define DAI2_MODE_MASK_SFT				GENMASK(27, 24)
1332
#define DAI2_SW_CLEAR_BUF_FULL_SFT			15
1333
#define DAI2_SW_CLEAR_BUF_FULL_MASK			0x1
1334
#define DAI2_SW_CLEAR_BUF_FULL_MASK_SFT			BIT(15)
1335
#define DAI2_DUPLICATE_WR_SFT				10
1336
#define DAI2_DUPLICATE_WR_MASK				0x1
1337
#define DAI2_DUPLICATE_WR_MASK_SFT			BIT(10)
1338
#define DAI2_MONO_SFT					8
1339
#define DAI2_MONO_MASK					0x1
1340
#define DAI2_MONO_MASK_SFT				BIT(8)
1341
#define DAI2_WR_SIGN_SFT				6
1342
#define DAI2_WR_SIGN_MASK				0x1
1343
#define DAI2_WR_SIGN_MASK_SFT				BIT(6)
1344
#define DAI2_NORMAL_MODE_SFT				5
1345
#define DAI2_NORMAL_MODE_MASK				0x1
1346
#define DAI2_NORMAL_MODE_MASK_SFT			BIT(5)
1347
#define DAI2_HALIGN_SFT					4
1348
#define DAI2_HALIGN_MASK				0x1
1349
#define DAI2_HALIGN_MASK_SFT				BIT(4)
1350
#define DAI2_HD_MODE_SFT				0
1351
#define DAI2_HD_MODE_MASK				0x3
1352
#define DAI2_HD_MODE_MASK_SFT				GENMASK(1, 0)
1353

1354
/* AFE_MEMIF_CON0 */
1355
#define CPU_COMPACT_MODE_SFT				2
1356
#define CPU_COMPACT_MODE_MASK_SFT			BIT(2)
1357
#define CPU_HD_ALIGN_SFT				1
1358
#define CPU_HD_ALIGN_MASK_SFT				BIT(1)
1359
#define SYSRAM_SIGN_SFT					0
1360
#define SYSRAM_SIGN_MASK_SFT				BIT(0)
1361

1362
/* AFE_IRQ_MCU_CON0 */
1363
#define IRQ31_MCU_ON_SFT				31
1364
#define IRQ31_MCU_ON_MASK				0x1
1365
#define IRQ31_MCU_ON_MASK_SFT				BIT(31)
1366
#define IRQ26_MCU_ON_SFT				26
1367
#define IRQ26_MCU_ON_MASK				0x1
1368
#define IRQ26_MCU_ON_MASK_SFT				BIT(26)
1369
#define IRQ25_MCU_ON_SFT				25
1370
#define IRQ25_MCU_ON_MASK				0x1
1371
#define IRQ25_MCU_ON_MASK_SFT				BIT(25)
1372
#define IRQ24_MCU_ON_SFT				24
1373
#define IRQ24_MCU_ON_MASK				0x1
1374
#define IRQ24_MCU_ON_MASK_SFT				BIT(24)
1375
#define IRQ23_MCU_ON_SFT				23
1376
#define IRQ23_MCU_ON_MASK				0x1
1377
#define IRQ23_MCU_ON_MASK_SFT				BIT(23)
1378
#define IRQ22_MCU_ON_SFT				22
1379
#define IRQ22_MCU_ON_MASK				0x1
1380
#define IRQ22_MCU_ON_MASK_SFT				BIT(22)
1381
#define IRQ21_MCU_ON_SFT				21
1382
#define IRQ21_MCU_ON_MASK				0x1
1383
#define IRQ21_MCU_ON_MASK_SFT				BIT(21)
1384
#define IRQ20_MCU_ON_SFT				20
1385
#define IRQ20_MCU_ON_MASK				0x1
1386
#define IRQ20_MCU_ON_MASK_SFT				BIT(20)
1387
#define IRQ19_MCU_ON_SFT				19
1388
#define IRQ19_MCU_ON_MASK				0x1
1389
#define IRQ19_MCU_ON_MASK_SFT				BIT(19)
1390
#define IRQ18_MCU_ON_SFT				18
1391
#define IRQ18_MCU_ON_MASK				0x1
1392
#define IRQ18_MCU_ON_MASK_SFT				BIT(18)
1393
#define IRQ17_MCU_ON_SFT				17
1394
#define IRQ17_MCU_ON_MASK				0x1
1395
#define IRQ17_MCU_ON_MASK_SFT				BIT(17)
1396
#define IRQ16_MCU_ON_SFT				16
1397
#define IRQ16_MCU_ON_MASK				0x1
1398
#define IRQ16_MCU_ON_MASK_SFT				BIT(16)
1399
#define IRQ15_MCU_ON_SFT				15
1400
#define IRQ15_MCU_ON_MASK				0x1
1401
#define IRQ15_MCU_ON_MASK_SFT				BIT(15)
1402
#define IRQ14_MCU_ON_SFT				14
1403
#define IRQ14_MCU_ON_MASK				0x1
1404
#define IRQ14_MCU_ON_MASK_SFT				BIT(14)
1405
#define IRQ13_MCU_ON_SFT				13
1406
#define IRQ13_MCU_ON_MASK				0x1
1407
#define IRQ13_MCU_ON_MASK_SFT				BIT(13)
1408
#define IRQ12_MCU_ON_SFT				12
1409
#define IRQ12_MCU_ON_MASK				0x1
1410
#define IRQ12_MCU_ON_MASK_SFT				BIT(12)
1411
#define IRQ11_MCU_ON_SFT				11
1412
#define IRQ11_MCU_ON_MASK				0x1
1413
#define IRQ11_MCU_ON_MASK_SFT				BIT(11)
1414
#define IRQ10_MCU_ON_SFT				10
1415
#define IRQ10_MCU_ON_MASK				0x1
1416
#define IRQ10_MCU_ON_MASK_SFT				BIT(10)
1417
#define IRQ9_MCU_ON_SFT					9
1418
#define IRQ9_MCU_ON_MASK				0x1
1419
#define IRQ9_MCU_ON_MASK_SFT				BIT(9)
1420
#define IRQ8_MCU_ON_SFT					8
1421
#define IRQ8_MCU_ON_MASK				0x1
1422
#define IRQ8_MCU_ON_MASK_SFT				BIT(8)
1423
#define IRQ7_MCU_ON_SFT					7
1424
#define IRQ7_MCU_ON_MASK				0x1
1425
#define IRQ7_MCU_ON_MASK_SFT				BIT(7)
1426
#define IRQ6_MCU_ON_SFT					6
1427
#define IRQ6_MCU_ON_MASK				0x1
1428
#define IRQ6_MCU_ON_MASK_SFT				BIT(6)
1429
#define IRQ5_MCU_ON_SFT					5
1430
#define IRQ5_MCU_ON_MASK				0x1
1431
#define IRQ5_MCU_ON_MASK_SFT				BIT(5)
1432
#define IRQ4_MCU_ON_SFT					4
1433
#define IRQ4_MCU_ON_MASK				0x1
1434
#define IRQ4_MCU_ON_MASK_SFT				BIT(4)
1435
#define IRQ3_MCU_ON_SFT					3
1436
#define IRQ3_MCU_ON_MASK				0x1
1437
#define IRQ3_MCU_ON_MASK_SFT				BIT(3)
1438
#define IRQ2_MCU_ON_SFT					2
1439
#define IRQ2_MCU_ON_MASK				0x1
1440
#define IRQ2_MCU_ON_MASK_SFT				BIT(2)
1441
#define IRQ1_MCU_ON_SFT					1
1442
#define IRQ1_MCU_ON_MASK				0x1
1443
#define IRQ1_MCU_ON_MASK_SFT				BIT(1)
1444
#define IRQ0_MCU_ON_SFT					0
1445
#define IRQ0_MCU_ON_MASK				0x1
1446
#define IRQ0_MCU_ON_MASK_SFT				BIT(0)
1447

1448
/* AFE_IRQ_MCU_CON1 */
1449
#define IRQ7_MCU_MODE_SFT				28
1450
#define IRQ7_MCU_MODE_MASK				0xf
1451
#define IRQ7_MCU_MODE_MASK_SFT				GENMASK(31, 28)
1452
#define IRQ6_MCU_MODE_SFT				24
1453
#define IRQ6_MCU_MODE_MASK				0xf
1454
#define IRQ6_MCU_MODE_MASK_SFT				GENMASK(27, 24)
1455
#define IRQ5_MCU_MODE_SFT				20
1456
#define IRQ5_MCU_MODE_MASK				0xf
1457
#define IRQ5_MCU_MODE_MASK_SFT				GENMASK(23, 20)
1458
#define IRQ4_MCU_MODE_SFT				16
1459
#define IRQ4_MCU_MODE_MASK				0xf
1460
#define IRQ4_MCU_MODE_MASK_SFT				GENMASK(19, 16)
1461
#define IRQ3_MCU_MODE_SFT				12
1462
#define IRQ3_MCU_MODE_MASK				0xf
1463
#define IRQ3_MCU_MODE_MASK_SFT				GENMASK(15, 12)
1464
#define IRQ2_MCU_MODE_SFT				8
1465
#define IRQ2_MCU_MODE_MASK				0xf
1466
#define IRQ2_MCU_MODE_MASK_SFT				GENMASK(11, 8)
1467
#define IRQ1_MCU_MODE_SFT				4
1468
#define IRQ1_MCU_MODE_MASK				0xf
1469
#define IRQ1_MCU_MODE_MASK_SFT				GENMASK(7, 4)
1470
#define IRQ0_MCU_MODE_SFT				0
1471
#define IRQ0_MCU_MODE_MASK				0xf
1472
#define IRQ0_MCU_MODE_MASK_SFT				GENMASK(3, 0)
1473

1474
/* AFE_IRQ_MCU_CON2 */
1475
#define IRQ15_MCU_MODE_SFT				28
1476
#define IRQ15_MCU_MODE_MASK				0xf
1477
#define IRQ15_MCU_MODE_MASK_SFT				GENMASK(31, 28)
1478
#define IRQ14_MCU_MODE_SFT				24
1479
#define IRQ14_MCU_MODE_MASK				0xf
1480
#define IRQ14_MCU_MODE_MASK_SFT				GENMASK(27, 24)
1481
#define IRQ13_MCU_MODE_SFT				20
1482
#define IRQ13_MCU_MODE_MASK				0xf
1483
#define IRQ13_MCU_MODE_MASK_SFT				GENMASK(23, 20)
1484
#define IRQ12_MCU_MODE_SFT				16
1485
#define IRQ12_MCU_MODE_MASK				0xf
1486
#define IRQ12_MCU_MODE_MASK_SFT				GENMASK(19, 16)
1487
#define IRQ11_MCU_MODE_SFT				12
1488
#define IRQ11_MCU_MODE_MASK				0xf
1489
#define IRQ11_MCU_MODE_MASK_SFT				GENMASK(15, 12)
1490
#define IRQ10_MCU_MODE_SFT				8
1491
#define IRQ10_MCU_MODE_MASK				0xf
1492
#define IRQ10_MCU_MODE_MASK_SFT				GENMASK(11, 8)
1493
#define IRQ9_MCU_MODE_SFT				4
1494
#define IRQ9_MCU_MODE_MASK				0xf
1495
#define IRQ9_MCU_MODE_MASK_SFT				GENMASK(7, 4)
1496
#define IRQ8_MCU_MODE_SFT				0
1497
#define IRQ8_MCU_MODE_MASK				0xf
1498
#define IRQ8_MCU_MODE_MASK_SFT				GENMASK(3, 0)
1499

1500
/* AFE_IRQ_MCU_CON3 */
1501
#define IRQ23_MCU_MODE_SFT				28
1502
#define IRQ23_MCU_MODE_MASK				0xf
1503
#define IRQ23_MCU_MODE_MASK_SFT				GENMASK(31, 28)
1504
#define IRQ22_MCU_MODE_SFT				24
1505
#define IRQ22_MCU_MODE_MASK				0xf
1506
#define IRQ22_MCU_MODE_MASK_SFT				GENMASK(27, 24)
1507
#define IRQ21_MCU_MODE_SFT				20
1508
#define IRQ21_MCU_MODE_MASK				0xf
1509
#define IRQ21_MCU_MODE_MASK_SFT				GENMASK(23, 20)
1510
#define IRQ20_MCU_MODE_SFT				16
1511
#define IRQ20_MCU_MODE_MASK				0xf
1512
#define IRQ20_MCU_MODE_MASK_SFT				GENMASK(19, 16)
1513
#define IRQ19_MCU_MODE_SFT				12
1514
#define IRQ19_MCU_MODE_MASK				0xf
1515
#define IRQ19_MCU_MODE_MASK_SFT				GENMASK(15, 12)
1516
#define IRQ18_MCU_MODE_SFT				8
1517
#define IRQ18_MCU_MODE_MASK				0xf
1518
#define IRQ18_MCU_MODE_MASK_SFT				GENMASK(11, 8)
1519
#define IRQ17_MCU_MODE_SFT				4
1520
#define IRQ17_MCU_MODE_MASK				0xf
1521
#define IRQ17_MCU_MODE_MASK_SFT				GENMASK(7, 4)
1522
#define IRQ16_MCU_MODE_SFT				0
1523
#define IRQ16_MCU_MODE_MASK				0xf
1524
#define IRQ16_MCU_MODE_MASK_SFT				GENMASK(3, 0)
1525

1526
/* AFE_IRQ_MCU_CON4 */
1527
#define IRQ26_MCU_MODE_SFT				8
1528
#define IRQ26_MCU_MODE_MASK				0xf
1529
#define IRQ26_MCU_MODE_MASK_SFT				GENMASK(11, 8)
1530
#define IRQ25_MCU_MODE_SFT				4
1531
#define IRQ25_MCU_MODE_MASK				0xf
1532
#define IRQ25_MCU_MODE_MASK_SFT				GENMASK(7, 4)
1533
#define IRQ24_MCU_MODE_SFT				0
1534
#define IRQ24_MCU_MODE_MASK				0xf
1535
#define IRQ24_MCU_MODE_MASK_SFT				GENMASK(3, 0)
1536

1537
/* AFE_IRQ_MCU_CLR */
1538
#define IRQ31_MCU_CLR_SFT				31
1539
#define IRQ31_MCU_CLR_MASK_SFT				BIT(31)
1540
#define IRQ26_MCU_CLR_SFT				26
1541
#define IRQ26_MCU_CLR_MASK_SFT				BIT(26)
1542
#define IRQ25_MCU_CLR_SFT				25
1543
#define IRQ25_MCU_CLR_MASK_SFT				BIT(25)
1544
#define IRQ24_MCU_CLR_SFT				24
1545
#define IRQ24_MCU_CLR_MASK_SFT				BIT(24)
1546
#define IRQ23_MCU_CLR_SFT				23
1547
#define IRQ23_MCU_CLR_MASK_SFT				BIT(23)
1548
#define IRQ22_MCU_CLR_SFT				22
1549
#define IRQ22_MCU_CLR_MASK_SFT				BIT(22)
1550
#define IRQ21_MCU_CLR_SFT				21
1551
#define IRQ21_MCU_CLR_MASK_SFT				BIT(21)
1552
#define IRQ20_MCU_CLR_SFT				20
1553
#define IRQ20_MCU_CLR_MASK_SFT				BIT(20)
1554
#define IRQ19_MCU_CLR_SFT				19
1555
#define IRQ19_MCU_CLR_MASK_SFT				BIT(19)
1556
#define IRQ18_MCU_CLR_SFT				18
1557
#define IRQ18_MCU_CLR_MASK_SFT				BIT(18)
1558
#define IRQ17_MCU_CLR_SFT				17
1559
#define IRQ17_MCU_CLR_MASK_SFT				BIT(17)
1560
#define IRQ16_MCU_CLR_SFT				16
1561
#define IRQ16_MCU_CLR_MASK_SFT				BIT(16)
1562
#define IRQ15_MCU_CLR_SFT				15
1563
#define IRQ15_MCU_CLR_MASK_SFT				BIT(15)
1564
#define IRQ14_MCU_CLR_SFT				14
1565
#define IRQ14_MCU_CLR_MASK_SFT				BIT(14)
1566
#define IRQ13_MCU_CLR_SFT				13
1567
#define IRQ13_MCU_CLR_MASK_SFT				BIT(13)
1568
#define IRQ12_MCU_CLR_SFT				12
1569
#define IRQ12_MCU_CLR_MASK_SFT				BIT(12)
1570
#define IRQ11_MCU_CLR_SFT				11
1571
#define IRQ11_MCU_CLR_MASK_SFT				BIT(11)
1572
#define IRQ10_MCU_CLR_SFT				10
1573
#define IRQ10_MCU_CLR_MASK_SFT				BIT(10)
1574
#define IRQ9_MCU_CLR_SFT				9
1575
#define IRQ9_MCU_CLR_MASK_SFT				BIT(9)
1576
#define IRQ8_MCU_CLR_SFT				8
1577
#define IRQ8_MCU_CLR_MASK_SFT				BIT(8)
1578
#define IRQ7_MCU_CLR_SFT				7
1579
#define IRQ7_MCU_CLR_MASK_SFT				BIT(7)
1580
#define IRQ6_MCU_CLR_SFT				6
1581
#define IRQ6_MCU_CLR_MASK_SFT				BIT(6)
1582
#define IRQ5_MCU_CLR_SFT				5
1583
#define IRQ5_MCU_CLR_MASK_SFT				BIT(5)
1584
#define IRQ4_MCU_CLR_SFT				4
1585
#define IRQ4_MCU_CLR_MASK_SFT				BIT(4)
1586
#define IRQ3_MCU_CLR_SFT				3
1587
#define IRQ3_MCU_CLR_MASK_SFT				BIT(3)
1588
#define IRQ2_MCU_CLR_SFT				2
1589
#define IRQ2_MCU_CLR_MASK_SFT				BIT(2)
1590
#define IRQ1_MCU_CLR_SFT				1
1591
#define IRQ1_MCU_CLR_MASK_SFT				BIT(1)
1592
#define IRQ0_MCU_CLR_SFT				0
1593
#define IRQ0_MCU_CLR_MASK_SFT				BIT(0)
1594

1595
/* AFE_IRQ_MCU_EN */
1596
#define IRQ31_MCU_EN_SFT				31
1597
#define IRQ30_MCU_EN_SFT				30
1598
#define IRQ29_MCU_EN_SFT				29
1599
#define IRQ28_MCU_EN_SFT				28
1600
#define IRQ27_MCU_EN_SFT				27
1601
#define IRQ26_MCU_EN_SFT				26
1602
#define IRQ25_MCU_EN_SFT				25
1603
#define IRQ24_MCU_EN_SFT				24
1604
#define IRQ23_MCU_EN_SFT				23
1605
#define IRQ22_MCU_EN_SFT				22
1606
#define IRQ21_MCU_EN_SFT				21
1607
#define IRQ20_MCU_EN_SFT				20
1608
#define IRQ19_MCU_EN_SFT				19
1609
#define IRQ18_MCU_EN_SFT				18
1610
#define IRQ17_MCU_EN_SFT				17
1611
#define IRQ16_MCU_EN_SFT				16
1612
#define IRQ15_MCU_EN_SFT				15
1613
#define IRQ14_MCU_EN_SFT				14
1614
#define IRQ13_MCU_EN_SFT				13
1615
#define IRQ12_MCU_EN_SFT				12
1616
#define IRQ11_MCU_EN_SFT				11
1617
#define IRQ10_MCU_EN_SFT				10
1618
#define IRQ9_MCU_EN_SFT					9
1619
#define IRQ8_MCU_EN_SFT					8
1620
#define IRQ7_MCU_EN_SFT					7
1621
#define IRQ6_MCU_EN_SFT					6
1622
#define IRQ5_MCU_EN_SFT					5
1623
#define IRQ4_MCU_EN_SFT					4
1624
#define IRQ3_MCU_EN_SFT					3
1625
#define IRQ2_MCU_EN_SFT					2
1626
#define IRQ1_MCU_EN_SFT					1
1627
#define IRQ0_MCU_EN_SFT					0
1628

1629
/* AFE_IRQ_MCU_SCP_EN */
1630
#define IRQ31_MCU_SCP_EN_SFT				31
1631
#define IRQ30_MCU_SCP_EN_SFT				30
1632
#define IRQ29_MCU_SCP_EN_SFT				29
1633
#define IRQ28_MCU_SCP_EN_SFT				28
1634
#define IRQ27_MCU_SCP_EN_SFT				27
1635
#define IRQ26_MCU_SCP_EN_SFT				26
1636
#define IRQ25_MCU_SCP_EN_SFT				25
1637
#define IRQ24_MCU_SCP_EN_SFT				24
1638
#define IRQ23_MCU_SCP_EN_SFT				23
1639
#define IRQ22_MCU_SCP_EN_SFT				22
1640
#define IRQ21_MCU_SCP_EN_SFT				21
1641
#define IRQ20_MCU_SCP_EN_SFT				20
1642
#define IRQ19_MCU_SCP_EN_SFT				19
1643
#define IRQ18_MCU_SCP_EN_SFT				18
1644
#define IRQ17_MCU_SCP_EN_SFT				17
1645
#define IRQ16_MCU_SCP_EN_SFT				16
1646
#define IRQ15_MCU_SCP_EN_SFT				15
1647
#define IRQ14_MCU_SCP_EN_SFT				14
1648
#define IRQ13_MCU_SCP_EN_SFT				13
1649
#define IRQ12_MCU_SCP_EN_SFT				12
1650
#define IRQ11_MCU_SCP_EN_SFT				11
1651
#define IRQ10_MCU_SCP_EN_SFT				10
1652
#define IRQ9_MCU_SCP_EN_SFT				9
1653
#define IRQ8_MCU_SCP_EN_SFT				8
1654
#define IRQ7_MCU_SCP_EN_SFT				7
1655
#define IRQ6_MCU_SCP_EN_SFT				6
1656
#define IRQ5_MCU_SCP_EN_SFT				5
1657
#define IRQ4_MCU_SCP_EN_SFT				4
1658
#define IRQ3_MCU_SCP_EN_SFT				3
1659
#define IRQ2_MCU_SCP_EN_SFT				2
1660
#define IRQ1_MCU_SCP_EN_SFT				1
1661
#define IRQ0_MCU_SCP_EN_SFT				0
1662

1663
/* AFE_IRQ_MCU_DSP_EN */
1664
#define IRQ31_MCU_DSP_EN_SFT				31
1665
#define IRQ30_MCU_DSP_EN_SFT				30
1666
#define IRQ29_MCU_DSP_EN_SFT				29
1667
#define IRQ28_MCU_DSP_EN_SFT				28
1668
#define IRQ27_MCU_DSP_EN_SFT				27
1669
#define IRQ26_MCU_DSP_EN_SFT				26
1670
#define IRQ25_MCU_DSP_EN_SFT				25
1671
#define IRQ24_MCU_DSP_EN_SFT				24
1672
#define IRQ23_MCU_DSP_EN_SFT				23
1673
#define IRQ22_MCU_DSP_EN_SFT				22
1674
#define IRQ21_MCU_DSP_EN_SFT				21
1675
#define IRQ20_MCU_DSP_EN_SFT				20
1676
#define IRQ19_MCU_DSP_EN_SFT				19
1677
#define IRQ18_MCU_DSP_EN_SFT				18
1678
#define IRQ17_MCU_DSP_EN_SFT				17
1679
#define IRQ16_MCU_DSP_EN_SFT				16
1680
#define IRQ15_MCU_DSP_EN_SFT				15
1681
#define IRQ14_MCU_DSP_EN_SFT				14
1682
#define IRQ13_MCU_DSP_EN_SFT				13
1683
#define IRQ12_MCU_DSP_EN_SFT				12
1684
#define IRQ11_MCU_DSP_EN_SFT				11
1685
#define IRQ10_MCU_DSP_EN_SFT				10
1686
#define IRQ9_MCU_DSP_EN_SFT				9
1687
#define IRQ8_MCU_DSP_EN_SFT				8
1688
#define IRQ7_MCU_DSP_EN_SFT				7
1689
#define IRQ6_MCU_DSP_EN_SFT				6
1690
#define IRQ5_MCU_DSP_EN_SFT				5
1691
#define IRQ4_MCU_DSP_EN_SFT				4
1692
#define IRQ3_MCU_DSP_EN_SFT				3
1693
#define IRQ2_MCU_DSP_EN_SFT				2
1694
#define IRQ1_MCU_DSP_EN_SFT				1
1695
#define IRQ0_MCU_DSP_EN_SFT				0
1696

1697
/* AFE_AUD_PAD_TOP */
1698
#define AUD_PAD_TOP_MON_SFT				15
1699
#define AUD_PAD_TOP_MON_MASK_SFT			GENMASK(31, 15)
1700
#define AUD_PAD_TOP_FIFO_RSP_SFT			4
1701
#define AUD_PAD_TOP_FIFO_RSP_MASK_SFT			GENMASK(7, 4)
1702
#define RG_RX_PROTOCOL2_SFT				3
1703
#define RG_RX_PROTOCOL2_MASK_SFT			BIT(3)
1704
#define RESERVDED_01_SFT				1
1705
#define RESERVDED_01_MASK_SFT				GENMASK(2, 1)
1706
#define RG_RX_FIFO_ON_SFT				0
1707
#define RG_RX_FIFO_ON_MASK_SFT				BIT(0)
1708

1709
/* AFE_ADDA_MTKAIF_SYNCWORD_CFG */
1710
#define RG_ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE_SFT	23
1711
#define RG_ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE_MASK_SFT	BIT(23)
1712

1713
/* AFE_ADDA_MTKAIF_RX_CFG0 */
1714
#define MTKAIF_RXIF_VOICE_MODE_SFT			20
1715
#define MTKAIF_RXIF_VOICE_MODE_MASK_SFT			GENMASK(23, 20)
1716
#define MTKAIF_RXIF_DETECT_ON_SFT			16
1717
#define MTKAIF_RXIF_DETECT_ON_MASK_SFT			BIT(16)
1718
#define MTKAIF_RXIF_DATA_BIT_SFT			8
1719
#define MTKAIF_RXIF_DATA_BIT_MASK_SFT			GENMASK(10, 8)
1720
#define MTKAIF_RXIF_FIFO_RSP_SFT			4
1721
#define MTKAIF_RXIF_FIFO_RSP_MASK_SFT			GENMASK(6, 4)
1722
#define MTKAIF_RXIF_DATA_MODE_SFT			0
1723
#define MTKAIF_RXIF_DATA_MODE_MASK_SFT			BIT(0)
1724

1725
/* GENERAL_ASRC_MODE */
1726
#define GENERAL2_ASRCOUT_MODE_SFT			12
1727
#define GENERAL2_ASRCOUT_MODE_MASK			0xf
1728
#define GENERAL2_ASRCOUT_MODE_MASK_SFT			GENMASK(15, 12)
1729
#define GENERAL2_ASRCIN_MODE_SFT			8
1730
#define GENERAL2_ASRCIN_MODE_MASK			0xf
1731
#define GENERAL2_ASRCIN_MODE_MASK_SFT			GENMASK(11, 8)
1732
#define GENERAL1_ASRCOUT_MODE_SFT			4
1733
#define GENERAL1_ASRCOUT_MODE_MASK			0xf
1734
#define GENERAL1_ASRCOUT_MODE_MASK_SFT			GENMASK(7, 4)
1735
#define GENERAL1_ASRCIN_MODE_SFT			0
1736
#define GENERAL1_ASRCIN_MODE_MASK			0xf
1737
#define GENERAL1_ASRCIN_MODE_MASK_SFT			GENMASK(3, 0)
1738

1739
/* GENERAL_ASRC_EN_ON */
1740
#define GENERAL2_ASRC_EN_ON_SFT				1
1741
#define GENERAL2_ASRC_EN_ON_MASK_SFT			BIT(1)
1742
#define GENERAL1_ASRC_EN_ON_SFT				0
1743
#define GENERAL1_ASRC_EN_ON_MASK_SFT			BIT(0)
1744

1745
/* AFE_GENERAL1_ASRC_2CH_CON0 */
1746
#define G_SRC_CHSET_STR_CLR_SFT				4
1747
#define G_SRC_CHSET_STR_CLR_MASK_SFT			BIT(4)
1748
#define G_SRC_CHSET_ON_SFT				2
1749
#define G_SRC_CHSET_ON_MASK_SFT				BIT(2)
1750
#define G_SRC_COEFF_SRAM_CTRL_SFT			1
1751
#define G_SRC_COEFF_SRAM_CTRL_MASK_SFT			BIT(1)
1752
#define G_SRC_ASM_ON_SFT				0
1753
#define G_SRC_ASM_ON_MASK_SFT				BIT(0)
1754

1755
/* AFE_GENERAL1_ASRC_2CH_CON3 */
1756
#define G_SRC_ASM_FREQ_4_SFT				0
1757
#define G_SRC_ASM_FREQ_4_MASK_SFT			GENMASK(23, 0)
1758

1759
/* AFE_GENERAL1_ASRC_2CH_CON4 */
1760
#define G_SRC_ASM_FREQ_5_SFT				0
1761
#define G_SRC_ASM_FREQ_5_MASK_SFT			GENMASK(23, 0)
1762

1763
/* AFE_GENERAL1_ASRC_2CH_CON13 */
1764
#define G_SRC_COEFF_SRAM_ADR_SFT			0
1765
#define G_SRC_COEFF_SRAM_ADR_MASK_SFT			GENMASK(5, 0)
1766

1767
/* AFE_GENERAL1_ASRC_2CH_CON2 */
1768
#define G_SRC_CHSET_O16BIT_SFT				19
1769
#define G_SRC_CHSET_O16BIT_MASK_SFT			BIT(19)
1770
#define G_SRC_CHSET_CLR_IIR_HISTORY_SFT			17
1771
#define G_SRC_CHSET_CLR_IIR_HISTORY_MASK_SFT		BIT(17)
1772
#define G_SRC_CHSET_IS_MONO_SFT				16
1773
#define G_SRC_CHSET_IS_MONO_MASK_SFT			BIT(16)
1774
#define G_SRC_CHSET_IIR_EN_SFT				11
1775
#define G_SRC_CHSET_IIR_EN_MASK_SFT			BIT(11)
1776
#define G_SRC_CHSET_IIR_STAGE_SFT			8
1777
#define G_SRC_CHSET_IIR_STAGE_MASK_SFT			GENMASK(10, 8)
1778
#define G_SRC_CHSET_STR_CLR_RU_SFT			5
1779
#define G_SRC_CHSET_STR_CLR_RU_MASK_SFT			BIT(5)
1780
#define G_SRC_CHSET_ON_SFT				2
1781
#define G_SRC_CHSET_ON_MASK_SFT				BIT(2)
1782
#define G_SRC_COEFF_SRAM_CTRL_SFT			1
1783
#define G_SRC_COEFF_SRAM_CTRL_MASK_SFT			BIT(1)
1784
#define G_SRC_ASM_ON_SFT				0
1785
#define G_SRC_ASM_ON_MASK_SFT				BIT(0)
1786

1787
/* AFE_ADDA_DL_SDM_DITHER_CON */
1788
#define AFE_DL_SDM_DITHER_64TAP_EN_SFT			20
1789
#define AFE_DL_SDM_DITHER_64TAP_EN_MASK_SFT		BIT(20)
1790
#define AFE_DL_SDM_DITHER_EN_SFT			16
1791
#define AFE_DL_SDM_DITHER_EN_MASK_SFT			BIT(16)
1792
#define AFE_DL_SDM_DITHER_GAIN_SFT			0
1793
#define AFE_DL_SDM_DITHER_GAIN_MASK_SFT			GENMASK(7, 0)
1794

1795
/* AFE_ADDA_DL_SDM_AUTO_RESET_CON */
1796
#define SDM_AUTO_RESET_TEST_ON_SFT			31
1797
#define SDM_AUTO_RESET_TEST_ON_MASK_SFT			BIT(31)
1798
#define AFE_DL_USE_NEW_2ND_SDM_SFT			28
1799
#define AFE_DL_USE_NEW_2ND_SDM_MASK_SFT			BIT(28)
1800
#define SDM_AUTO_RESET_COUNT_TH_SFT			0
1801
#define SDM_AUTO_RESET_COUNT_TH_MASK_SFT		GENMASK(23, 0)
1802

1803
/* AFE_ASRC_2CH_CON0 */
1804
#define CON0_CHSET_STR_CLR_SFT				4
1805
#define CON0_CHSET_STR_CLR_MASK_SFT			BIT(4)
1806
#define CON0_ASM_ON_SFT					0
1807
#define CON0_ASM_ON_MASK_SFT				BIT(0)
1808

1809
/* AFE_ASRC_2CH_CON5 */
1810
#define CALI_EN_SFT					0
1811
#define CALI_EN_MASK_SFT				BIT(0)
1812

1813
/* FPGA_CFG4 */
1814
#define IRQ_COUNTER_SFT					3
1815
#define IRQ_COUNTER_MASK_SFT				GENMASK(31, 3)
1816
#define IRQ_CLK_COUNTER_CLEAN_SFT			2
1817
#define IRQ_CLK_COUNTER_CLEAN_MASK_SFT			BIT(2)
1818
#define IRQ_CLK_COUNTER_PAUSE_SFT			1
1819
#define IRQ_CLK_COUNTER_PAUSE_MASK_SFT			BIT(1)
1820
#define IRQ_CLK_COUNTER_ON_SFT				0
1821
#define IRQ_CLK_COUNTER_ON_MASK_SFT			BIT(0)
1822

1823
/* FPGA_CFG5 */
1824
#define WR_MSTR_ON_SFT					16
1825
#define WR_MSTR_ON_MASK_SFT				GENMASK(28, 16)
1826
#define WR_AG_SEL_SFT					0
1827
#define WR_AG_SEL_MASK_SFT				GENMASK(12, 0)
1828

1829
/* FPGA_CFG6 */
1830
#define WR_MSTR_REQ_REAL_SFT				16
1831
#define WR_MSTR_REQ_REAL_MASK_SFT			GENMASK(28, 16)
1832
#define WR_MSTR_REQ_IN_SFT				0
1833
#define WR_MSTR_REQ_IN_MASK_SFT				GENMASK(12, 0)
1834

1835
/* FPGA_CFG7 */
1836
#define MEM1_WDATA_MON0_SFT				0
1837
#define MEM1_WDATA_MON0_MASK_SFT			GENMASK(31, 0)
1838

1839
/* FPGA_CFG8 */
1840
#define MEM1_WDATA_MON1_SFT				0
1841
#define MEM1_WDATA_MON1_MASK_SFT			GENMASK(31, 0)
1842

1843
/* FPGA_CFG9 */
1844
#define MEM_WE_SFT					31
1845
#define MEM_WE_MASK_SFT					BIT(31)
1846
#define AFE_HREADY_SFT					30
1847
#define AFE_HREADY_MASK_SFT				BIT(30)
1848
#define MEM_WR_REQ_SFT					29
1849
#define MEM_WR_REQ_MASK_SFT				BIT(29)
1850
#define WR_AG_REG_MON_SFT				16
1851
#define WR_AG_REG_MON_MASK_SFT				GENMASK(28, 16)
1852
#define HCLK_CK_SFT					15
1853
#define HCLK_CK_MASK_SFT				BIT(15)
1854
#define MEM_RD_REQ_SFT					14
1855
#define MEM_RD_REQ_MASK_SFT				BIT(14)
1856
#define RD_AG_REQ_MON_SFT				0
1857
#define RD_AG_REQ_MON_MASK_SFT				GENMASK(13, 0)
1858

1859
/* FPGA_CFG10 */
1860
#define MEM_BYTE_0_SFT					0
1861
#define MEM_BYTE_0_MASK_SFT				GENMASK(31, 0)
1862

1863
/* FPGA_CFG11 */
1864
#define MEM_BYTE_1_SFT					0
1865
#define MEM_BYTE_1_MASK_SFT				GENMASK(31, 0)
1866

1867
/* FPGA_CFG12 */
1868
#define RDATA_CNT_SFT					30
1869
#define RDATA_CNT_MASK_SFT				GENMASK(31, 30)
1870
#define MS2_HREADY_SFT					29
1871
#define MS2_HREADY_MASK_SFT				BIT(29)
1872
#define MS1_HREADY_SFT					28
1873
#define MS1_HREADY_MASK_SFT				BIT(28)
1874
#define AG_SEL_SFT					0
1875
#define AG_SEL_MASK_SFT					GENMASK(25, 0)
1876

1877
/* FPGA_CFG13 */
1878
#define AFE_ST_SFT					27
1879
#define AFE_ST_MASK_SFT					GENMASK(31, 27)
1880
#define AG_IN_SERVICE_SFT				0
1881
#define AG_IN_SERVICE_MASK_SFT				GENMASK(25, 0)
1882

1883
/* ETDM_IN1_CON0 */
1884
#define ETDM_IN1_CON0_REG_ETDM_IN_EN_SFT			0
1885
#define ETDM_IN1_CON0_REG_ETDM_IN_EN_MASK_SFT			BIT(0)
1886
#define ETDM_IN1_CON0_REG_SYNC_MODE_SFT				1
1887
#define ETDM_IN1_CON0_REG_SYNC_MODE_MASK_SFT			BIT(1)
1888
#define ETDM_IN1_CON0_REG_LSB_FIRST_SFT				3
1889
#define ETDM_IN1_CON0_REG_LSB_FIRST_MASK_SFT			BIT(3)
1890
#define ETDM_IN1_CON0_REG_SOFT_RST_SFT				4
1891
#define ETDM_IN1_CON0_REG_SOFT_RST_MASK_SFT			BIT(4)
1892
#define ETDM_IN1_CON0_REG_SLAVE_MODE_SFT			5
1893
#define ETDM_IN1_CON0_REG_SLAVE_MODE_MASK_SFT			BIT(5)
1894
#define ETDM_IN1_CON0_REG_FMT_SFT				6
1895
#define ETDM_IN1_CON0_REG_FMT_MASK_SFT				GENMASK(8, 6)
1896
#define ETDM_IN1_CON0_REG_LRCK_EDGE_SEL_SFT			10
1897
#define ETDM_IN1_CON0_REG_LRCK_EDGE_SEL_MASK_SFT		BIT(10)
1898
#define ETDM_IN1_CON0_REG_BIT_LENGTH_SFT			11
1899
#define ETDM_IN1_CON0_REG_BIT_LENGTH_MASK_SFT			GENMASK(15, 11)
1900
#define ETDM_IN1_CON0_REG_WORD_LENGTH_SFT			16
1901
#define ETDM_IN1_CON0_REG_WORD_LENGTH_MASK_SFT			GENMASK(20, 16)
1902
#define ETDM_IN1_CON0_REG_CH_NUM_SFT				23
1903
#define ETDM_IN1_CON0_REG_CH_NUM_MASK_SFT			GENMASK(27, 23)
1904
#define ETDM_IN1_CON0_REG_RELATCH_1X_EN_SEL_DOMAIN_SFT		28
1905
#define ETDM_IN1_CON0_REG_RELATCH_1X_EN_SEL_DOMAIN_MASK_SFT	GENMASK(31, 28)
1906
#define ETDM_IN1_CON0_REG_VALID_TOGETHER_SFT			31
1907
#define ETDM_IN1_CON0_REG_VALID_TOGETHER_MASK_SFT		BIT(31)
1908
#define ETDM_IN_CON0_CTRL_MASK					0x1f9ff9e2
1909

1910
/* ETDM_IN1_CON1 */
1911
#define ETDM_IN1_CON1_REG_INITIAL_COUNT_SFT			0
1912
#define ETDM_IN1_CON1_REG_INITIAL_COUNT_MASK_SFT		GENMASK(4, 0)
1913
#define ETDM_IN1_CON1_REG_INITIAL_POINT_SFT			5
1914
#define ETDM_IN1_CON1_REG_INITIAL_POINT_MASK_SFT		GENMASK(9, 5)
1915
#define ETDM_IN1_CON1_REG_LRCK_AUTO_OFF_SFT			10
1916
#define ETDM_IN1_CON1_REG_LRCK_AUTO_OFF_MASK_SFT		BIT(10)
1917
#define ETDM_IN1_CON1_REG_BCK_AUTO_OFF_SFT			11
1918
#define ETDM_IN1_CON1_REG_BCK_AUTO_OFF_MASK_SFT			BIT(11)
1919
#define ETDM_IN1_CON1_REG_INITIAL_LRCK_SFT			13
1920
#define ETDM_IN1_CON1_REG_INITIAL_LRCK_MASK_SFT			BIT(13)
1921
#define ETDM_IN1_CON1_REG_LRCK_RESET_SFT			15
1922
#define ETDM_IN1_CON1_REG_LRCK_RESET_MASK_SFT			BIT(15)
1923
#define ETDM_IN1_CON1_PINMUX_MCLK_CTRL_OE_SFT			16
1924
#define ETDM_IN1_CON1_PINMUX_MCLK_CTRL_OE_MASK_SFT		BIT(16)
1925
#define ETDM_IN1_CON1_REG_OUTPUT_CR_EN_SFT			18
1926
#define ETDM_IN1_CON1_REG_OUTPUT_CR_EN_MASK_SFT			BIT(18)
1927
#define ETDM_IN1_CON1_REG_LR_ALIGN_SFT				19
1928
#define ETDM_IN1_CON1_REG_LR_ALIGN_MASK_SFT			BIT(19)
1929
#define ETDM_IN1_CON1_REG_LRCK_WIDTH_SFT			20
1930
#define ETDM_IN1_CON1_REG_LRCK_WIDTH_MASK_SFT			GENMASK(29, 20)
1931
#define ETDM_IN1_CON1_REG_DIRECT_INPUT_MASTER_BCK_SFT		30
1932
#define ETDM_IN1_CON1_REG_DIRECT_INPUT_MASTER_BCK_MASK_SFT	BIT(30)
1933
#define ETDM_IN1_CON1_REG_LRCK_AUTO_MODE_SFT			31
1934
#define ETDM_IN1_CON1_REG_LRCK_AUTO_MODE_MASK_SFT		BIT(31)
1935
#define ETDM_IN_CON1_CTRL_MASK					0xbff10000
1936

1937
/* ETDM_IN1_CON2 */
1938
#define ETDM_IN1_CON2_REG_UPDATE_POINT_SFT			0
1939
#define ETDM_IN1_CON2_REG_UPDATE_POINT_MASK_SFT			GENMASK(4, 0)
1940
#define ETDM_IN1_CON2_REG_UPDATE_GAP_SFT			5
1941
#define ETDM_IN1_CON2_REG_UPDATE_GAP_MASK_SFT			GENMASK(9, 5)
1942
#define ETDM_IN1_CON2_REG_CLOCK_SOURCE_SEL_SFT			10
1943
#define ETDM_IN1_CON2_REG_CLOCK_SOURCE_SEL_MASK_SFT		GENMASK(12, 10)
1944
#define ETDM_IN1_CON2_REG_AGENT_USE_ETDM_BCK_SFT		13
1945
#define ETDM_IN1_CON2_REG_AGENT_USE_ETDM_BCK_MASK_SFT		BIT(13)
1946
#define ETDM_IN1_CON2_REG_CK_EN_SEL_AUTO_SFT			14
1947
#define ETDM_IN1_CON2_REG_CK_EN_SEL_AUTO_MASK_SFT		BIT(14)
1948
#define ETDM_IN1_CON2_REG_MULTI_IP_ONE_DATA_CH_NUM_SFT		15
1949
#define ETDM_IN1_CON2_REG_MULTI_IP_ONE_DATA_CH_NUM_MASK_SFT	GENMASK(19, 15)
1950
#define ETDM_IN1_CON2_REG_MASK_AUTO_SFT				20
1951
#define ETDM_IN1_CON2_REG_MASK_AUTO_MASK_SFT			BIT(20)
1952
#define ETDM_IN1_CON2_REG_MASK_NUM_SFT				21
1953
#define ETDM_IN1_CON2_REG_MASK_NUM_MASK_SFT			GENMASK(25, 21)
1954
#define ETDM_IN1_CON2_REG_UPDATE_POINT_AUTO_SFT			26
1955
#define ETDM_IN1_CON2_REG_UPDATE_POINT_AUTO_MASK_SFT		BIT(26)
1956
#define ETDM_IN1_CON2_REG_SDATA_DELAY_0P5T_EN_SFT		27
1957
#define ETDM_IN1_CON2_REG_SDATA_DELAY_0P5T_EN_MASK_SFT		BIT(27)
1958
#define ETDM_IN1_CON2_REG_SDATA_DELAY_BCK_INV_SFT		28
1959
#define ETDM_IN1_CON2_REG_SDATA_DELAY_BCK_INV_MASK_SFT		BIT(28)
1960
#define ETDM_IN1_CON2_REG_LRCK_DELAY_0P5T_EN_SFT		29
1961
#define ETDM_IN1_CON2_REG_LRCK_DELAY_0P5T_EN_MASK_SFT		BIT(29)
1962
#define ETDM_IN1_CON2_REG_LRCK_DELAY_BCK_INV_SFT		30
1963
#define ETDM_IN1_CON2_REG_LRCK_DELAY_BCK_INV_MASK_SFT		BIT(30)
1964
#define ETDM_IN1_CON2_REG_MULTI_IP_MODE_SFT			31
1965
#define ETDM_IN1_CON2_REG_MULTI_IP_MODE_MASK_SFT		BIT(31)
1966
#define ETDM_IN_CON2_CTRL_MASK					0x800f8000
1967
#define ETDM_IN_CON2_MULTI_IP_CH(x)				(((x) - 1) << 15)
1968
#define ETDM_IN_CON2_MULTI_IP_2CH_MODE				BIT(31)
1969

1970
/* ETDM_IN1_CON3 */
1971
#define ETDM_IN1_CON3_REG_DISABLE_OUT_0_SFT			0
1972
#define ETDM_IN1_CON3_REG_DISABLE_OUT_0_MASK_SFT		BIT(0)
1973
#define ETDM_IN1_CON3_REG_DISABLE_OUT_1_SFT			1
1974
#define ETDM_IN1_CON3_REG_DISABLE_OUT_1_MASK_SFT		BIT(1)
1975
#define ETDM_IN1_CON3_REG_DISABLE_OUT_2_SFT			2
1976
#define ETDM_IN1_CON3_REG_DISABLE_OUT_2_MASK_SFT		BIT(2)
1977
#define ETDM_IN1_CON3_REG_DISABLE_OUT_3_SFT			3
1978
#define ETDM_IN1_CON3_REG_DISABLE_OUT_3_MASK_SFT		BIT(3)
1979
#define ETDM_IN1_CON3_REG_DISABLE_OUT_4_SFT			4
1980
#define ETDM_IN1_CON3_REG_DISABLE_OUT_4_MASK_SFT		BIT(4)
1981
#define ETDM_IN1_CON3_REG_DISABLE_OUT_5_SFT			5
1982
#define ETDM_IN1_CON3_REG_DISABLE_OUT_5_MASK_SFT		BIT(5)
1983
#define ETDM_IN1_CON3_REG_DISABLE_OUT_6_SFT			6
1984
#define ETDM_IN1_CON3_REG_DISABLE_OUT_6_MASK_SFT		BIT(6)
1985
#define ETDM_IN1_CON3_REG_DISABLE_OUT_7_SFT			7
1986
#define ETDM_IN1_CON3_REG_DISABLE_OUT_7_MASK_SFT		BIT(7)
1987
#define ETDM_IN1_CON3_REG_DISABLE_OUT_8_SFT			8
1988
#define ETDM_IN1_CON3_REG_DISABLE_OUT_8_MASK_SFT		BIT(8)
1989
#define ETDM_IN1_CON3_REG_DISABLE_OUT_9_SFT			9
1990
#define ETDM_IN1_CON3_REG_DISABLE_OUT_9_MASK_SFT		BIT(9)
1991
#define ETDM_IN1_CON3_REG_DISABLE_OUT_10_SFT			10
1992
#define ETDM_IN1_CON3_REG_DISABLE_OUT_10_MASK_SFT		BIT(10)
1993
#define ETDM_IN1_CON3_REG_DISABLE_OUT_11_SFT			11
1994
#define ETDM_IN1_CON3_REG_DISABLE_OUT_11_MASK_SFT		BIT(11)
1995
#define ETDM_IN1_CON3_REG_DISABLE_OUT_12_SFT			12
1996
#define ETDM_IN1_CON3_REG_DISABLE_OUT_12_MASK_SFT		BIT(12)
1997
#define ETDM_IN1_CON3_REG_DISABLE_OUT_13_SFT			13
1998
#define ETDM_IN1_CON3_REG_DISABLE_OUT_13_MASK_SFT		BIT(13)
1999
#define ETDM_IN1_CON3_REG_DISABLE_OUT_14_SFT			14
2000
#define ETDM_IN1_CON3_REG_DISABLE_OUT_14_MASK_SFT		BIT(14)
2001
#define ETDM_IN1_CON3_REG_DISABLE_OUT_15_SFT			15
2002
#define ETDM_IN1_CON3_REG_DISABLE_OUT_15_MASK_SFT		BIT(15)
2003
#define ETDM_IN1_CON3_REG_RJ_DATA_RIGHT_ALIGN_SFT		16
2004
#define ETDM_IN1_CON3_REG_RJ_DATA_RIGHT_ALIGN_MASK_SFT		BIT(16)
2005
#define ETDM_IN1_CON3_REG_MONITOR_SEL_SFT			17
2006
#define ETDM_IN1_CON3_REG_MONITOR_SEL_MASK_SFT			GENMASK(18, 17)
2007
#define ETDM_IN1_CON3_REG_CNT_UPPER_LIMIT_SFT			19
2008
#define ETDM_IN1_CON3_REG_CNT_UPPER_LIMIT_MASK_SFT		GENMASK(24, 19)
2009
#define ETDM_IN1_CON3_REG_COMPACT_SAMPLE_END_DIS_SFT		25
2010
#define ETDM_IN1_CON3_REG_COMPACT_SAMPLE_END_DIS_MASK_SFT	BIT(25)
2011
#define ETDM_IN1_CON3_REG_FS_TIMING_SEL_SFT			26
2012
#define ETDM_IN1_CON3_REG_FS_TIMING_SEL_MASK_SFT		GENMASK(30, 26)
2013
#define ETDM_IN1_CON3_REG_SAMPLE_END_MODE_SFT			31
2014
#define ETDM_IN1_CON3_REG_SAMPLE_END_MODE_MASK_SFT		BIT(31)
2015
#define ETDM_IN_CON3_CTRL_MASK					(0x7c000000)
2016
#define ETDM_IN_CON3_FS(x)					(((x) & 0x1f) << 26)
2017

2018
/* ETDM_IN1_CON4 */
2019
#define ETDM_IN1_CON4_REG_DSD_MODE_SFT				0
2020
#define ETDM_IN1_CON4_REG_DSD_MODE_MASK_SFT			GENMASK(5, 0)
2021
#define ETDM_IN1_CON4_REG_DSD_REPACK_AUTO_MODE_SFT		8
2022
#define ETDM_IN1_CON4_REG_DSD_REPACK_AUTO_MODE_MASK_SFT		BIT(8)
2023
#define ETDM_IN1_CON4_REG_REPACK_WORD_LENGTH_SFT		9
2024
#define ETDM_IN1_CON4_REG_REPACK_WORD_LENGTH_MASK_SFT		GENMASK(10, 9)
2025
#define ETDM_IN1_CON4_REG_ASYNC_RESET_SFT			11
2026
#define ETDM_IN1_CON4_REG_ASYNC_RESET_MASK_SFT			BIT(11)
2027
#define ETDM_IN1_CON4_REG_DSD_CHNUM_SFT				12
2028
#define ETDM_IN1_CON4_REG_DSD_CHNUM_MASK_SFT			GENMASK(15, 12)
2029
#define ETDM_IN1_CON4_REG_SLAVE_BCK_INV_SFT			16
2030
#define ETDM_IN1_CON4_REG_SLAVE_BCK_INV_MASK_SFT		BIT(16)
2031
#define ETDM_IN1_CON4_REG_SLAVE_LRCK_INV_SFT			17
2032
#define ETDM_IN1_CON4_REG_SLAVE_LRCK_INV_MASK_SFT		BIT(17)
2033
#define ETDM_IN1_CON4_REG_MASTER_BCK_INV_SFT			18
2034
#define ETDM_IN1_CON4_REG_MASTER_BCK_INV_MASK_SFT		BIT(18)
2035
#define ETDM_IN1_CON4_REG_MASTER_LRCK_INV_SFT			19
2036
#define ETDM_IN1_CON4_REG_MASTER_LRCK_INV_MASK_SFT		BIT(19)
2037
#define ETDM_IN1_CON4_REG_RELATCH_1X_EN_SEL_SFT			20
2038
#define ETDM_IN1_CON4_REG_RELATCH_1X_EN_SEL_MASK_SFT		GENMASK(24, 20)
2039
#define ETDM_IN1_CON4_REG_SAMPLE_END_POINT_SFT			25
2040
#define ETDM_IN1_CON4_REG_SAMPLE_END_POINT_MASK_SFT		GENMASK(29, 25)
2041
#define ETDM_IN1_CON4_REG_WAIT_LAST_SAMPLE_SFT			30
2042
#define ETDM_IN1_CON4_REG_WAIT_LAST_SAMPLE_MASK_SFT		BIT(30)
2043
#define ETDM_IN1_CON4_REG_MASTER_BCK_FORCE_ON_SFT		31
2044
#define ETDM_IN1_CON4_REG_MASTER_BCK_FORCE_ON_MASK_SFT		BIT(31)
2045
#define ETDM_IN_CON4_CTRL_MASK					0x1ff0000
2046
#define ETDM_IN_CON4_FS(x)					(((x) & 0x1f) << 20)
2047
#define ETDM_IN_CON4_CON0_MASTER_LRCK_INV			BIT(19)
2048
#define ETDM_IN_CON4_CON0_MASTER_BCK_INV			BIT(18)
2049
#define ETDM_IN_CON4_CON0_SLAVE_LRCK_INV			BIT(17)
2050
#define ETDM_IN_CON4_CON0_SLAVE_BCK_INV				BIT(16)
2051

2052
/* ETDM_IN1_CON5 */
2053
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_0_SFT			0
2054
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_0_MASK_SFT		BIT(0)
2055
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_1_SFT			1
2056
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_1_MASK_SFT		BIT(1)
2057
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_2_SFT			2
2058
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_2_MASK_SFT		BIT(2)
2059
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_3_SFT			3
2060
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_3_MASK_SFT		BIT(3)
2061
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_4_SFT			4
2062
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_4_MASK_SFT		BIT(4)
2063
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_5_SFT			5
2064
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_5_MASK_SFT		BIT(5)
2065
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_6_SFT			6
2066
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_6_MASK_SFT		BIT(6)
2067
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_7_SFT			7
2068
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_7_MASK_SFT		BIT(7)
2069
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_8_SFT			8
2070
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_8_MASK_SFT		BIT(8)
2071
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_9_SFT			9
2072
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_9_MASK_SFT		BIT(9)
2073
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_10_SFT			10
2074
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_10_MASK_SFT		BIT(10)
2075
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_11_SFT			11
2076
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_11_MASK_SFT		BIT(11)
2077
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_12_SFT			12
2078
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_12_MASK_SFT		BIT(12)
2079
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_13_SFT			13
2080
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_13_MASK_SFT		BIT(13)
2081
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_14_SFT			14
2082
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_14_MASK_SFT		BIT(14)
2083
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_15_SFT			15
2084
#define ETDM_IN1_CON5_REG_ODD_FLAG_EN_15_MASK_SFT		BIT(15)
2085
#define ETDM_IN1_CON5_REG_LR_SWAP_0_SFT				16
2086
#define ETDM_IN1_CON5_REG_LR_SWAP_0_MASK_SFT			BIT(16)
2087
#define ETDM_IN1_CON5_REG_LR_SWAP_1_SFT				17
2088
#define ETDM_IN1_CON5_REG_LR_SWAP_1_MASK_SFT			BIT(17)
2089
#define ETDM_IN1_CON5_REG_LR_SWAP_2_SFT				18
2090
#define ETDM_IN1_CON5_REG_LR_SWAP_2_MASK_SFT			BIT(18)
2091
#define ETDM_IN1_CON5_REG_LR_SWAP_3_SFT				19
2092
#define ETDM_IN1_CON5_REG_LR_SWAP_3_MASK_SFT			BIT(19)
2093
#define ETDM_IN1_CON5_REG_LR_SWAP_4_SFT				20
2094
#define ETDM_IN1_CON5_REG_LR_SWAP_4_MASK_SFT			BIT(20)
2095
#define ETDM_IN1_CON5_REG_LR_SWAP_5_SFT				21
2096
#define ETDM_IN1_CON5_REG_LR_SWAP_5_MASK_SFT			BIT(21)
2097
#define ETDM_IN1_CON5_REG_LR_SWAP_6_SFT				22
2098
#define ETDM_IN1_CON5_REG_LR_SWAP_6_MASK_SFT			BIT(22)
2099
#define ETDM_IN1_CON5_REG_LR_SWAP_7_SFT				23
2100
#define ETDM_IN1_CON5_REG_LR_SWAP_7_MASK_SFT			BIT(23)
2101
#define ETDM_IN1_CON5_REG_LR_SWAP_8_SFT				24
2102
#define ETDM_IN1_CON5_REG_LR_SWAP_8_MASK_SFT			BIT(24)
2103
#define ETDM_IN1_CON5_REG_LR_SWAP_9_SFT				25
2104
#define ETDM_IN1_CON5_REG_LR_SWAP_9_MASK_SFT			BIT(25)
2105
#define ETDM_IN1_CON5_REG_LR_SWAP_10_SFT			26
2106
#define ETDM_IN1_CON5_REG_LR_SWAP_10_MASK_SFT			BIT(26)
2107
#define ETDM_IN1_CON5_REG_LR_SWAP_11_SFT			27
2108
#define ETDM_IN1_CON5_REG_LR_SWAP_11_MASK_SFT			BIT(27)
2109
#define ETDM_IN1_CON5_REG_LR_SWAP_12_SFT			28
2110
#define ETDM_IN1_CON5_REG_LR_SWAP_12_MASK_SFT			BIT(28)
2111
#define ETDM_IN1_CON5_REG_LR_SWAP_13_SFT			29
2112
#define ETDM_IN1_CON5_REG_LR_SWAP_13_MASK_SFT			BIT(29)
2113
#define ETDM_IN1_CON5_REG_LR_SWAP_14_SFT			30
2114
#define ETDM_IN1_CON5_REG_LR_SWAP_14_MASK_SFT			BIT(30)
2115
#define ETDM_IN1_CON5_REG_LR_SWAP_15_SFT			31
2116
#define ETDM_IN1_CON5_REG_LR_SWAP_15_MASK_SFT			BIT(31)
2117

2118
/* ETDM_IN1_CON6 */
2119
#define ETDM_IN1_CON6_LCH_DATA_REG_SFT				0
2120
#define ETDM_IN1_CON6_LCH_DATA_REG_MASK_SFT			GENMASK(31, 0)
2121

2122
/* ETDM_IN1_CON7 */
2123
#define ETDM_IN1_CON7_RCH_DATA_REG_SFT				0
2124
#define ETDM_IN1_CON7_RCH_DATA_REG_MASK_SFT			GENMASK(31, 0)
2125

2126
/* ETDM_IN1_CON8 */
2127
#define ETDM_IN1_CON8_REG_AFIFO_THRESHOLD_SFT			29
2128
#define ETDM_IN1_CON8_REG_AFIFO_THRESHOLD_MASK_SFT		GENMASK(30, 29)
2129
#define ETDM_IN1_CON8_REG_CK_EN_SEL_MANUAL_SFT			16
2130
#define ETDM_IN1_CON8_REG_CK_EN_SEL_MANUAL_MASK_SFT		GENMASK(25, 16)
2131
#define ETDM_IN1_CON8_REG_AFIFO_SW_RESET_SFT			15
2132
#define ETDM_IN1_CON8_REG_AFIFO_SW_RESET_MASK_SFT		BIT(15)
2133
#define ETDM_IN1_CON8_REG_AFIFO_RESET_SEL_SFT			14
2134
#define ETDM_IN1_CON8_REG_AFIFO_RESET_SEL_MASK_SFT		BIT(14)
2135
#define ETDM_IN1_CON8_REG_AFIFO_AUTO_RESET_DIS_SFT		9
2136
#define ETDM_IN1_CON8_REG_AFIFO_AUTO_RESET_DIS_MASK_SFT		BIT(9)
2137
#define ETDM_IN1_CON8_REG_ETDM_USE_AFIFO_SFT			8
2138
#define ETDM_IN1_CON8_REG_ETDM_USE_AFIFO_MASK_SFT		BIT(8)
2139
#define ETDM_IN1_CON8_REG_AFIFO_CLOCK_DOMAIN_SEL_SFT		5
2140
#define ETDM_IN1_CON8_REG_AFIFO_CLOCK_DOMAIN_SEL_MASK_SFT	GENMASK(7, 5)
2141
#define ETDM_IN1_CON8_REG_AFIFO_MODE_SFT			0
2142
#define ETDM_IN1_CON8_REG_AFIFO_MODE_MASK_SFT			GENMASK(4, 0)
2143
#define ETDM_IN_CON8_FS(x)					(((x) & 0x1f) << 0)
2144
#define ETDM_IN_CON8_CTRL_MASK					0x13f
2145

2146
#define AUDIO_TOP_CON0					0x0000
2147
#define AUDIO_TOP_CON1					0x0004
2148
#define AUDIO_TOP_CON2					0x0008
2149
#define AUDIO_TOP_CON3					0x000c
2150
#define AFE_DAC_CON0					0x0010
2151
#define AFE_I2S_CON					0x0018
2152
#define AFE_CONN0					0x0020
2153
#define AFE_CONN1					0x0024
2154
#define AFE_CONN2					0x0028
2155
#define AFE_CONN3					0x002c
2156
#define AFE_CONN4					0x0030
2157
#define AFE_I2S_CON1					0x0034
2158
#define AFE_I2S_CON2					0x0038
2159
#define AFE_I2S_CON3					0x0040
2160
#define AFE_CONN5					0x0044
2161
#define AFE_CONN_24BIT					0x0048
2162
#define AFE_DL1_CON0					0x004c
2163
#define AFE_DL1_BASE_MSB				0x0050
2164
#define AFE_DL1_BASE					0x0054
2165
#define AFE_DL1_CUR_MSB					0x0058
2166
#define AFE_DL1_CUR					0x005c
2167
#define AFE_DL1_END_MSB					0x0060
2168
#define AFE_DL1_END					0x0064
2169
#define AFE_DL2_CON0					0x0068
2170
#define AFE_DL2_BASE_MSB				0x006c
2171
#define AFE_DL2_BASE					0x0070
2172
#define AFE_DL2_CUR_MSB					0x0074
2173
#define AFE_DL2_CUR					0x0078
2174
#define AFE_DL2_END_MSB					0x007c
2175
#define AFE_DL2_END					0x0080
2176
#define AFE_DL3_CON0					0x0084
2177
#define AFE_DL3_BASE_MSB				0x0088
2178
#define AFE_DL3_BASE					0x008c
2179
#define AFE_DL3_CUR_MSB					0x0090
2180
#define AFE_DL3_CUR					0x0094
2181
#define AFE_DL3_END_MSB					0x0098
2182
#define AFE_DL3_END					0x009c
2183
#define AFE_CONN6					0x00bc
2184
#define AFE_DL4_CON0					0x00cc
2185
#define AFE_DL4_BASE_MSB				0x00d0
2186
#define AFE_DL4_BASE					0x00d4
2187
#define AFE_DL4_CUR_MSB					0x00d8
2188
#define AFE_DL4_CUR					0x00dc
2189
#define AFE_DL4_END_MSB					0x00e0
2190
#define AFE_DL4_END					0x00e4
2191
#define AFE_DL12_CON0					0x00e8
2192
#define AFE_DL12_BASE_MSB				0x00ec
2193
#define AFE_DL12_BASE					0x00f0
2194
#define AFE_DL12_CUR_MSB				0x00f4
2195
#define AFE_DL12_CUR					0x00f8
2196
#define AFE_DL12_END_MSB				0x00fc
2197
#define AFE_DL12_END					0x0100
2198
#define AFE_ADDA_DL_SRC2_CON0				0x0108
2199
#define AFE_ADDA_DL_SRC2_CON1				0x010c
2200
#define AFE_ADDA_UL_SRC_CON0				0x0114
2201
#define AFE_ADDA_UL_SRC_CON1				0x0118
2202
#define AFE_ADDA_TOP_CON0				0x0120
2203
#define AFE_ADDA_UL_DL_CON0				0x0124
2204
#define AFE_ADDA_SRC_DEBUG				0x012c
2205
#define AFE_ADDA_SRC_DEBUG_MON0				0x0130
2206
#define AFE_ADDA_SRC_DEBUG_MON1				0x0134
2207
#define AFE_ADDA_UL_SRC_MON0				0x0148
2208
#define AFE_ADDA_UL_SRC_MON1				0x014c
2209
#define AFE_SECURE_CON0					0x0150
2210
#define AFE_SRAM_BOUND					0x0154
2211
#define AFE_SECURE_CON1					0x0158
2212
#define AFE_SECURE_CONN0				0x015c
2213
#define AFE_VUL_CON0					0x0170
2214
#define AFE_VUL_BASE_MSB				0x0174
2215
#define AFE_VUL_BASE					0x0178
2216
#define AFE_VUL_CUR_MSB					0x017c
2217
#define AFE_VUL_CUR					0x0180
2218
#define AFE_VUL_END_MSB					0x0184
2219
#define AFE_VUL_END					0x0188
2220
#define AFE_SIDETONE_DEBUG				0x01d0
2221
#define AFE_SIDETONE_MON				0x01d4
2222
#define AFE_SINEGEN_CON2				0x01dc
2223
#define AFE_SIDETONE_CON0				0x01e0
2224
#define AFE_SIDETONE_COEFF				0x01e4
2225
#define AFE_SIDETONE_CON1				0x01e8
2226
#define AFE_SIDETONE_GAIN				0x01ec
2227
#define AFE_SINEGEN_CON0				0x01f0
2228
#define AFE_TOP_CON0					0x0200
2229
#define AFE_VUL2_CON0					0x020c
2230
#define AFE_VUL2_BASE_MSB				0x0210
2231
#define AFE_VUL2_BASE					0x0214
2232
#define AFE_VUL2_CUR_MSB				0x0218
2233
#define AFE_VUL2_CUR					0x021c
2234
#define AFE_VUL2_END_MSB				0x0220
2235
#define AFE_VUL2_END					0x0224
2236
#define AFE_VUL3_CON0					0x0228
2237
#define AFE_VUL3_BASE_MSB				0x022c
2238
#define AFE_VUL3_BASE					0x0230
2239
#define AFE_VUL3_CUR_MSB				0x0234
2240
#define AFE_VUL3_CUR					0x0238
2241
#define AFE_VUL3_END_MSB				0x023c
2242
#define AFE_VUL3_END					0x0240
2243
#define AFE_BUSY					0x0244
2244
#define AFE_BUS_CFG					0x0250
2245
#define AFE_ADDA_PREDIS_CON0				0x0260
2246
#define AFE_ADDA_PREDIS_CON1				0x0264
2247
#define AFE_I2S_MON					0x027c
2248
#define AFE_ADDA_IIR_COEF_02_01				0x0290
2249
#define AFE_ADDA_IIR_COEF_04_03				0x0294
2250
#define AFE_ADDA_IIR_COEF_06_05				0x0298
2251
#define AFE_ADDA_IIR_COEF_08_07				0x029c
2252
#define AFE_ADDA_IIR_COEF_10_09				0x02a0
2253
#define AFE_IRQ_MCU_CON1				0x02e4
2254
#define AFE_IRQ_MCU_CON2				0x02e8
2255
#define AFE_DAC_MON					0x02ec
2256
#define AFE_IRQ_MCU_CON3				0x02f0
2257
#define AFE_IRQ_MCU_CON4				0x02f4
2258
#define AFE_IRQ_MCU_CNT0				0x0300
2259
#define AFE_IRQ_MCU_CNT6				0x0304
2260
#define AFE_IRQ_MCU_CNT8				0x0308
2261
#define AFE_IRQ_MCU_DSP2_EN				0x030c
2262
#define AFE_IRQ0_MCU_CNT_MON				0x0310
2263
#define AFE_IRQ6_MCU_CNT_MON				0x0314
2264
#define AFE_VUL4_CON0					0x0358
2265
#define AFE_VUL4_BASE_MSB				0x035c
2266
#define AFE_VUL4_BASE					0x0360
2267
#define AFE_VUL4_CUR_MSB				0x0364
2268
#define AFE_VUL4_CUR					0x0368
2269
#define AFE_VUL4_END_MSB				0x036c
2270
#define AFE_VUL4_END					0x0370
2271
#define AFE_VUL12_CON0					0x0374
2272
#define AFE_VUL12_BASE_MSB				0x0378
2273
#define AFE_VUL12_BASE					0x037c
2274
#define AFE_VUL12_CUR_MSB				0x0380
2275
#define AFE_VUL12_CUR					0x0384
2276
#define AFE_VUL12_END_MSB				0x0388
2277
#define AFE_VUL12_END					0x038c
2278
#define AFE_IRQ3_MCU_CNT_MON				0x0398
2279
#define AFE_IRQ4_MCU_CNT_MON				0x039c
2280
#define AFE_IRQ_MCU_CON0				0x03a0
2281
#define AFE_IRQ_MCU_STATUS				0x03a4
2282
#define AFE_IRQ_MCU_CLR					0x03a8
2283
#define AFE_IRQ_MCU_CNT1				0x03ac
2284
#define AFE_IRQ_MCU_CNT2				0x03b0
2285
#define AFE_IRQ_MCU_EN					0x03b4
2286
#define AFE_IRQ_MCU_MON2				0x03b8
2287
#define AFE_IRQ_MCU_CNT5				0x03bc
2288
#define AFE_IRQ1_MCU_CNT_MON				0x03c0
2289
#define AFE_IRQ2_MCU_CNT_MON				0x03c4
2290
#define AFE_IRQ5_MCU_CNT_MON				0x03cc
2291
#define AFE_IRQ_MCU_DSP_EN				0x03d0
2292
#define AFE_IRQ_MCU_SCP_EN				0x03d4
2293
#define AFE_IRQ_MCU_CNT7				0x03dc
2294
#define AFE_IRQ7_MCU_CNT_MON				0x03e0
2295
#define AFE_IRQ_MCU_CNT3				0x03e4
2296
#define AFE_IRQ_MCU_CNT4				0x03e8
2297
#define AFE_IRQ_MCU_CNT11				0x03ec
2298
#define AFE_APLL1_TUNER_CFG				0x03f0
2299
#define AFE_APLL2_TUNER_CFG				0x03f4
2300
#define AFE_IRQ_MCU_MISS_CLR				0x03f8
2301
#define AFE_CONN33					0x0408
2302
#define AFE_IRQ_MCU_CNT12				0x040c
2303
#define AFE_GAIN1_CON0					0x0410
2304
#define AFE_GAIN1_CON1					0x0414
2305
#define AFE_GAIN1_CON2					0x0418
2306
#define AFE_GAIN1_CON3					0x041c
2307
#define AFE_CONN7					0x0420
2308
#define AFE_GAIN1_CUR					0x0424
2309
#define AFE_GAIN2_CON0					0x0428
2310
#define AFE_GAIN2_CON1					0x042c
2311
#define AFE_GAIN2_CON2					0x0430
2312
#define AFE_GAIN2_CON3					0x0434
2313
#define AFE_CONN8					0x0438
2314
#define AFE_GAIN2_CUR					0x043c
2315
#define AFE_CONN9					0x0440
2316
#define AFE_CONN10					0x0444
2317
#define AFE_CONN11					0x0448
2318
#define AFE_CONN12					0x044c
2319
#define AFE_CONN13					0x0450
2320
#define AFE_CONN14					0x0454
2321
#define AFE_CONN15					0x0458
2322
#define AFE_CONN16					0x045c
2323
#define AFE_CONN17					0x0460
2324
#define AFE_CONN18					0x0464
2325
#define AFE_CONN19					0x0468
2326
#define AFE_CONN20					0x046c
2327
#define AFE_CONN21					0x0470
2328
#define AFE_CONN22					0x0474
2329
#define AFE_CONN23					0x0478
2330
#define AFE_CONN24					0x047c
2331
#define AFE_CONN_RS					0x0494
2332
#define AFE_CONN_DI					0x0498
2333
#define AFE_CONN25					0x04b0
2334
#define AFE_CONN26					0x04b4
2335
#define AFE_CONN27					0x04b8
2336
#define AFE_CONN28					0x04bc
2337
#define AFE_CONN29					0x04c0
2338
#define AFE_CONN30					0x04c4
2339
#define AFE_CONN31					0x04c8
2340
#define AFE_CONN32					0x04cc
2341
#define AFE_SRAM_DELSEL_CON1				0x04f4
2342
#define AFE_CONN56					0x0500
2343
#define AFE_CONN57					0x0504
2344
#define AFE_CONN58					0x0508
2345
#define AFE_CONN59					0x050c
2346
#define AFE_CONN56_1					0x0510
2347
#define AFE_CONN57_1					0x0514
2348
#define AFE_CONN58_1					0x0518
2349
#define AFE_CONN59_1					0x051c
2350
#define PCM_INTF_CON1					0x0530
2351
#define PCM_INTF_CON2					0x0538
2352
#define PCM2_INTF_CON					0x053c
2353
#define AFE_CM1_CON					0x0550
2354
#define AFE_CONN34					0x0580
2355
#define FPGA_CFG0					0x05b0
2356
#define FPGA_CFG1					0x05b4
2357
#define FPGA_CFG2					0x05c0
2358
#define FPGA_CFG3					0x05c4
2359
#define AUDIO_TOP_DBG_CON				0x05c8
2360
#define AUDIO_TOP_DBG_MON0				0x05cc
2361
#define AUDIO_TOP_DBG_MON1				0x05d0
2362
#define AFE_IRQ8_MCU_CNT_MON				0x05e4
2363
#define AFE_IRQ11_MCU_CNT_MON				0x05e8
2364
#define AFE_IRQ12_MCU_CNT_MON				0x05ec
2365
#define AFE_IRQ_MCU_CNT9				0x0600
2366
#define AFE_IRQ_MCU_CNT10				0x0604
2367
#define AFE_IRQ_MCU_CNT13				0x0608
2368
#define AFE_IRQ_MCU_CNT14				0x060c
2369
#define AFE_IRQ_MCU_CNT15				0x0610
2370
#define AFE_IRQ_MCU_CNT16				0x0614
2371
#define AFE_IRQ_MCU_CNT17				0x0618
2372
#define AFE_IRQ_MCU_CNT18				0x061c
2373
#define AFE_IRQ_MCU_CNT19				0x0620
2374
#define AFE_IRQ_MCU_CNT20				0x0624
2375
#define AFE_IRQ_MCU_CNT21				0x0628
2376
#define AFE_IRQ_MCU_CNT22				0x062c
2377
#define AFE_IRQ_MCU_CNT23				0x0630
2378
#define AFE_IRQ_MCU_CNT24				0x0634
2379
#define AFE_IRQ_MCU_CNT25				0x0638
2380
#define AFE_IRQ_MCU_CNT26				0x063c
2381
#define AFE_IRQ9_MCU_CNT_MON				0x0660
2382
#define AFE_IRQ10_MCU_CNT_MON				0x0664
2383
#define AFE_IRQ13_MCU_CNT_MON				0x0668
2384
#define AFE_IRQ14_MCU_CNT_MON				0x066c
2385
#define AFE_IRQ15_MCU_CNT_MON				0x0670
2386
#define AFE_IRQ16_MCU_CNT_MON				0x0674
2387
#define AFE_IRQ17_MCU_CNT_MON				0x0678
2388
#define AFE_IRQ18_MCU_CNT_MON				0x067c
2389
#define AFE_IRQ19_MCU_CNT_MON				0x0680
2390
#define AFE_IRQ20_MCU_CNT_MON				0x0684
2391
#define AFE_IRQ21_MCU_CNT_MON				0x0688
2392
#define AFE_IRQ22_MCU_CNT_MON				0x068c
2393
#define AFE_IRQ23_MCU_CNT_MON				0x0690
2394
#define AFE_IRQ24_MCU_CNT_MON				0x0694
2395
#define AFE_IRQ25_MCU_CNT_MON				0x0698
2396
#define AFE_IRQ26_MCU_CNT_MON				0x069c
2397
#define AFE_IRQ31_MCU_CNT_MON				0x06a0
2398
#define AFE_GENERAL_REG0				0x0800
2399
#define AFE_GENERAL_REG1				0x0804
2400
#define AFE_GENERAL_REG2				0x0808
2401
#define AFE_GENERAL_REG3				0x080c
2402
#define AFE_GENERAL_REG4				0x0810
2403
#define AFE_GENERAL_REG5				0x0814
2404
#define AFE_GENERAL_REG6				0x0818
2405
#define AFE_GENERAL_REG7				0x081c
2406
#define AFE_GENERAL_REG8				0x0820
2407
#define AFE_GENERAL_REG9				0x0824
2408
#define AFE_GENERAL_REG10				0x0828
2409
#define AFE_GENERAL_REG11				0x082c
2410
#define AFE_GENERAL_REG12				0x0830
2411
#define AFE_GENERAL_REG13				0x0834
2412
#define AFE_GENERAL_REG14				0x0838
2413
#define AFE_GENERAL_REG15				0x083c
2414
#define AFE_CBIP_CFG0					0x0840
2415
#define AFE_CBIP_MON0					0x0844
2416
#define AFE_CBIP_SLV_MUX_MON0				0x0848
2417
#define AFE_CBIP_SLV_DECODER_MON0			0x084c
2418
#define AFE_ADDA6_MTKAIF_MON0				0x0854
2419
#define AFE_ADDA6_MTKAIF_MON1				0x0858
2420
#define AFE_AWB_CON0					0x085c
2421
#define AFE_AWB_BASE_MSB				0x0860
2422
#define AFE_AWB_BASE					0x0864
2423
#define AFE_AWB_CUR_MSB					0x0868
2424
#define AFE_AWB_CUR					0x086c
2425
#define AFE_AWB_END_MSB					0x0870
2426
#define AFE_AWB_END					0x0874
2427
#define AFE_AWB2_CON0					0x0878
2428
#define AFE_AWB2_BASE_MSB				0x087c
2429
#define AFE_AWB2_BASE					0x0880
2430
#define AFE_AWB2_CUR_MSB				0x0884
2431
#define AFE_AWB2_CUR					0x0888
2432
#define AFE_AWB2_END_MSB				0x088c
2433
#define AFE_AWB2_END					0x0890
2434
#define AFE_DAI_CON0					0x0894
2435
#define AFE_DAI_BASE_MSB				0x0898
2436
#define AFE_DAI_BASE					0x089c
2437
#define AFE_DAI_CUR_MSB					0x08a0
2438
#define AFE_DAI_CUR					0x08a4
2439
#define AFE_DAI_END_MSB					0x08a8
2440
#define AFE_DAI_END					0x08ac
2441
#define AFE_DAI2_CON0					0x08b0
2442
#define AFE_DAI2_BASE_MSB				0x08b4
2443
#define AFE_DAI2_BASE					0x08b8
2444
#define AFE_DAI2_CUR_MSB				0x08bc
2445
#define AFE_DAI2_CUR					0x08c0
2446
#define AFE_DAI2_END_MSB				0x08c4
2447
#define AFE_DAI2_END					0x08c8
2448
#define AFE_MEMIF_CON0					0x08cc
2449
#define AFE_CONN0_1					0x0900
2450
#define AFE_CONN1_1					0x0904
2451
#define AFE_CONN2_1					0x0908
2452
#define AFE_CONN3_1					0x090c
2453
#define AFE_CONN4_1					0x0910
2454
#define AFE_CONN5_1					0x0914
2455
#define AFE_CONN6_1					0x0918
2456
#define AFE_CONN7_1					0x091c
2457
#define AFE_CONN8_1					0x0920
2458
#define AFE_CONN9_1					0x0924
2459
#define AFE_CONN10_1					0x0928
2460
#define AFE_CONN11_1					0x092c
2461
#define AFE_CONN12_1					0x0930
2462
#define AFE_CONN13_1					0x0934
2463
#define AFE_CONN14_1					0x0938
2464
#define AFE_CONN15_1					0x093c
2465
#define AFE_CONN16_1					0x0940
2466
#define AFE_CONN17_1					0x0944
2467
#define AFE_CONN18_1					0x0948
2468
#define AFE_CONN19_1					0x094c
2469
#define AFE_CONN20_1					0x0950
2470
#define AFE_CONN21_1					0x0954
2471
#define AFE_CONN22_1					0x0958
2472
#define AFE_CONN23_1					0x095c
2473
#define AFE_CONN24_1					0x0960
2474
#define AFE_CONN25_1					0x0964
2475
#define AFE_CONN26_1					0x0968
2476
#define AFE_CONN27_1					0x096c
2477
#define AFE_CONN28_1					0x0970
2478
#define AFE_CONN29_1					0x0974
2479
#define AFE_CONN30_1					0x0978
2480
#define AFE_CONN31_1					0x097c
2481
#define AFE_CONN32_1					0x0980
2482
#define AFE_CONN33_1					0x0984
2483
#define AFE_CONN34_1					0x0988
2484
#define AFE_CONN_RS_1					0x098c
2485
#define AFE_CONN_DI_1					0x0990
2486
#define AFE_CONN_24BIT_1				0x0994
2487
#define AFE_CONN_REG					0x0998
2488
#define AFE_CONN35					0x09a0
2489
#define AFE_CONN36					0x09a4
2490
#define AFE_CONN37					0x09a8
2491
#define AFE_CONN38					0x09ac
2492
#define AFE_CONN35_1					0x09b0
2493
#define AFE_CONN36_1					0x09b4
2494
#define AFE_CONN37_1					0x09b8
2495
#define AFE_CONN38_1					0x09bc
2496
#define AFE_CONN39					0x09c0
2497
#define AFE_CONN40					0x09c4
2498
#define AFE_CONN41					0x09c8
2499
#define AFE_CONN42					0x09cc
2500
#define AFE_CONN39_1					0x09e0
2501
#define AFE_CONN40_1					0x09e4
2502
#define AFE_CONN41_1					0x09e8
2503
#define AFE_CONN42_1					0x09ec
2504
#define AFE_I2S_CON4					0x09f8
2505
#define AFE_CONN60					0x0a64
2506
#define AFE_CONN61					0x0a68
2507
#define AFE_CONN62					0x0a6c
2508
#define AFE_CONN63					0x0a70
2509
#define AFE_CONN64					0x0a74
2510
#define AFE_CONN65					0x0a78
2511
#define AFE_CONN66					0x0a7c
2512
#define AFE_ADDA6_TOP_CON0				0x0a80
2513
#define AFE_ADDA6_UL_SRC_CON0				0x0a84
2514
#define AFE_ADDA6_UL_SRC_CON1				0x0a88
2515
#define AFE_ADDA6_SRC_DEBUG				0x0a8c
2516
#define AFE_ADDA6_SRC_DEBUG_MON0			0x0a90
2517
#define AFE_ADDA6_ULCF_CFG_02_01			0x0aa0
2518
#define AFE_ADDA6_ULCF_CFG_04_03			0x0aa4
2519
#define AFE_ADDA6_ULCF_CFG_06_05			0x0aa8
2520
#define AFE_ADDA6_ULCF_CFG_08_07			0x0aac
2521
#define AFE_ADDA6_ULCF_CFG_10_09			0x0ab0
2522
#define AFE_ADDA6_ULCF_CFG_12_11			0x0ab4
2523
#define AFE_ADDA6_ULCF_CFG_14_13			0x0ab8
2524
#define AFE_ADDA6_ULCF_CFG_16_15			0x0abc
2525
#define AFE_ADDA6_ULCF_CFG_18_17			0x0ac0
2526
#define AFE_ADDA6_ULCF_CFG_20_19			0x0ac4
2527
#define AFE_ADDA6_ULCF_CFG_22_21			0x0ac8
2528
#define AFE_ADDA6_ULCF_CFG_24_23			0x0acc
2529
#define AFE_ADDA6_ULCF_CFG_26_25			0x0ad0
2530
#define AFE_ADDA6_ULCF_CFG_28_27			0x0ad4
2531
#define AFE_ADDA6_ULCF_CFG_30_29			0x0ad8
2532
#define AFE_ADD6A_UL_SRC_MON0				0x0ae4
2533
#define AFE_ADDA6_UL_SRC_MON1				0x0ae8
2534
#define AFE_CONN43					0x0af8
2535
#define AFE_CONN43_1					0x0afc
2536
#define AFE_MOD_DAI_CON0				0x0b00
2537
#define AFE_MOD_DAI_BASE_MSB				0x0b04
2538
#define AFE_MOD_DAI_BASE				0x0b08
2539
#define AFE_MOD_DAI_CUR_MSB				0x0b0c
2540
#define AFE_MOD_DAI_CUR					0x0b10
2541
#define AFE_MOD_DAI_END_MSB				0x0b14
2542
#define AFE_MOD_DAI_END					0x0b18
2543
#define AFE_AWB_RCH_MON					0x0b70
2544
#define AFE_AWB_LCH_MON					0x0b74
2545
#define AFE_VUL_RCH_MON					0x0b78
2546
#define AFE_VUL_LCH_MON					0x0b7c
2547
#define AFE_VUL12_RCH_MON				0x0b80
2548
#define AFE_VUL12_LCH_MON				0x0b84
2549
#define AFE_VUL2_RCH_MON				0x0b88
2550
#define AFE_VUL2_LCH_MON				0x0b8c
2551
#define AFE_DAI_DATA_MON				0x0b90
2552
#define AFE_MOD_DAI_DATA_MON				0x0b94
2553
#define AFE_DAI2_DATA_MON				0x0b98
2554
#define AFE_AWB2_RCH_MON				0x0b9c
2555
#define AFE_AWB2_LCH_MON				0x0ba0
2556
#define AFE_VUL3_RCH_MON				0x0ba4
2557
#define AFE_VUL3_LCH_MON				0x0ba8
2558
#define AFE_VUL4_RCH_MON				0x0bac
2559
#define AFE_VUL4_LCH_MON				0x0bb0
2560
#define AFE_VUL5_RCH_MON				0x0bb4
2561
#define AFE_VUL5_LCH_MON				0x0bb8
2562
#define AFE_VUL6_RCH_MON				0x0bbc
2563
#define AFE_VUL6_LCH_MON				0x0bc0
2564
#define AFE_DL1_RCH_MON					0x0bc4
2565
#define AFE_DL1_LCH_MON					0x0bc8
2566
#define AFE_DL2_RCH_MON					0x0bcc
2567
#define AFE_DL2_LCH_MON					0x0bd0
2568
#define AFE_DL12_RCH1_MON				0x0bd4
2569
#define AFE_DL12_LCH1_MON				0x0bd8
2570
#define AFE_DL12_RCH2_MON				0x0bdc
2571
#define AFE_DL12_LCH2_MON				0x0be0
2572
#define AFE_DL3_RCH_MON					0x0be4
2573
#define AFE_DL3_LCH_MON					0x0be8
2574
#define AFE_DL4_RCH_MON					0x0bec
2575
#define AFE_DL4_LCH_MON					0x0bf0
2576
#define AFE_DL5_RCH_MON					0x0bf4
2577
#define AFE_DL5_LCH_MON					0x0bf8
2578
#define AFE_DL6_RCH_MON					0x0bfc
2579
#define AFE_DL6_LCH_MON					0x0c00
2580
#define AFE_DL7_RCH_MON					0x0c04
2581
#define AFE_DL7_LCH_MON					0x0c08
2582
#define AFE_DL8_RCH_MON					0x0c0c
2583
#define AFE_DL8_LCH_MON					0x0c10
2584
#define AFE_VUL5_CON0					0x0c14
2585
#define AFE_VUL5_BASE_MSB				0x0c18
2586
#define AFE_VUL5_BASE					0x0c1c
2587
#define AFE_VUL5_CUR_MSB				0x0c20
2588
#define AFE_VUL5_CUR					0x0c24
2589
#define AFE_VUL5_END_MSB				0x0c28
2590
#define AFE_VUL5_END					0x0c2c
2591
#define AFE_VUL6_CON0					0x0c30
2592
#define AFE_VUL6_BASE_MSB				0x0c34
2593
#define AFE_VUL6_BASE					0x0c38
2594
#define AFE_VUL6_CUR_MSB				0x0c3c
2595
#define AFE_VUL6_CUR					0x0c40
2596
#define AFE_VUL6_END_MSB				0x0c44
2597
#define AFE_VUL6_END					0x0c48
2598
#define AFE_ADDA_DL_SDM_DCCOMP_CON			0x0c50
2599
#define AFE_ADDA_DL_SDM_TEST				0x0c54
2600
#define AFE_ADDA_DL_DC_COMP_CFG0			0x0c58
2601
#define AFE_ADDA_DL_DC_COMP_CFG1			0x0c5c
2602
#define AFE_ADDA_DL_SDM_FIFO_MON			0x0c60
2603
#define AFE_ADDA_DL_SRC_LCH_MON				0x0c64
2604
#define AFE_ADDA_DL_SRC_RCH_MON				0x0c68
2605
#define AFE_ADDA_DL_SDM_OUT_MON				0x0c6c
2606
#define AFE_ADDA_DL_SDM_DITHER_CON			0x0c70
2607
#define AFE_ADDA_DL_SDM_AUTO_RESET_CON			0x0c74
2608
#define AFE_CONNSYS_I2S_CON				0x0c78
2609
#define AFE_CONNSYS_I2S_MON				0x0c7c
2610
#define AFE_ASRC_2CH_CON0				0x0c80
2611
#define AFE_ASRC_2CH_CON1				0x0c84
2612
#define AFE_ASRC_2CH_CON2				0x0c88
2613
#define AFE_ASRC_2CH_CON3				0x0c8c
2614
#define AFE_ASRC_2CH_CON4				0x0c90
2615
#define AFE_ASRC_2CH_CON5				0x0c94
2616
#define AFE_ASRC_2CH_CON6				0x0c98
2617
#define AFE_ASRC_2CH_CON7				0x0c9c
2618
#define AFE_ASRC_2CH_CON8				0x0ca0
2619
#define AFE_ASRC_2CH_CON9				0x0ca4
2620
#define AFE_ASRC_2CH_CON10				0x0ca8
2621
#define AFE_ASRC_2CH_CON12				0x0cb0
2622
#define AFE_ASRC_2CH_CON13				0x0cb4
2623
#define AFE_ADDA6_IIR_COEF_02_01			0x0ce0
2624
#define AFE_ADDA6_IIR_COEF_04_03			0x0ce4
2625
#define AFE_ADDA6_IIR_COEF_06_05			0x0ce8
2626
#define AFE_ADDA6_IIR_COEF_08_07			0x0cec
2627
#define AFE_ADDA6_IIR_COEF_10_09			0x0cf0
2628
#define AFE_CONN67					0x0cf4
2629
#define AFE_CONN68					0x0cf8
2630
#define AFE_CONN69					0x0cfc
2631
#define AFE_SE_PROT_SIDEBAND				0x0d38
2632
#define AFE_SE_DOMAIN_SIDEBAND0				0x0d3c
2633
#define AFE_ADDA_PREDIS_CON2				0x0d40
2634
#define AFE_ADDA_PREDIS_CON3				0x0d44
2635
#define AFE_SE_DOMAIN_SIDEBAND1				0x0d54
2636
#define AFE_SE_DOMAIN_SIDEBAND2				0x0d58
2637
#define AFE_SE_DOMAIN_SIDEBAND3				0x0d5c
2638
#define AFE_CONN44					0x0d70
2639
#define AFE_CONN45					0x0d74
2640
#define AFE_CONN46					0x0d78
2641
#define AFE_CONN47					0x0d7c
2642
#define AFE_CONN44_1					0x0d80
2643
#define AFE_CONN45_1					0x0d84
2644
#define AFE_CONN46_1					0x0d88
2645
#define AFE_CONN47_1					0x0d8c
2646
#define AFE_HD_ENGEN_ENABLE				0x0dd0
2647
#define AFE_ADDA_DL_NLE_FIFO_MON			0x0dfc
2648
#define AFE_ADDA_MTKAIF_CFG0				0x0e00
2649
#define AFE_CONN67_1					0x0e04
2650
#define AFE_CONN68_1					0x0e08
2651
#define AFE_CONN69_1					0x0e0c
2652
#define AFE_ADDA_MTKAIF_SYNCWORD_CFG			0x0e14
2653
#define AFE_ADDA_MTKAIF_RX_CFG0				0x0e20
2654
#define AFE_ADDA_MTKAIF_RX_CFG1				0x0e24
2655
#define AFE_ADDA_MTKAIF_RX_CFG2				0x0e28
2656
#define AFE_ADDA_MTKAIF_MON0				0x0e34
2657
#define AFE_ADDA_MTKAIF_MON1				0x0e38
2658
#define AFE_AUD_PAD_TOP					0x0e40
2659
#define AFE_DL_NLE_R_CFG0				0x0e44
2660
#define AFE_DL_NLE_R_CFG1				0x0e48
2661
#define AFE_DL_NLE_L_CFG0				0x0e4c
2662
#define AFE_DL_NLE_L_CFG1				0x0e50
2663
#define AFE_DL_NLE_R_MON0				0x0e54
2664
#define AFE_DL_NLE_R_MON1				0x0e58
2665
#define AFE_DL_NLE_R_MON2				0x0e5c
2666
#define AFE_DL_NLE_L_MON0				0x0e60
2667
#define AFE_DL_NLE_L_MON1				0x0e64
2668
#define AFE_DL_NLE_L_MON2				0x0e68
2669
#define AFE_DL_NLE_GAIN_CFG0				0x0e6c
2670
#define AFE_ADDA6_MTKAIF_CFG0				0x0e70
2671
#define AFE_ADDA6_MTKAIF_RX_CFG0			0x0e74
2672
#define AFE_ADDA6_MTKAIF_RX_CFG1			0x0e78
2673
#define AFE_ADDA6_MTKAIF_RX_CFG2			0x0e7c
2674
#define AFE_GENERAL1_ASRC_2CH_CON0			0x0e80
2675
#define AFE_GENERAL1_ASRC_2CH_CON1			0x0e84
2676
#define AFE_GENERAL1_ASRC_2CH_CON2			0x0e88
2677
#define AFE_GENERAL1_ASRC_2CH_CON3			0x0e8c
2678
#define AFE_GENERAL1_ASRC_2CH_CON4			0x0e90
2679
#define AFE_GENERAL1_ASRC_2CH_CON5			0x0e94
2680
#define AFE_GENERAL1_ASRC_2CH_CON6			0x0e98
2681
#define AFE_GENERAL1_ASRC_2CH_CON7			0x0e9c
2682
#define AFE_GENERAL1_ASRC_2CH_CON8			0x0ea0
2683
#define AFE_GENERAL1_ASRC_2CH_CON9			0x0ea4
2684
#define AFE_GENERAL1_ASRC_2CH_CON10			0x0ea8
2685
#define AFE_GENERAL1_ASRC_2CH_CON12			0x0eb0
2686
#define AFE_GENERAL1_ASRC_2CH_CON13			0x0eb4
2687
#define GENERAL_ASRC_MODE				0x0eb8
2688
#define GENERAL_ASRC_EN_ON				0x0ebc
2689
#define AFE_CONN48					0x0ec0
2690
#define AFE_CONN49					0x0ec4
2691
#define AFE_CONN50					0x0ec8
2692
#define AFE_CONN51					0x0ecc
2693
#define AFE_CONN52					0x0ed0
2694
#define AFE_CONN53					0x0ed4
2695
#define AFE_CONN54					0x0ed8
2696
#define AFE_CONN55					0x0edc
2697
#define AFE_CONN48_1					0x0ee0
2698
#define AFE_CONN49_1					0x0ee4
2699
#define AFE_CONN50_1					0x0ee8
2700
#define AFE_CONN51_1					0x0eec
2701
#define AFE_CONN52_1					0x0ef0
2702
#define AFE_CONN53_1					0x0ef4
2703
#define AFE_CONN54_1					0x0ef8
2704
#define AFE_CONN55_1					0x0efc
2705
#define AFE_GENERAL2_ASRC_2CH_CON0			0x0f00
2706
#define AFE_GENERAL2_ASRC_2CH_CON1			0x0f04
2707
#define AFE_GENERAL2_ASRC_2CH_CON2			0x0f08
2708
#define AFE_GENERAL2_ASRC_2CH_CON3			0x0f0c
2709
#define AFE_GENERAL2_ASRC_2CH_CON4			0x0f10
2710
#define AFE_GENERAL2_ASRC_2CH_CON5			0x0f14
2711
#define AFE_GENERAL2_ASRC_2CH_CON6			0x0f18
2712
#define AFE_GENERAL2_ASRC_2CH_CON7			0x0f1c
2713
#define AFE_GENERAL2_ASRC_2CH_CON8			0x0f20
2714
#define AFE_GENERAL2_ASRC_2CH_CON9			0x0f24
2715
#define AFE_GENERAL2_ASRC_2CH_CON10			0x0f28
2716
#define AFE_GENERAL2_ASRC_2CH_CON12			0x0f30
2717
#define AFE_GENERAL2_ASRC_2CH_CON13			0x0f34
2718
#define AFE_DL5_CON0					0x0f4c
2719
#define AFE_DL5_BASE_MSB				0x0f50
2720
#define AFE_DL5_BASE					0x0f54
2721
#define AFE_DL5_CUR_MSB					0x0f58
2722
#define AFE_DL5_CUR					0x0f5c
2723
#define AFE_DL5_END_MSB					0x0f60
2724
#define AFE_DL5_END					0x0f64
2725
#define AFE_DL6_CON0					0x0f68
2726
#define AFE_DL6_BASE_MSB				0x0f6c
2727
#define AFE_DL6_BASE					0x0f70
2728
#define AFE_DL6_CUR_MSB					0x0f74
2729
#define AFE_DL6_CUR					0x0f78
2730
#define AFE_DL6_END_MSB					0x0f7c
2731
#define AFE_DL6_END					0x0f80
2732
#define AFE_DL7_CON0					0x0f84
2733
#define AFE_DL7_BASE_MSB				0x0f88
2734
#define AFE_DL7_BASE					0x0f8c
2735
#define AFE_DL7_CUR_MSB					0x0f90
2736
#define AFE_DL7_CUR					0x0f94
2737
#define AFE_DL7_END_MSB					0x0f98
2738
#define AFE_DL7_END					0x0f9c
2739
#define AFE_DL8_CON0					0x0fa0
2740
#define AFE_DL8_BASE_MSB				0x0fa4
2741
#define AFE_DL8_BASE					0x0fa8
2742
#define AFE_DL8_CUR_MSB					0x0fac
2743
#define AFE_DL8_CUR					0x0fb0
2744
#define AFE_DL8_END_MSB					0x0fb4
2745
#define AFE_DL8_END					0x0fb8
2746
#define AFE_SE_SECURE_CON				0x1004
2747
#define AFE_PROT_SIDEBAND_MON				0x1008
2748
#define AFE_DOMAIN_SIDEBAND0_MON			0x100c
2749
#define AFE_DOMAIN_SIDEBAND1_MON			0x1010
2750
#define AFE_DOMAIN_SIDEBAND2_MON			0x1014
2751
#define AFE_DOMAIN_SIDEBAND3_MON			0x1018
2752
#define AFE_SECURE_MASK_CONN0				0x1020
2753
#define AFE_SECURE_MASK_CONN1				0x1024
2754
#define AFE_SECURE_MASK_CONN2				0x1028
2755
#define AFE_SECURE_MASK_CONN3				0x102c
2756
#define AFE_SECURE_MASK_CONN4				0x1030
2757
#define AFE_SECURE_MASK_CONN5				0x1034
2758
#define AFE_SECURE_MASK_CONN6				0x1038
2759
#define AFE_SECURE_MASK_CONN7				0x103c
2760
#define AFE_SECURE_MASK_CONN8				0x1040
2761
#define AFE_SECURE_MASK_CONN9				0x1044
2762
#define AFE_SECURE_MASK_CONN10				0x1048
2763
#define AFE_SECURE_MASK_CONN11				0x104c
2764
#define AFE_SECURE_MASK_CONN12				0x1050
2765
#define AFE_SECURE_MASK_CONN13				0x1054
2766
#define AFE_SECURE_MASK_CONN14				0x1058
2767
#define AFE_SECURE_MASK_CONN15				0x105c
2768
#define AFE_SECURE_MASK_CONN16				0x1060
2769
#define AFE_SECURE_MASK_CONN17				0x1064
2770
#define AFE_SECURE_MASK_CONN18				0x1068
2771
#define AFE_SECURE_MASK_CONN19				0x106c
2772
#define AFE_SECURE_MASK_CONN20				0x1070
2773
#define AFE_SECURE_MASK_CONN21				0x1074
2774
#define AFE_SECURE_MASK_CONN22				0x1078
2775
#define AFE_SECURE_MASK_CONN23				0x107c
2776
#define AFE_SECURE_MASK_CONN24				0x1080
2777
#define AFE_SECURE_MASK_CONN25				0x1084
2778
#define AFE_SECURE_MASK_CONN26				0x1088
2779
#define AFE_SECURE_MASK_CONN27				0x108c
2780
#define AFE_SECURE_MASK_CONN28				0x1090
2781
#define AFE_SECURE_MASK_CONN29				0x1094
2782
#define AFE_SECURE_MASK_CONN30				0x1098
2783
#define AFE_SECURE_MASK_CONN31				0x109c
2784
#define AFE_SECURE_MASK_CONN32				0x10a0
2785
#define AFE_SECURE_MASK_CONN33				0x10a4
2786
#define AFE_SECURE_MASK_CONN34				0x10a8
2787
#define AFE_SECURE_MASK_CONN35				0x10ac
2788
#define AFE_SECURE_MASK_CONN36				0x10b0
2789
#define AFE_SECURE_MASK_CONN37				0x10b4
2790
#define AFE_SECURE_MASK_CONN38				0x10b8
2791
#define AFE_SECURE_MASK_CONN39				0x10bc
2792
#define AFE_SECURE_MASK_CONN40				0x10c0
2793
#define AFE_SECURE_MASK_CONN41				0x10c4
2794
#define AFE_SECURE_MASK_CONN42				0x10c8
2795
#define AFE_SECURE_MASK_CONN43				0x10cc
2796
#define AFE_SECURE_MASK_CONN44				0x10d0
2797
#define AFE_SECURE_MASK_CONN45				0x10d4
2798
#define AFE_SECURE_MASK_CONN46				0x10d8
2799
#define AFE_SECURE_MASK_CONN47				0x10dc
2800
#define AFE_SECURE_MASK_CONN48				0x10e0
2801
#define AFE_SECURE_MASK_CONN49				0x10e4
2802
#define AFE_SECURE_MASK_CONN50				0x10e8
2803
#define AFE_SECURE_MASK_CONN51				0x10ec
2804
#define AFE_SECURE_MASK_CONN52				0x10f0
2805
#define AFE_SECURE_MASK_CONN53				0x10f4
2806
#define AFE_SECURE_MASK_CONN54				0x10f8
2807
#define AFE_SECURE_MASK_CONN55				0x10fc
2808
#define AFE_SECURE_MASK_CONN56				0x1100
2809
#define AFE_SECURE_MASK_CONN57				0x1104
2810
#define AFE_SECURE_MASK_CONN0_1				0x1108
2811
#define AFE_SECURE_MASK_CONN1_1				0x110c
2812
#define AFE_SECURE_MASK_CONN2_1				0x1110
2813
#define AFE_SECURE_MASK_CONN3_1				0x1114
2814
#define AFE_SECURE_MASK_CONN4_1				0x1118
2815
#define AFE_SECURE_MASK_CONN5_1				0x111c
2816
#define AFE_SECURE_MASK_CONN6_1				0x1120
2817
#define AFE_SECURE_MASK_CONN7_1				0x1124
2818
#define AFE_SECURE_MASK_CONN8_1				0x1128
2819
#define AFE_SECURE_MASK_CONN9_1				0x112c
2820
#define AFE_SECURE_MASK_CONN10_1			0x1130
2821
#define AFE_SECURE_MASK_CONN11_1			0x1134
2822
#define AFE_SECURE_MASK_CONN12_1			0x1138
2823
#define AFE_SECURE_MASK_CONN13_1			0x113c
2824
#define AFE_SECURE_MASK_CONN14_1			0x1140
2825
#define AFE_SECURE_MASK_CONN15_1			0x1144
2826
#define AFE_SECURE_MASK_CONN16_1			0x1148
2827
#define AFE_SECURE_MASK_CONN17_1			0x114c
2828
#define AFE_SECURE_MASK_CONN18_1			0x1150
2829
#define AFE_SECURE_MASK_CONN19_1			0x1154
2830
#define AFE_SECURE_MASK_CONN20_1			0x1158
2831
#define AFE_SECURE_MASK_CONN21_1			0x115c
2832
#define AFE_SECURE_MASK_CONN22_1			0x1160
2833
#define AFE_SECURE_MASK_CONN23_1			0x1164
2834
#define AFE_SECURE_MASK_CONN24_1			0x1168
2835
#define AFE_SECURE_MASK_CONN25_1			0x116c
2836
#define AFE_SECURE_MASK_CONN26_1			0x1170
2837
#define AFE_SECURE_MASK_CONN27_1			0x1174
2838
#define AFE_SECURE_MASK_CONN28_1			0x1178
2839
#define AFE_SECURE_MASK_CONN29_1			0x117c
2840
#define AFE_SECURE_MASK_CONN30_1			0x1180
2841
#define AFE_SECURE_MASK_CONN31_1			0x1184
2842
#define AFE_SECURE_MASK_CONN32_1			0x1188
2843
#define AFE_SECURE_MASK_CONN33_1			0x118c
2844
#define AFE_SECURE_MASK_CONN34_1			0x1190
2845
#define AFE_SECURE_MASK_CONN35_1			0x1194
2846
#define AFE_SECURE_MASK_CONN36_1			0x1198
2847
#define AFE_SECURE_MASK_CONN37_1			0x119c
2848
#define AFE_SECURE_MASK_CONN38_1			0x11a0
2849
#define AFE_SECURE_MASK_CONN39_1			0x11a4
2850
#define AFE_SECURE_MASK_CONN40_1			0x11a8
2851
#define AFE_SECURE_MASK_CONN41_1			0x11ac
2852
#define AFE_SECURE_MASK_CONN42_1			0x11b0
2853
#define AFE_SECURE_MASK_CONN43_1			0x11b4
2854
#define AFE_SECURE_MASK_CONN44_1			0x11b8
2855
#define AFE_SECURE_MASK_CONN45_1			0x11bc
2856
#define AFE_SECURE_MASK_CONN46_1			0x11c0
2857
#define AFE_SECURE_MASK_CONN47_1			0x11c4
2858
#define AFE_SECURE_MASK_CONN48_1			0x11c8
2859
#define AFE_SECURE_MASK_CONN49_1			0x11cc
2860
#define AFE_SECURE_MASK_CONN50_1			0x11d0
2861
#define AFE_SECURE_MASK_CONN51_1			0x11d4
2862
#define AFE_SECURE_MASK_CONN52_1			0x11d8
2863
#define AFE_SECURE_MASK_CONN53_1			0x11dc
2864
#define AFE_SECURE_MASK_CONN54_1			0x11e0
2865
#define AFE_SECURE_MASK_CONN55_1			0x11e4
2866
#define AFE_SECURE_MASK_CONN56_1			0x11e8
2867
#define AFE_CONN60_1					0x11f0
2868
#define AFE_CONN61_1					0x11f4
2869
#define AFE_CONN62_1					0x11f8
2870
#define AFE_CONN63_1					0x11fc
2871
#define AFE_CONN64_1					0x1220
2872
#define AFE_CONN65_1					0x1224
2873
#define AFE_CONN66_1					0x1228
2874
#define FPGA_CFG4					0x1230
2875
#define FPGA_CFG5					0x1234
2876
#define FPGA_CFG6					0x1238
2877
#define FPGA_CFG7					0x123c
2878
#define FPGA_CFG8					0x1240
2879
#define FPGA_CFG9					0x1244
2880
#define FPGA_CFG10					0x1248
2881
#define FPGA_CFG11					0x124c
2882
#define FPGA_CFG12					0x1250
2883
#define FPGA_CFG13					0x1254
2884
#define ETDM_IN1_CON0					0x1430
2885
#define ETDM_IN1_CON1					0x1434
2886
#define ETDM_IN1_CON2					0x1438
2887
#define ETDM_IN1_CON3					0x143c
2888
#define ETDM_IN1_CON4					0x1440
2889
#define ETDM_IN1_CON5					0x1444
2890
#define ETDM_IN1_CON6					0x1448
2891
#define ETDM_IN1_CON7					0x144c
2892
#define ETDM_IN1_CON8					0x1450
2893
#define ETDM_OUT1_CON0					0x1454
2894
#define ETDM_OUT1_CON1					0x1458
2895
#define ETDM_OUT1_CON2					0x145c
2896
#define ETDM_OUT1_CON3					0x1460
2897
#define ETDM_OUT1_CON4					0x1464
2898
#define ETDM_OUT1_CON5					0x1468
2899
#define ETDM_OUT1_CON6					0x146c
2900
#define ETDM_OUT1_CON7					0x1470
2901
#define ETDM_OUT1_CON8					0x1474
2902
#define ETDM_IN1_MON					0x1478
2903
#define ETDM_OUT1_MON					0x147c
2904
#define ETDM_0_3_COWORK_CON0				0x18b0
2905
#define ETDM_0_3_COWORK_CON1				0x18b4
2906
#define ETDM_0_3_COWORK_CON3				0x18bc
2907

2908
#define AFE_MAX_REGISTER				ETDM_0_3_COWORK_CON3
2909

2910
#define AFE_IRQ_STATUS_BITS				0x87FFFFFF
2911
#define AFE_IRQ_CNT_SHIFT				0
2912
#define AFE_IRQ_CNT_MASK				0x3ffff
2913
#endif
2914

2915
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