Path: blob/master/sound/soc/mediatek/mt8188/mt8188-afe-common.h
26488 views
/* SPDX-License-Identifier: GPL-2.0 */1/*2* mt8188-afe-common.h -- MediaTek 8188 audio driver definitions3*4* Copyright (c) 2022 MediaTek Inc.5* Author: Bicycle Tsai <[email protected]>6* Trevor Wu <[email protected]>7* Chun-Chia Chiu <[email protected]>8*/910#ifndef _MT_8188_AFE_COMMON_H_11#define _MT_8188_AFE_COMMON_H_1213#include <linux/list.h>14#include <linux/regmap.h>15#include <sound/soc.h>16#include "../common/mtk-base-afe.h"1718enum {19MT8188_DAI_START,20MT8188_AFE_MEMIF_START = MT8188_DAI_START,21MT8188_AFE_MEMIF_DL2 = MT8188_AFE_MEMIF_START,22MT8188_AFE_MEMIF_DL3,23MT8188_AFE_MEMIF_DL6,24MT8188_AFE_MEMIF_DL7,25MT8188_AFE_MEMIF_DL8,26MT8188_AFE_MEMIF_DL10,27MT8188_AFE_MEMIF_DL11,28MT8188_AFE_MEMIF_UL_START,29MT8188_AFE_MEMIF_UL1 = MT8188_AFE_MEMIF_UL_START,30MT8188_AFE_MEMIF_UL2,31MT8188_AFE_MEMIF_UL3,32MT8188_AFE_MEMIF_UL4,33MT8188_AFE_MEMIF_UL5,34MT8188_AFE_MEMIF_UL6,35MT8188_AFE_MEMIF_UL8,36MT8188_AFE_MEMIF_UL9,37MT8188_AFE_MEMIF_UL10,38MT8188_AFE_MEMIF_END,39MT8188_AFE_MEMIF_NUM = (MT8188_AFE_MEMIF_END - MT8188_AFE_MEMIF_START),40MT8188_AFE_IO_START = MT8188_AFE_MEMIF_END,41MT8188_AFE_IO_DL_SRC = MT8188_AFE_IO_START,42MT8188_AFE_IO_DMIC_IN,43MT8188_AFE_IO_DPTX,44MT8188_AFE_IO_ETDM_START,45MT8188_AFE_IO_ETDM1_IN = MT8188_AFE_IO_ETDM_START,46MT8188_AFE_IO_ETDM2_IN,47MT8188_AFE_IO_ETDM1_OUT,48MT8188_AFE_IO_ETDM2_OUT,49MT8188_AFE_IO_ETDM3_OUT,50MT8188_AFE_IO_ETDM_END,51MT8188_AFE_IO_ETDM_NUM =52(MT8188_AFE_IO_ETDM_END - MT8188_AFE_IO_ETDM_START),53MT8188_AFE_IO_PCM = MT8188_AFE_IO_ETDM_END,54MT8188_AFE_IO_UL_SRC,55MT8188_AFE_IO_END,56MT8188_AFE_IO_NUM = (MT8188_AFE_IO_END - MT8188_AFE_IO_START),57MT8188_DAI_END = MT8188_AFE_IO_END,58MT8188_DAI_NUM = (MT8188_DAI_END - MT8188_DAI_START),59};6061enum {62MT8188_TOP_CG_A1SYS_TIMING,63MT8188_TOP_CG_A2SYS_TIMING,64MT8188_TOP_CG_26M_TIMING,65MT8188_TOP_CG_NUM,66};6768enum {69MT8188_AFE_IRQ_1,70MT8188_AFE_IRQ_2,71MT8188_AFE_IRQ_3,72MT8188_AFE_IRQ_8,73MT8188_AFE_IRQ_9,74MT8188_AFE_IRQ_10,75MT8188_AFE_IRQ_13,76MT8188_AFE_IRQ_14,77MT8188_AFE_IRQ_15,78MT8188_AFE_IRQ_16,79MT8188_AFE_IRQ_17,80MT8188_AFE_IRQ_18,81MT8188_AFE_IRQ_19,82MT8188_AFE_IRQ_20,83MT8188_AFE_IRQ_21,84MT8188_AFE_IRQ_22,85MT8188_AFE_IRQ_23,86MT8188_AFE_IRQ_24,87MT8188_AFE_IRQ_25,88MT8188_AFE_IRQ_26,89MT8188_AFE_IRQ_27,90MT8188_AFE_IRQ_28,91MT8188_AFE_IRQ_NUM,92};9394enum {95MT8188_ETDM_OUT1_1X_EN = 9,96MT8188_ETDM_OUT2_1X_EN = 10,97MT8188_ETDM_OUT3_1X_EN = 11,98MT8188_ETDM_IN1_1X_EN = 12,99MT8188_ETDM_IN2_1X_EN = 13,100MT8188_ETDM_IN1_NX_EN = 25,101MT8188_ETDM_IN2_NX_EN = 26,102};103104enum {105MT8188_MTKAIF_MISO_0,106MT8188_MTKAIF_MISO_1,107MT8188_MTKAIF_MISO_NUM,108};109110struct mtk_dai_memif_irq_priv {111unsigned int asys_timing_sel;112};113114struct mtkaif_param {115bool mtkaif_calibration_ok;116int mtkaif_chosen_phase[MT8188_MTKAIF_MISO_NUM];117int mtkaif_phase_cycle[MT8188_MTKAIF_MISO_NUM];118int mtkaif_dmic_on;119};120121struct clk;122123struct mt8188_afe_private {124struct clk **clk;125struct clk_lookup **lookup;126struct regmap *topckgen;127int pm_runtime_bypass_reg_ctl;128spinlock_t afe_ctrl_lock; /* Lock for afe control */129struct mtk_dai_memif_irq_priv irq_priv[MT8188_AFE_IRQ_NUM];130struct mtkaif_param mtkaif_params;131132/* dai */133void *dai_priv[MT8188_DAI_NUM];134};135136int mt8188_afe_fs_timing(unsigned int rate);137/* dai register */138int mt8188_dai_adda_register(struct mtk_base_afe *afe);139int mt8188_dai_dmic_register(struct mtk_base_afe *afe);140int mt8188_dai_etdm_register(struct mtk_base_afe *afe);141int mt8188_dai_pcm_register(struct mtk_base_afe *afe);142143#define MT8188_SOC_ENUM_EXT(xname, xenum, xhandler_get, xhandler_put, id) \144{ \145.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \146.info = snd_soc_info_enum_double, \147.get = xhandler_get, .put = xhandler_put, \148.device = id, \149.private_value = (unsigned long)&(xenum), \150}151152#endif153154155