Path: blob/master/sound/soc/mediatek/mt8188/mt8188-audsys-clkid.h
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/* SPDX-License-Identifier: GPL-2.0 */1/*2* mt8188-audsys-clkid.h -- MediaTek 8188 audsys clock id definition3*4* Copyright (c) 2022 MediaTek Inc.5* Author: Chun-Chia Chiu <[email protected]>6*/78#ifndef _MT8188_AUDSYS_CLKID_H_9#define _MT8188_AUDSYS_CLKID_H_1011enum{12CLK_AUD_AFE,13CLK_AUD_LRCK_CNT,14CLK_AUD_SPDIFIN_TUNER_APLL,15CLK_AUD_SPDIFIN_TUNER_DBG,16CLK_AUD_UL_TML,17CLK_AUD_APLL1_TUNER,18CLK_AUD_APLL2_TUNER,19CLK_AUD_TOP0_SPDF,20CLK_AUD_APLL,21CLK_AUD_APLL2,22CLK_AUD_DAC,23CLK_AUD_DAC_PREDIS,24CLK_AUD_TML,25CLK_AUD_ADC,26CLK_AUD_DAC_HIRES,27CLK_AUD_A1SYS_HP,28CLK_AUD_AFE_DMIC1,29CLK_AUD_AFE_DMIC2,30CLK_AUD_AFE_DMIC3,31CLK_AUD_AFE_DMIC4,32CLK_AUD_AFE_26M_DMIC_TM,33CLK_AUD_UL_TML_HIRES,34CLK_AUD_ADC_HIRES,35CLK_AUD_DMIC_HIRES1,36CLK_AUD_DMIC_HIRES2,37CLK_AUD_DMIC_HIRES3,38CLK_AUD_DMIC_HIRES4,39CLK_AUD_LINEIN_TUNER,40CLK_AUD_EARC_TUNER,41CLK_AUD_I2SIN,42CLK_AUD_TDM_IN,43CLK_AUD_I2S_OUT,44CLK_AUD_TDM_OUT,45CLK_AUD_HDMI_OUT,46CLK_AUD_ASRC11,47CLK_AUD_ASRC12,48CLK_AUD_MULTI_IN,49CLK_AUD_INTDIR,50CLK_AUD_A1SYS,51CLK_AUD_A2SYS,52CLK_AUD_PCMIF,53CLK_AUD_A3SYS,54CLK_AUD_A4SYS,55CLK_AUD_MEMIF_UL1,56CLK_AUD_MEMIF_UL2,57CLK_AUD_MEMIF_UL3,58CLK_AUD_MEMIF_UL4,59CLK_AUD_MEMIF_UL5,60CLK_AUD_MEMIF_UL6,61CLK_AUD_MEMIF_UL8,62CLK_AUD_MEMIF_UL9,63CLK_AUD_MEMIF_UL10,64CLK_AUD_MEMIF_DL2,65CLK_AUD_MEMIF_DL3,66CLK_AUD_MEMIF_DL6,67CLK_AUD_MEMIF_DL7,68CLK_AUD_MEMIF_DL8,69CLK_AUD_MEMIF_DL10,70CLK_AUD_MEMIF_DL11,71CLK_AUD_GASRC0,72CLK_AUD_GASRC1,73CLK_AUD_GASRC2,74CLK_AUD_GASRC3,75CLK_AUD_GASRC4,76CLK_AUD_GASRC5,77CLK_AUD_GASRC6,78CLK_AUD_GASRC7,79CLK_AUD_GASRC8,80CLK_AUD_GASRC9,81CLK_AUD_GASRC10,82CLK_AUD_GASRC11,83CLK_AUD_NR_CLK,84};8586#endif878889