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torvalds
GitHub Repository: torvalds/linux
 Path: blob/master/sound/soc/mediatek/mt8189/mt8189-afe-clk.h
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/* SPDX-License-Identifier: GPL-2.0 */

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/*

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 * mt8189-afe-clk.h  --  Mediatek 8189 afe clock ctrl definition

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 *

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 * Copyright (c) 2025 MediaTek Inc.

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 * Author: Darren Ye <[email protected]>

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 */

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#ifndef _MT8189_AFE_CLOCK_CTRL_H_

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#define _MT8189_AFE_CLOCK_CTRL_H_

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/* APLL */

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#define APLL1_W_NAME "APLL1"

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#define APLL2_W_NAME "APLL2"

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enum {

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	MT8189_APLL1,

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	MT8189_APLL2,

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};

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enum {

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	MT8189_CLK_TOP_MUX_AUDIOINTBUS,

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	MT8189_CLK_TOP_MUX_AUD_ENG1,

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	MT8189_CLK_TOP_MUX_AUD_ENG2,

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	MT8189_CLK_TOP_MUX_AUDIO_H,

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	/* pll */

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	MT8189_CLK_TOP_APLL1_CK,

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	MT8189_CLK_TOP_APLL2_CK,

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	/* divider */

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	MT8189_CLK_TOP_APLL1_D4,

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	MT8189_CLK_TOP_APLL2_D4,

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	MT8189_CLK_TOP_APLL12_DIV_I2SIN0,

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	MT8189_CLK_TOP_APLL12_DIV_I2SIN1,

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	MT8189_CLK_TOP_APLL12_DIV_I2SOUT0,

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	MT8189_CLK_TOP_APLL12_DIV_I2SOUT1,

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	MT8189_CLK_TOP_APLL12_DIV_FMI2S,

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	MT8189_CLK_TOP_APLL12_DIV_TDMOUT_M,

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	MT8189_CLK_TOP_APLL12_DIV_TDMOUT_B,

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	/* mux */

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	MT8189_CLK_TOP_MUX_AUD_1,

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	MT8189_CLK_TOP_MUX_AUD_2,

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	MT8189_CLK_TOP_I2SIN0_M_SEL,

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	MT8189_CLK_TOP_I2SIN1_M_SEL,

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	MT8189_CLK_TOP_I2SOUT0_M_SEL,

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	MT8189_CLK_TOP_I2SOUT1_M_SEL,

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	MT8189_CLK_TOP_FMI2S_M_SEL,

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	MT8189_CLK_TOP_TDMOUT_M_SEL,

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	/* top 26m */

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	MT8189_CLK_TOP_CLK26M,

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	/* peri */

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	MT8189_CLK_PERAO_AUDIO_SLV_CK_PERI,

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	MT8189_CLK_PERAO_AUDIO_MST_CK_PERI,

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	MT8189_CLK_PERAO_INTBUS_CK_PERI,

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	MT8189_CLK_NUM,

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};

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struct mtk_base_afe;

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int mt8189_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate);

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int mt8189_mck_disable(struct mtk_base_afe *afe, int mck_id);

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int mt8189_get_apll_rate(struct mtk_base_afe *afe, int apll);

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int mt8189_get_apll_by_rate(struct mtk_base_afe *afe, int rate);

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int mt8189_get_apll_by_name(struct mtk_base_afe *afe, const char *name);

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int mt8189_init_clock(struct mtk_base_afe *afe);

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int mt8189_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);

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void mt8189_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);

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int mt8189_apll1_enable(struct mtk_base_afe *afe);

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void mt8189_apll1_disable(struct mtk_base_afe *afe);

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int mt8189_apll2_enable(struct mtk_base_afe *afe);

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void mt8189_apll2_disable(struct mtk_base_afe *afe);

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int mt8189_afe_enable_main_clock(struct mtk_base_afe *afe);

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void mt8189_afe_disable_main_clock(struct mtk_base_afe *afe);

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int mt8189_afe_enable_reg_rw_clk(struct mtk_base_afe *afe);

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int mt8189_afe_disable_reg_rw_clk(struct mtk_base_afe *afe);

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#endif

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