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torvalds
GitHub Repository: torvalds/linux
Path: blob/master/sound/soc/mediatek/mt8189/mt8189-afe-common.h
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* mt8189-afe-common.h -- Mediatek 8189 audio driver definitions
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*
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* Copyright (c) 2025 MediaTek Inc.
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* Author: Darren Ye <[email protected]>
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*/
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#ifndef _MT_8189_AFE_COMMON_H_
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#define _MT_8189_AFE_COMMON_H_
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#include <linux/regmap.h>
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#include <sound/soc.h>
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#include "mt8189-reg.h"
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#include "../common/mtk-base-afe.h"
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enum {
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MTK_AFE_RATE_8K,
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MTK_AFE_RATE_11K,
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MTK_AFE_RATE_12K,
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MTK_AFE_RATE_384K,
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MTK_AFE_RATE_16K,
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MTK_AFE_RATE_22K,
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MTK_AFE_RATE_24K,
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MTK_AFE_RATE_352K,
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MTK_AFE_RATE_32K,
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MTK_AFE_RATE_44K,
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MTK_AFE_RATE_48K,
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MTK_AFE_RATE_88K,
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MTK_AFE_RATE_96K,
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MTK_AFE_RATE_176K,
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MTK_AFE_RATE_192K,
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MTK_AFE_RATE_260K,
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};
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/* HW IPM 2.0 */
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enum {
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MTK_AFE_IPM2P0_RATE_8K = 0x0,
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MTK_AFE_IPM2P0_RATE_11K = 0x1,
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MTK_AFE_IPM2P0_RATE_12K = 0x2,
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MTK_AFE_IPM2P0_RATE_16K = 0x4,
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MTK_AFE_IPM2P0_RATE_22K = 0x5,
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MTK_AFE_IPM2P0_RATE_24K = 0x6,
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MTK_AFE_IPM2P0_RATE_32K = 0x8,
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MTK_AFE_IPM2P0_RATE_44K = 0x9,
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MTK_AFE_IPM2P0_RATE_48K = 0xa,
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MTK_AFE_IPM2P0_RATE_88K = 0xd,
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MTK_AFE_IPM2P0_RATE_96K = 0xe,
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MTK_AFE_IPM2P0_RATE_176K = 0x11,
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MTK_AFE_IPM2P0_RATE_192K = 0x12,
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MTK_AFE_IPM2P0_RATE_352K = 0x15,
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MTK_AFE_IPM2P0_RATE_384K = 0x16,
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};
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enum {
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MTK_AFE_DAI_MEMIF_RATE_8K,
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MTK_AFE_DAI_MEMIF_RATE_16K,
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MTK_AFE_DAI_MEMIF_RATE_32K,
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MTK_AFE_DAI_MEMIF_RATE_48K,
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};
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enum {
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MTK_AFE_PCM_RATE_8K,
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MTK_AFE_PCM_RATE_16K,
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MTK_AFE_PCM_RATE_32K,
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MTK_AFE_PCM_RATE_48K,
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};
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enum {
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MTKAIF_PROTOCOL_1,
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MTKAIF_PROTOCOL_2,
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MTKAIF_PROTOCOL_2_CLK_P2,
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};
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enum {
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MT8189_MEMIF_DL0,
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MT8189_MEMIF_DL1,
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MT8189_MEMIF_DL2,
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MT8189_MEMIF_DL3,
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MT8189_MEMIF_DL4,
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MT8189_MEMIF_DL5,
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MT8189_MEMIF_DL6,
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MT8189_MEMIF_DL7,
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MT8189_MEMIF_DL8,
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MT8189_MEMIF_DL23,
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MT8189_MEMIF_DL24,
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MT8189_MEMIF_DL25,
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MT8189_MEMIF_DL_24CH,
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MT8189_MEMIF_VUL0,
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MT8189_MEMIF_VUL1,
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MT8189_MEMIF_VUL2,
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MT8189_MEMIF_VUL3,
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MT8189_MEMIF_VUL4,
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MT8189_MEMIF_VUL5,
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MT8189_MEMIF_VUL6,
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MT8189_MEMIF_VUL7,
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MT8189_MEMIF_VUL8,
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MT8189_MEMIF_VUL9,
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MT8189_MEMIF_VUL10,
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MT8189_MEMIF_VUL24,
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MT8189_MEMIF_VUL25,
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MT8189_MEMIF_VUL_CM0,
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MT8189_MEMIF_VUL_CM1,
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MT8189_MEMIF_ETDM_IN0,
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MT8189_MEMIF_ETDM_IN1,
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MT8189_MEMIF_HDMI,
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MT8189_MEMIF_NUM,
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MT8189_DAI_ADDA = MT8189_MEMIF_NUM,
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MT8189_DAI_ADDA_CH34,
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MT8189_DAI_ADDA_CH56,
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MT8189_DAI_AP_DMIC,
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MT8189_DAI_AP_DMIC_CH34,
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MT8189_DAI_I2S_IN0,
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MT8189_DAI_I2S_IN1,
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MT8189_DAI_I2S_OUT0,
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MT8189_DAI_I2S_OUT1,
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MT8189_DAI_I2S_OUT4,
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MT8189_DAI_PCM_0,
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MT8189_DAI_TDM,
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MT8189_DAI_TDM_DPTX,
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MT8189_DAI_NUM,
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};
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/* update irq ID (= enum) from AFE_IRQ_MCU_STATUS */
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enum {
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MT8189_IRQ_0,
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MT8189_IRQ_1,
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MT8189_IRQ_2,
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MT8189_IRQ_3,
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MT8189_IRQ_4,
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MT8189_IRQ_5,
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MT8189_IRQ_6,
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MT8189_IRQ_7,
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MT8189_IRQ_8,
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MT8189_IRQ_9,
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MT8189_IRQ_10,
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MT8189_IRQ_11,
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MT8189_IRQ_12,
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MT8189_IRQ_13,
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MT8189_IRQ_14,
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MT8189_IRQ_15,
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MT8189_IRQ_16,
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MT8189_IRQ_17,
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MT8189_IRQ_18,
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MT8189_IRQ_19,
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MT8189_IRQ_20,
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MT8189_IRQ_21,
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MT8189_IRQ_22,
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MT8189_IRQ_23,
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MT8189_IRQ_24,
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MT8189_IRQ_25,
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MT8189_IRQ_26,
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MT8189_IRQ_31,
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MT8189_IRQ_NUM,
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};
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/* update irq ID (= enum) from AFE_IRQ_MCU_STATUS */
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enum {
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MT8189_CUS_IRQ_TDM, /* used only for TDM */
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MT8189_CUS_IRQ_NUM,
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};
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enum {
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/* AUDIO_ENGEN_CON0 */
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MT8189_AUDIO_26M_EN_ON,
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MT8189_AUDIO_F3P25M_EN_ON,
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MT8189_AUDIO_APLL1_EN_ON,
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MT8189_AUDIO_APLL2_EN_ON,
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MT8189_AUDIO_F26M_EN_RST,
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MT8189_MULTI_USER_RST,
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MT8189_MULTI_USER_BYPASS,
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/* AUDIO_TOP_CON4 */
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MT8189_CG_AUDIO_HOPPING_CK,
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MT8189_CG_AUDIO_F26M_CK,
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MT8189_CG_APLL1_CK,
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MT8189_CG_APLL2_CK,
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MT8189_PDN_APLL_TUNER2,
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MT8189_PDN_APLL_TUNER1,
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MT8189_AUDIO_CG_NUM,
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};
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/* MCLK */
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enum {
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MT8189_I2SIN0_MCK,
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MT8189_I2SIN1_MCK,
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MT8189_I2SOUT0_MCK,
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MT8189_I2SOUT1_MCK,
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MT8189_FMI2S_MCK,
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MT8189_TDMOUT_MCK,
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MT8189_TDMOUT_BCK,
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MT8189_MCK_NUM,
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};
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enum {
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CM0,
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CM1,
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CM_NUM,
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};
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struct clk;
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struct mt8189_afe_private {
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struct clk **clk;
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struct regmap *pmic_regmap;
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/* dai */
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void *dai_priv[MT8189_DAI_NUM];
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/* adda */
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int mtkaif_protocol;
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int mtkaif_chosen_phase[4];
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int mtkaif_phase_cycle[4];
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int mtkaif_calibration_num_phase;
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int mtkaif_dmic;
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int mtkaif_dmic_ch34;
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/* add for vs1 voter */
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bool is_adda_dl_on;
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bool is_adda_ul_on;
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/* adda dl vol idx is at maximum */
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bool is_adda_dl_max_vol;
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/* current vote status of vs1 */
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bool is_mt6363_vote;
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/* mck */
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int mck_rate[MT8189_MCK_NUM];
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/* channel merge */
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unsigned int cm_rate[CM_NUM];
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unsigned int cm_channels;
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};
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int mt8189_dai_adda_register(struct mtk_base_afe *afe);
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int mt8189_dai_i2s_register(struct mtk_base_afe *afe);
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int mt8189_dai_pcm_register(struct mtk_base_afe *afe);
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int mt8189_dai_tdm_register(struct mtk_base_afe *afe);
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#endif
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