Path: blob/master/sound/soc/mediatek/mt8189/mt8189-interconnection.h
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/* SPDX-License-Identifier: GPL-2.0 */1/*2* Mediatek MT8189 audio driver interconnection definition3*4* Copyright (c) 2025 MediaTek Inc.5* Author: Darren Ye <[email protected]>6*/78#ifndef _MT8189_INTERCONNECTION_H_9#define _MT8189_INTERCONNECTION_H_1011/* in port define */12#define I_CONNSYS_I2S_CH1 013#define I_CONNSYS_I2S_CH2 114#define I_GAIN0_OUT_CH1 615#define I_GAIN0_OUT_CH2 716#define I_GAIN1_OUT_CH1 817#define I_GAIN1_OUT_CH2 918#define I_GAIN2_OUT_CH1 1019#define I_GAIN2_OUT_CH2 1120#define I_GAIN3_OUT_CH1 1221#define I_GAIN3_OUT_CH2 1322#define I_STF_CH1 1423#define I_ADDA_UL_CH1 1624#define I_ADDA_UL_CH2 1725#define I_ADDA_UL_CH3 1826#define I_ADDA_UL_CH4 1927#define I_UL_PROX_CH1 2028#define I_UL_PROX_CH2 2129#define I_ADDA_UL_CH5 2430#define I_ADDA_UL_CH6 2531#define I_DMIC0_CH1 2832#define I_DMIC0_CH2 2933#define I_DMIC1_CH1 3034#define I_DMIC1_CH2 313536/* in port define >= 32 */37#define I_32_OFFSET 3238#define I_DL0_CH1 (32 - I_32_OFFSET)39#define I_DL0_CH2 (33 - I_32_OFFSET)40#define I_DL1_CH1 (34 - I_32_OFFSET)41#define I_DL1_CH2 (35 - I_32_OFFSET)42#define I_DL2_CH1 (36 - I_32_OFFSET)43#define I_DL2_CH2 (37 - I_32_OFFSET)44#define I_DL3_CH1 (38 - I_32_OFFSET)45#define I_DL3_CH2 (39 - I_32_OFFSET)46#define I_DL4_CH1 (40 - I_32_OFFSET)47#define I_DL4_CH2 (41 - I_32_OFFSET)48#define I_DL5_CH1 (42 - I_32_OFFSET)49#define I_DL5_CH2 (43 - I_32_OFFSET)50#define I_DL6_CH1 (44 - I_32_OFFSET)51#define I_DL6_CH2 (45 - I_32_OFFSET)52#define I_DL7_CH1 (46 - I_32_OFFSET)53#define I_DL7_CH2 (47 - I_32_OFFSET)54#define I_DL8_CH1 (48 - I_32_OFFSET)55#define I_DL8_CH2 (49 - I_32_OFFSET)56#define I_DL_24CH_CH1 (54 - I_32_OFFSET)57#define I_DL_24CH_CH2 (55 - I_32_OFFSET)58#define I_DL_24CH_CH3 (56 - I_32_OFFSET)59#define I_DL_24CH_CH4 (57 - I_32_OFFSET)60#define I_DL_24CH_CH5 (58 - I_32_OFFSET)61#define I_DL_24CH_CH6 (59 - I_32_OFFSET)62#define I_DL_24CH_CH7 (60 - I_32_OFFSET)63#define I_DL_24CH_CH8 (61 - I_32_OFFSET)6465/* in port define >= 64 */66#define I_64_OFFSET 6467#define I_DL23_CH1 (78 - I_64_OFFSET)68#define I_DL23_CH2 (79 - I_64_OFFSET)69#define I_DL24_CH1 (80 - I_64_OFFSET)70#define I_DL24_CH2 (81 - I_64_OFFSET)71#define I_DL25_CH1 (82 - I_64_OFFSET)72#define I_DL25_CH2 (83 - I_64_OFFSET)7374/* in port define >= 128 */75#define I_128_OFFSET 12876#define I_PCM_0_CAP_CH1 (130 - I_128_OFFSET)77#define I_PCM_0_CAP_CH2 (131 - I_128_OFFSET)78#define I_I2SIN0_CH1 (134 - I_128_OFFSET)79#define I_I2SIN0_CH2 (135 - I_128_OFFSET)80#define I_I2SIN1_CH1 (136 - I_128_OFFSET)81#define I_I2SIN1_CH2 (137 - I_128_OFFSET)8283/* in port define >= 192 */84#define I_192_OFFSET 19285#define I_SRC_0_OUT_CH1 (198 - I_192_OFFSET)86#define I_SRC_0_OUT_CH2 (199 - I_192_OFFSET)87#define I_SRC_1_OUT_CH1 (200 - I_192_OFFSET)88#define I_SRC_1_OUT_CH2 (201 - I_192_OFFSET)89#define I_SRC_2_OUT_CH1 (202 - I_192_OFFSET)90#define I_SRC_2_OUT_CH2 (203 - I_192_OFFSET)91#define I_SRC_3_OUT_CH1 (204 - I_192_OFFSET)92#define I_SRC_3_OUT_CH2 (205 - I_192_OFFSET)93#define I_SRC_4_OUT_CH1 (206 - I_192_OFFSET)94#define I_SRC_4_OUT_CH2 (207 - I_192_OFFSET)9596#endif979899