Path: blob/master/sound/soc/mediatek/mt8192/mt8192-dai-tdm.c
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// SPDX-License-Identifier: GPL-2.01//2// MediaTek ALSA SoC Audio DAI TDM Control3//4// Copyright (c) 2020 MediaTek Inc.5// Author: Shane Chien <[email protected]>67#include <linux/regmap.h>8#include <sound/pcm_params.h>910#include "mt8192-afe-clk.h"11#include "mt8192-afe-common.h"12#include "mt8192-afe-gpio.h"13#include "mt8192-interconnection.h"1415struct mtk_afe_tdm_priv {16int id;17int bck_id;18int bck_rate;19int tdm_out_mode;20int bck_invert;21int lck_invert;22int mclk_id;23int mclk_multiple; /* according to sample rate */24int mclk_rate;25int mclk_apll;26};2728enum {29TDM_OUT_I2S = 0,30TDM_OUT_DSP_A = 1,31TDM_OUT_DSP_B = 2,32};3334enum {35TDM_BCK_NON_INV = 0,36TDM_BCK_INV = 1,37};3839enum {40TDM_LCK_NON_INV = 0,41TDM_LCK_INV = 1,42};4344enum {45TDM_WLEN_16_BIT = 1,46TDM_WLEN_32_BIT = 2,47};4849enum {50TDM_CHANNEL_BCK_16 = 0,51TDM_CHANNEL_BCK_24 = 1,52TDM_CHANNEL_BCK_32 = 2,53};5455enum {56TDM_CHANNEL_NUM_2 = 0,57TDM_CHANNEL_NUM_4 = 1,58TDM_CHANNEL_NUM_8 = 2,59};6061enum {62TDM_CH_START_O30_O31 = 0,63TDM_CH_START_O32_O33,64TDM_CH_START_O34_O35,65TDM_CH_START_O36_O37,66TDM_CH_ZERO,67};6869static unsigned int get_tdm_wlen(snd_pcm_format_t format)70{71return snd_pcm_format_physical_width(format) <= 16 ?72TDM_WLEN_16_BIT : TDM_WLEN_32_BIT;73}7475static unsigned int get_tdm_channel_bck(snd_pcm_format_t format)76{77return snd_pcm_format_physical_width(format) <= 16 ?78TDM_CHANNEL_BCK_16 : TDM_CHANNEL_BCK_32;79}8081static unsigned int get_tdm_lrck_width(snd_pcm_format_t format)82{83return snd_pcm_format_physical_width(format) - 1;84}8586static unsigned int get_tdm_ch(unsigned int ch)87{88switch (ch) {89case 1:90case 2:91return TDM_CHANNEL_NUM_2;92case 3:93case 4:94return TDM_CHANNEL_NUM_4;95case 5:96case 6:97case 7:98case 8:99default:100return TDM_CHANNEL_NUM_8;101}102}103104static unsigned int get_tdm_ch_fixup(unsigned int channels)105{106if (channels > 4)107return 8;108else if (channels > 2)109return 4;110else111return 2;112}113114static unsigned int get_tdm_ch_per_sdata(unsigned int mode,115unsigned int channels)116{117if (mode == TDM_OUT_DSP_A || mode == TDM_OUT_DSP_B)118return get_tdm_ch_fixup(channels);119else120return 2;121}122123/* interconnection */124enum {125HDMI_CONN_CH0 = 0,126HDMI_CONN_CH1,127HDMI_CONN_CH2,128HDMI_CONN_CH3,129HDMI_CONN_CH4,130HDMI_CONN_CH5,131HDMI_CONN_CH6,132HDMI_CONN_CH7,133};134135static const char *const hdmi_conn_mux_map[] = {136"CH0", "CH1", "CH2", "CH3",137"CH4", "CH5", "CH6", "CH7",138};139140static int hdmi_conn_mux_map_value[] = {141HDMI_CONN_CH0,142HDMI_CONN_CH1,143HDMI_CONN_CH2,144HDMI_CONN_CH3,145HDMI_CONN_CH4,146HDMI_CONN_CH5,147HDMI_CONN_CH6,148HDMI_CONN_CH7,149};150151static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum,152AFE_HDMI_CONN0,153HDMI_O_0_SFT,154HDMI_O_0_MASK,155hdmi_conn_mux_map,156hdmi_conn_mux_map_value);157158static const struct snd_kcontrol_new hdmi_ch0_mux_control =159SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum);160161static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum,162AFE_HDMI_CONN0,163HDMI_O_1_SFT,164HDMI_O_1_MASK,165hdmi_conn_mux_map,166hdmi_conn_mux_map_value);167168static const struct snd_kcontrol_new hdmi_ch1_mux_control =169SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum);170171static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum,172AFE_HDMI_CONN0,173HDMI_O_2_SFT,174HDMI_O_2_MASK,175hdmi_conn_mux_map,176hdmi_conn_mux_map_value);177178static const struct snd_kcontrol_new hdmi_ch2_mux_control =179SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum);180181static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum,182AFE_HDMI_CONN0,183HDMI_O_3_SFT,184HDMI_O_3_MASK,185hdmi_conn_mux_map,186hdmi_conn_mux_map_value);187188static const struct snd_kcontrol_new hdmi_ch3_mux_control =189SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum);190191static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum,192AFE_HDMI_CONN0,193HDMI_O_4_SFT,194HDMI_O_4_MASK,195hdmi_conn_mux_map,196hdmi_conn_mux_map_value);197198static const struct snd_kcontrol_new hdmi_ch4_mux_control =199SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum);200201static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum,202AFE_HDMI_CONN0,203HDMI_O_5_SFT,204HDMI_O_5_MASK,205hdmi_conn_mux_map,206hdmi_conn_mux_map_value);207208static const struct snd_kcontrol_new hdmi_ch5_mux_control =209SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum);210211static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum,212AFE_HDMI_CONN0,213HDMI_O_6_SFT,214HDMI_O_6_MASK,215hdmi_conn_mux_map,216hdmi_conn_mux_map_value);217218static const struct snd_kcontrol_new hdmi_ch6_mux_control =219SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum);220221static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum,222AFE_HDMI_CONN0,223HDMI_O_7_SFT,224HDMI_O_7_MASK,225hdmi_conn_mux_map,226hdmi_conn_mux_map_value);227228static const struct snd_kcontrol_new hdmi_ch7_mux_control =229SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum);230231enum {232SUPPLY_SEQ_APLL,233SUPPLY_SEQ_TDM_MCK_EN,234SUPPLY_SEQ_TDM_BCK_EN,235SUPPLY_SEQ_TDM_EN,236};237238static int get_tdm_id_by_name(const char *name)239{240return MT8192_DAI_TDM;241}242243static int mtk_tdm_en_event(struct snd_soc_dapm_widget *w,244struct snd_kcontrol *kcontrol,245int event)246{247struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);248struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);249struct mt8192_afe_private *afe_priv = afe->platform_priv;250int dai_id = get_tdm_id_by_name(w->name);251struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];252253if (!tdm_priv) {254dev_warn(afe->dev, "%s(), tdm_priv == NULL", __func__);255return -EINVAL;256}257258dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x\n",259__func__, w->name, event);260261switch (event) {262case SND_SOC_DAPM_PRE_PMU:263mt8192_afe_gpio_request(afe->dev, true, tdm_priv->id, 0);264break;265case SND_SOC_DAPM_POST_PMD:266mt8192_afe_gpio_request(afe->dev, false, tdm_priv->id, 0);267break;268default:269break;270}271272return 0;273}274275static int mtk_tdm_bck_en_event(struct snd_soc_dapm_widget *w,276struct snd_kcontrol *kcontrol,277int event)278{279struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);280struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);281struct mt8192_afe_private *afe_priv = afe->platform_priv;282int dai_id = get_tdm_id_by_name(w->name);283struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];284285if (!tdm_priv) {286dev_warn(afe->dev, "%s(), tdm_priv == NULL", __func__);287return -EINVAL;288}289290dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x, dai_id %d\n",291__func__, w->name, event, dai_id);292293switch (event) {294case SND_SOC_DAPM_PRE_PMU:295mt8192_mck_enable(afe, tdm_priv->bck_id, tdm_priv->bck_rate);296break;297case SND_SOC_DAPM_POST_PMD:298mt8192_mck_disable(afe, tdm_priv->bck_id);299break;300default:301break;302}303304return 0;305}306307static int mtk_tdm_mck_en_event(struct snd_soc_dapm_widget *w,308struct snd_kcontrol *kcontrol,309int event)310{311struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);312struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);313struct mt8192_afe_private *afe_priv = afe->platform_priv;314int dai_id = get_tdm_id_by_name(w->name);315struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];316317if (!tdm_priv) {318dev_warn(afe->dev, "%s(), tdm_priv == NULL", __func__);319return -EINVAL;320}321322dev_dbg(cmpnt->dev, "%s(), name %s, event 0x%x, dai_id %d\n",323__func__, w->name, event, dai_id);324325switch (event) {326case SND_SOC_DAPM_PRE_PMU:327mt8192_mck_enable(afe, tdm_priv->mclk_id, tdm_priv->mclk_rate);328break;329case SND_SOC_DAPM_POST_PMD:330tdm_priv->mclk_rate = 0;331mt8192_mck_disable(afe, tdm_priv->mclk_id);332break;333default:334break;335}336337return 0;338}339340static const struct snd_soc_dapm_widget mtk_dai_tdm_widgets[] = {341SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0,342&hdmi_ch0_mux_control),343SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0,344&hdmi_ch1_mux_control),345SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0,346&hdmi_ch2_mux_control),347SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0,348&hdmi_ch3_mux_control),349SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0,350&hdmi_ch4_mux_control),351SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0,352&hdmi_ch5_mux_control),353SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0,354&hdmi_ch6_mux_control),355SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0,356&hdmi_ch7_mux_control),357358SND_SOC_DAPM_CLOCK_SUPPLY("aud_tdm_clk"),359360SND_SOC_DAPM_SUPPLY_S("TDM_EN", SUPPLY_SEQ_TDM_EN,361AFE_TDM_CON1, TDM_EN_SFT, 0,362mtk_tdm_en_event,363SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),364365SND_SOC_DAPM_SUPPLY_S("TDM_BCK", SUPPLY_SEQ_TDM_BCK_EN,366SND_SOC_NOPM, 0, 0,367mtk_tdm_bck_en_event,368SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),369370SND_SOC_DAPM_SUPPLY_S("TDM_MCK", SUPPLY_SEQ_TDM_MCK_EN,371SND_SOC_NOPM, 0, 0,372mtk_tdm_mck_en_event,373SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),374};375376static int mtk_afe_tdm_apll_connect(struct snd_soc_dapm_widget *source,377struct snd_soc_dapm_widget *sink)378{379struct snd_soc_dapm_widget *w = sink;380struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);381struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);382struct mt8192_afe_private *afe_priv = afe->platform_priv;383int dai_id = get_tdm_id_by_name(w->name);384struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai_id];385int cur_apll;386387/* which apll */388cur_apll = mt8192_get_apll_by_name(afe, source->name);389390return (tdm_priv->mclk_apll == cur_apll) ? 1 : 0;391}392393static const struct snd_soc_dapm_route mtk_dai_tdm_routes[] = {394{"HDMI_CH0_MUX", "CH0", "HDMI"},395{"HDMI_CH0_MUX", "CH1", "HDMI"},396{"HDMI_CH0_MUX", "CH2", "HDMI"},397{"HDMI_CH0_MUX", "CH3", "HDMI"},398{"HDMI_CH0_MUX", "CH4", "HDMI"},399{"HDMI_CH0_MUX", "CH5", "HDMI"},400{"HDMI_CH0_MUX", "CH6", "HDMI"},401{"HDMI_CH0_MUX", "CH7", "HDMI"},402403{"HDMI_CH1_MUX", "CH0", "HDMI"},404{"HDMI_CH1_MUX", "CH1", "HDMI"},405{"HDMI_CH1_MUX", "CH2", "HDMI"},406{"HDMI_CH1_MUX", "CH3", "HDMI"},407{"HDMI_CH1_MUX", "CH4", "HDMI"},408{"HDMI_CH1_MUX", "CH5", "HDMI"},409{"HDMI_CH1_MUX", "CH6", "HDMI"},410{"HDMI_CH1_MUX", "CH7", "HDMI"},411412{"HDMI_CH2_MUX", "CH0", "HDMI"},413{"HDMI_CH2_MUX", "CH1", "HDMI"},414{"HDMI_CH2_MUX", "CH2", "HDMI"},415{"HDMI_CH2_MUX", "CH3", "HDMI"},416{"HDMI_CH2_MUX", "CH4", "HDMI"},417{"HDMI_CH2_MUX", "CH5", "HDMI"},418{"HDMI_CH2_MUX", "CH6", "HDMI"},419{"HDMI_CH2_MUX", "CH7", "HDMI"},420421{"HDMI_CH3_MUX", "CH0", "HDMI"},422{"HDMI_CH3_MUX", "CH1", "HDMI"},423{"HDMI_CH3_MUX", "CH2", "HDMI"},424{"HDMI_CH3_MUX", "CH3", "HDMI"},425{"HDMI_CH3_MUX", "CH4", "HDMI"},426{"HDMI_CH3_MUX", "CH5", "HDMI"},427{"HDMI_CH3_MUX", "CH6", "HDMI"},428{"HDMI_CH3_MUX", "CH7", "HDMI"},429430{"HDMI_CH4_MUX", "CH0", "HDMI"},431{"HDMI_CH4_MUX", "CH1", "HDMI"},432{"HDMI_CH4_MUX", "CH2", "HDMI"},433{"HDMI_CH4_MUX", "CH3", "HDMI"},434{"HDMI_CH4_MUX", "CH4", "HDMI"},435{"HDMI_CH4_MUX", "CH5", "HDMI"},436{"HDMI_CH4_MUX", "CH6", "HDMI"},437{"HDMI_CH4_MUX", "CH7", "HDMI"},438439{"HDMI_CH5_MUX", "CH0", "HDMI"},440{"HDMI_CH5_MUX", "CH1", "HDMI"},441{"HDMI_CH5_MUX", "CH2", "HDMI"},442{"HDMI_CH5_MUX", "CH3", "HDMI"},443{"HDMI_CH5_MUX", "CH4", "HDMI"},444{"HDMI_CH5_MUX", "CH5", "HDMI"},445{"HDMI_CH5_MUX", "CH6", "HDMI"},446{"HDMI_CH5_MUX", "CH7", "HDMI"},447448{"HDMI_CH6_MUX", "CH0", "HDMI"},449{"HDMI_CH6_MUX", "CH1", "HDMI"},450{"HDMI_CH6_MUX", "CH2", "HDMI"},451{"HDMI_CH6_MUX", "CH3", "HDMI"},452{"HDMI_CH6_MUX", "CH4", "HDMI"},453{"HDMI_CH6_MUX", "CH5", "HDMI"},454{"HDMI_CH6_MUX", "CH6", "HDMI"},455{"HDMI_CH6_MUX", "CH7", "HDMI"},456457{"HDMI_CH7_MUX", "CH0", "HDMI"},458{"HDMI_CH7_MUX", "CH1", "HDMI"},459{"HDMI_CH7_MUX", "CH2", "HDMI"},460{"HDMI_CH7_MUX", "CH3", "HDMI"},461{"HDMI_CH7_MUX", "CH4", "HDMI"},462{"HDMI_CH7_MUX", "CH5", "HDMI"},463{"HDMI_CH7_MUX", "CH6", "HDMI"},464{"HDMI_CH7_MUX", "CH7", "HDMI"},465466{"TDM", NULL, "HDMI_CH0_MUX"},467{"TDM", NULL, "HDMI_CH1_MUX"},468{"TDM", NULL, "HDMI_CH2_MUX"},469{"TDM", NULL, "HDMI_CH3_MUX"},470{"TDM", NULL, "HDMI_CH4_MUX"},471{"TDM", NULL, "HDMI_CH5_MUX"},472{"TDM", NULL, "HDMI_CH6_MUX"},473{"TDM", NULL, "HDMI_CH7_MUX"},474475{"TDM", NULL, "aud_tdm_clk"},476{"TDM", NULL, "TDM_BCK"},477{"TDM", NULL, "TDM_EN"},478{"TDM_BCK", NULL, "TDM_MCK"},479{"TDM_MCK", NULL, APLL1_W_NAME, mtk_afe_tdm_apll_connect},480{"TDM_MCK", NULL, APLL2_W_NAME, mtk_afe_tdm_apll_connect},481};482483/* dai ops */484static int mtk_dai_tdm_cal_mclk(struct mtk_base_afe *afe,485struct mtk_afe_tdm_priv *tdm_priv,486int freq)487{488int apll;489int apll_rate;490491apll = mt8192_get_apll_by_rate(afe, freq);492apll_rate = mt8192_get_apll_rate(afe, apll);493494if (!freq || freq > apll_rate) {495dev_warn(afe->dev,496"%s(), freq(%d Hz) invalid\n", __func__, freq);497return -EINVAL;498}499500if (apll_rate % freq != 0) {501dev_warn(afe->dev,502"%s(), APLL cannot generate %d Hz", __func__, freq);503return -EINVAL;504}505506tdm_priv->mclk_rate = freq;507tdm_priv->mclk_apll = apll;508509return 0;510}511512static int mtk_dai_tdm_hw_params(struct snd_pcm_substream *substream,513struct snd_pcm_hw_params *params,514struct snd_soc_dai *dai)515{516struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);517struct mt8192_afe_private *afe_priv = afe->platform_priv;518int tdm_id = dai->id;519struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[tdm_id];520unsigned int tdm_out_mode = tdm_priv->tdm_out_mode;521unsigned int rate = params_rate(params);522unsigned int channels = params_channels(params);523unsigned int out_channels_per_sdata =524get_tdm_ch_per_sdata(tdm_out_mode, channels);525snd_pcm_format_t format = params_format(params);526unsigned int tdm_con = 0;527528/* calculate mclk_rate, if not set explicitly */529if (!tdm_priv->mclk_rate) {530tdm_priv->mclk_rate = rate * tdm_priv->mclk_multiple;531mtk_dai_tdm_cal_mclk(afe,532tdm_priv,533tdm_priv->mclk_rate);534}535536/* calculate bck */537tdm_priv->bck_rate = rate *538out_channels_per_sdata *539snd_pcm_format_physical_width(format);540541if (tdm_priv->bck_rate > tdm_priv->mclk_rate)542dev_warn(afe->dev, "%s(), bck_rate > mclk_rate rate", __func__);543544if (tdm_priv->mclk_rate % tdm_priv->bck_rate != 0)545dev_warn(afe->dev, "%s(), bck cannot generate", __func__);546547dev_dbg(afe->dev, "%s(), id %d, rate %d, channels %d, format %d, mclk_rate %d, bck_rate %d\n",548__func__,549tdm_id, rate, channels, format,550tdm_priv->mclk_rate, tdm_priv->bck_rate);551552dev_dbg(afe->dev, "%s(), out_channels_per_sdata = %d\n",553__func__, out_channels_per_sdata);554555/* set tdm */556if (tdm_priv->bck_invert)557regmap_update_bits(afe->regmap, AUDIO_TOP_CON3,558BCK_INVERSE_MASK_SFT,5590x1 << BCK_INVERSE_SFT);560561if (tdm_priv->lck_invert)562tdm_con |= 1 << LRCK_INVERSE_SFT;563564if (tdm_priv->tdm_out_mode == TDM_OUT_I2S) {565tdm_con |= 1 << DELAY_DATA_SFT;566tdm_con |= get_tdm_lrck_width(format) << LRCK_TDM_WIDTH_SFT;567} else if (tdm_priv->tdm_out_mode == TDM_OUT_DSP_A) {568tdm_con |= 1 << DELAY_DATA_SFT;569tdm_con |= 0 << LRCK_TDM_WIDTH_SFT;570} else if (tdm_priv->tdm_out_mode == TDM_OUT_DSP_B) {571tdm_con |= 0 << DELAY_DATA_SFT;572tdm_con |= 0 << LRCK_TDM_WIDTH_SFT;573}574575tdm_con |= 1 << LEFT_ALIGN_SFT;576tdm_con |= get_tdm_wlen(format) << WLEN_SFT;577tdm_con |= get_tdm_ch(out_channels_per_sdata) << CHANNEL_NUM_SFT;578tdm_con |= get_tdm_channel_bck(format) << CHANNEL_BCK_CYCLES_SFT;579regmap_write(afe->regmap, AFE_TDM_CON1, tdm_con);580581if (out_channels_per_sdata == 2) {582switch (channels) {583case 1:584case 2:585tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;586tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT1_SFT;587tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT;588tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;589break;590case 3:591case 4:592tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;593tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;594tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT;595tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;596break;597case 5:598case 6:599tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;600tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;601tdm_con |= TDM_CH_START_O34_O35 << ST_CH_PAIR_SOUT2_SFT;602tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;603break;604case 7:605case 8:606tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;607tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;608tdm_con |= TDM_CH_START_O34_O35 << ST_CH_PAIR_SOUT2_SFT;609tdm_con |= TDM_CH_START_O36_O37 << ST_CH_PAIR_SOUT3_SFT;610break;611default:612tdm_con = 0;613}614} else {615tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;616tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT1_SFT;617tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT;618tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;619}620621regmap_write(afe->regmap, AFE_TDM_CON2, tdm_con);622623regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,624HDMI_CH_NUM_MASK_SFT,625channels << HDMI_CH_NUM_SFT);626return 0;627}628629static int mtk_dai_tdm_set_sysclk(struct snd_soc_dai *dai,630int clk_id, unsigned int freq, int dir)631{632struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);633struct mt8192_afe_private *afe_priv = afe->platform_priv;634struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai->id];635636if (!tdm_priv) {637dev_warn(afe->dev, "%s(), tdm_priv == NULL", __func__);638return -EINVAL;639}640641if (dir != SND_SOC_CLOCK_OUT) {642dev_warn(afe->dev, "%s(), dir != SND_SOC_CLOCK_OUT", __func__);643return -EINVAL;644}645646dev_dbg(afe->dev, "%s(), freq %d\n", __func__, freq);647648return mtk_dai_tdm_cal_mclk(afe, tdm_priv, freq);649}650651static int mtk_dai_tdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)652{653struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);654struct mt8192_afe_private *afe_priv = afe->platform_priv;655struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai->id];656657if (!tdm_priv) {658dev_warn(afe->dev, "%s(), tdm_priv == NULL", __func__);659return -EINVAL;660}661662/* DAI mode*/663switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {664case SND_SOC_DAIFMT_I2S:665tdm_priv->tdm_out_mode = TDM_OUT_I2S;666break;667case SND_SOC_DAIFMT_DSP_A:668tdm_priv->tdm_out_mode = TDM_OUT_DSP_A;669break;670case SND_SOC_DAIFMT_DSP_B:671tdm_priv->tdm_out_mode = TDM_OUT_DSP_B;672break;673default:674tdm_priv->tdm_out_mode = TDM_OUT_I2S;675}676677/* DAI clock inversion*/678switch (fmt & SND_SOC_DAIFMT_INV_MASK) {679case SND_SOC_DAIFMT_NB_NF:680tdm_priv->bck_invert = TDM_BCK_NON_INV;681tdm_priv->lck_invert = TDM_LCK_NON_INV;682break;683case SND_SOC_DAIFMT_NB_IF:684tdm_priv->bck_invert = TDM_BCK_NON_INV;685tdm_priv->lck_invert = TDM_LCK_INV;686break;687case SND_SOC_DAIFMT_IB_NF:688tdm_priv->bck_invert = TDM_BCK_INV;689tdm_priv->lck_invert = TDM_LCK_NON_INV;690break;691case SND_SOC_DAIFMT_IB_IF:692default:693tdm_priv->bck_invert = TDM_BCK_INV;694tdm_priv->lck_invert = TDM_LCK_INV;695break;696}697698return 0;699}700701static const struct snd_soc_dai_ops mtk_dai_tdm_ops = {702.hw_params = mtk_dai_tdm_hw_params,703.set_sysclk = mtk_dai_tdm_set_sysclk,704.set_fmt = mtk_dai_tdm_set_fmt,705};706707/* dai driver */708#define MTK_TDM_RATES (SNDRV_PCM_RATE_8000_48000 |\709SNDRV_PCM_RATE_88200 |\710SNDRV_PCM_RATE_96000 |\711SNDRV_PCM_RATE_176400 |\712SNDRV_PCM_RATE_192000)713714#define MTK_TDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\715SNDRV_PCM_FMTBIT_S24_LE |\716SNDRV_PCM_FMTBIT_S32_LE)717718static struct snd_soc_dai_driver mtk_dai_tdm_driver[] = {719{720.name = "TDM",721.id = MT8192_DAI_TDM,722.playback = {723.stream_name = "TDM",724.channels_min = 2,725.channels_max = 8,726.rates = MTK_TDM_RATES,727.formats = MTK_TDM_FORMATS,728},729.ops = &mtk_dai_tdm_ops,730},731};732733static struct mtk_afe_tdm_priv *init_tdm_priv_data(struct mtk_base_afe *afe)734{735struct mtk_afe_tdm_priv *tdm_priv;736737tdm_priv = devm_kzalloc(afe->dev, sizeof(struct mtk_afe_tdm_priv),738GFP_KERNEL);739if (!tdm_priv)740return NULL;741742tdm_priv->mclk_multiple = 512;743tdm_priv->bck_id = MT8192_I2S4_BCK;744tdm_priv->mclk_id = MT8192_I2S4_MCK;745tdm_priv->id = MT8192_DAI_TDM;746747return tdm_priv;748}749750int mt8192_dai_tdm_register(struct mtk_base_afe *afe)751{752struct mt8192_afe_private *afe_priv = afe->platform_priv;753struct mtk_afe_tdm_priv *tdm_priv;754struct mtk_base_afe_dai *dai;755756dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);757if (!dai)758return -ENOMEM;759760list_add(&dai->list, &afe->sub_dais);761762dai->dai_drivers = mtk_dai_tdm_driver;763dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_tdm_driver);764765dai->dapm_widgets = mtk_dai_tdm_widgets;766dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_tdm_widgets);767dai->dapm_routes = mtk_dai_tdm_routes;768dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_tdm_routes);769770tdm_priv = init_tdm_priv_data(afe);771if (!tdm_priv)772return -ENOMEM;773774afe_priv->dai_priv[MT8192_DAI_TDM] = tdm_priv;775776return 0;777}778779780